SDM INSTITUTE OF TECHNOLOGY, UJIRE

I Internal Assessment Test

VERILOG HDL (18EC56)
V Sem A. ECE Dept Time: 1 hour Max. marks: 30
Instructions:
(1) Write your USN, Name, Subject Code, Subject Title and append your signature on
the top of the answer script. Mention page number at the bottom of every page
without fail.
(2) Save in one single PDF format by giving the name of the file ‘USN_first IA_Subject
code.pdf’
(3) Email the scanned PDF file to varunsk@sdmit.in (Cell No. 9480716174 ) within 15
minutes after completion of the test.
Answer ONE full question from PART A and ONE full question from PART B

Q. No. Marks
PART A
1 (a) Draw the diagram of typical HDL design flow and elaborate each block
10
in few words.
(b) Apply the Bottom-Up design methodology for the design of 4:1 MUX
using 2:1 MUX. 5
OR
2 (a) Design 4-Bit Ripple carry adder using 1-bit Full adder and explain the
design block and simulation block. 10
(b) Mention the two styles of stimulus application of component of a
simulation. With the example explain the same. 5

PART B
3 (a) List the Data types used in the Verilog HDL. Explain with examples. 10
(b) Declare the following variables in Verilog.
1. An &bit vector net called a-in.
2. An integer called count.
3. A time variable called snap-shot.
4. An array called delays. Array contains 20 elements of the type
integer.
5. A parameter cache-size equal to 512. 5

OR
4 (a) Design SR-Flipflop using basic gates. Write the module definition for
this module. Include the list of ports and port declarations. 10
(b) With an examples elaborate port connections rules. 5