Roll No:

K. L. N. COLLEGE OF ENGINEERING, POTTAPALAYAM 630612

(An Autonomous Institution, Affiliated to Anna University, Chennai)

B.E. / B.Tech Programme

Third Semester
Information Technology
CS8351 - DIGITAL PRINCIPLES AND SYSTEM DESIGN
(Regulation 2017)
Centralized Internal Test – II– October 2020

Date / Duration: 15.10.2020 / 50 Minutes Maximum: 25 Marks

I. Course Outcomes, Question Numbers, Marks

COs CO1 CO2 CO3 CO4 CO5
Q. Nos. 1,2,6.b,7.b 3,4,5,6.a,7.a
Marks (40) 14 26

II. Knowledge Levels

Remember Understand Apply Analysis Evaluate Create
Level
(K1) (K2) (K3) (K4) (K5) (K6)
Q. Nos. 1,2,4,5 6(a) 6(b),7(a&b) 3
Marks (40) 8 10 20 2
Answer ALL Questions
PART – A (5× 2 = 10 Marks)

1. Show the logic diagram of Full adder using half adders. [K1]
2. What is priority encoder? [K1]
3. Distinguish between synchronous and asynchronous counter. [K4]
4. What is Johnson counter? [K1]
5. List out the difference between Latch & flipflop. [K1]
PART – B (1× 15 = 15 Marks)
6. (a) A Sequential circuit has two JK flip-flops A and b and one input x. The 10 [K2]
circuit is described by the following equations
JA= x, KA= B, JB=x, KB=A’
i)Derive the state equations A(t+1) and B(t+1)
ii) Draw the state diagram
(b) Construct a full adder using decoder. 05 [K3]
(Or)
7. (a) Construct a MOD -9 Synchronous Counter using JK flip-flops. 10 [K3]

(b) Construct a full subtractor using MUX 05 [K3]