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 Proposal of a Photovoltaic AC-Module with
a Single-Stage Transformerless Grid-
Connected Boost Microinverter (STBM)
Fernando C. Melo, Lucas S. Garcia, Luiz C. Freitas, Ernane A. A. Coelho, Valdeir J. Farias
and Luiz C. G. Freitas
Abstract-- Microinverters for photovoltaic modules can
improve the energy generation by reducing the effects of
shading, since the energy harvesting of each PV module
can be controlled individually. In this context, this paper
presents a topology of single-stage transformerless grid-
connected Boost microinverter (STBM). It promotes high
voltage gain without using a pre-regulator circuit or a
high/low frequency transformer. A 500 W laboratory
prototype was implemented and experimental tests were
carried out so that the proposed Microinverter was
evaluated in a grid-connected PV system. Experimental
analysis was performed in order to corroborate the
theoretical approach and to verify the effectiveness of the
proposed Modified P&O “Gama” MPPT technique and the
Proportional-Resonant (P-Res) grid current controller
under different irradiation conditions and under partial
shading.
Index Terms-- AC-Modules, Inverters, Microinverter,
Photovoltaic, Solar Energy.
I. INTRODUCTION
M ICROINVERTERS for low power systems and
photovoltaic (PV) modules can improve the energy
generation by reducing the effects of shading, compared to
string inverters, since the energy harvesting of each PV
module can be controlled individually [1]-[3]. Solar
microinverters are also called Module Integrated Converter
(MIC) since it is integrated into each PV module [1]. The
MICs found commercially are designed to be connected to PV
modules with low voltage, around 25 to 60 VMPP, and injecting
energy to a single-phase power grid (127 Vrms). In this
context, it is worth noting some benefits gained by this
equipment, such as [1]-[5]:
• Improved utilization of collected energy through
maximum power point tracking (MPPT) techniques for each
module or for a maximum of two PV modules connected in
series;
Manuscript received March 10, 2017; revised July 26, 2017;
accepted August 21, 2017. This work was supported by CNPq
(Process 406845/2013-1, 472457/2013-6, 304252/2013-1,
304307/2013-0) and FAPEMIG (Process APQ-01219-13, TEC-PPM-
00031-14)
F. C. Melo, L. C. Freitas, E. A. A. Coelho, V. J. Farias, L. C. G.
Freitas are with the Núcleo de Pesquisa em Eletrônica de Potência,
Universidade Federal de Uberlândia, Faculdade de Engenharia
Elétrica, Uberlândia 38400-902, Brazil (e-mail:
fernandocardoso101@gmail.com, lcgfreitas@yahoo.com.br).
L. S. Garcia is with the Departamento de Ciências Exatas e
Tecnológicas, Universidade Estadual de Santa Cruz, Ilhéus, Bahia,
Brazil, 45662-900.
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• Plug-and-play operation, justifying the installation
simplicity;
• Increased flexibility and modularity in PV installations
allowing future expansion of generation capacity according to
the consumer’s needs and the capital to be invested;
• High power density with low weight, which is an
important feature for rooftop PV systems;
• Improved safety since the dc cable length can be reduced,
coming down from the roof only ac cables and the grounding
conductor.
Concerning commercial MICs topologies, one can observe
that, generally, isolated converters are used, lowering the
efficiency, lifetime and increasing the costs. On the other
hand, the so called transformerless inverters can operate with
high switching frequencies, reducing reactive elements and
heat dissipation. Then, one can produce converters with lower
weight, volume and cost. Another very common feature in
commercial MICs is that they have two power stages, one
step-up dc-dc converter and a dc-ac converter (inverter) for
powering local loads and/or for grid connection [3], [6]- [7].
In the literature are found various single-stage topologies
that were reviewed in [3], such as non-isolated Boost inverter
with four switches. In this converter, the ac output voltage is
obtained from the difference of the outputs of two dc-dc boost
converters with a common source that have sinusoidal
waveforms displaced of 180º. In other words, each boost
converter generates a half-cycle of the output sinusoidal
voltage waveform. Another topology uses two Buck-Boost
converters that provide each half-cycle of the output voltage
from a dc symmetrical source. One can observe another
single-stage topology with four switches and zero current
switching (ZCS) named as Resonant Buck-Boost.
In [8] is presented two single-stage inverters: one for step-
down, composed by a typical Voltage Source Inverter (VSI)
with a LCL output filter and the other is for step-up
applications with a CL filter (Current Source Inverter - CSI).
Moreover, are presented topologies that operate as step-down
and step-up, such as the Z-Source Inverter and the Natural
Soft-Switching Inverter.
In [9] a topology of voltage inverter that can operate as a
step-up or a step-down converter with only one power
processing stage and transformerless is presented. Great
results were shown, being evaluated considering off-grid
applications.
In this context, the quest for increasing efficiency and
lowering costs, which can be achieved by reducing the number
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of solid-state devices, has motivated the development of the
proposed Single-Stage Transformerless Boost Microinverter
(STBM). The structure presented in [10] and illustrated in Fig.
1 was developed for stand-alone application. The main
operational feature observed is the high output voltage gain,
since it affords Boost operating mode with totally controlled
sinusoidal output voltage and input inductors currents, without
using any transformer, neither High Frequency (HF) nor Low
Frequency (LF). Additionally, it has reduced number of
switches and diodes.
Fig. 1. Single-stage Transformerless Boost Inverter for stand-alone
application.
The main contribution of this paper is to propose the
STBM, shown in Fig. 2(a) that was designed and evaluated
considering the grid-tied application. A wide supply voltage
range can also be afforded, making the proposed inverter
suitable for AC-Module applications and/or photovoltaic
systems where various configurations of PV modules in series
and/or in parallel connection can be used. Therefore,
commercial ac voltage of 127 Vrms can be provided to local
loads or the mains supply from a low voltage supply.
The STBM is different from the previous one (Fig.1) in
terms of its control structure, which was developed
exclusively for this CSI topology, highlighting the
implementation of the Modified P&O “Gama” MPPT
algorithm; the establishment of a novel operating principle
with just three stages for each half-cycle; the PLL (Phase-
Locked Loop) digitally implemented; and the design of a grid
current control that depends on the output capacitor voltage
imposition for injection of active power into the grid, ensuring
a high power factor, low THDI and high efficiency. Besides, in
this paper, it was performed the average state space modeling
of the converter structure for defining the best grid current
controller using the Proportional-Resonant (P-Res).
Concerning the converter topology, two Boost inductors L1
and L2 are used in a single-stage topology and was added the
coupling inductor to the grid Lgrid. Each one operates in its
respective half-cycle of the sinusoidal output voltage
waveform. While the proposed STBM injects sinusoidal
energy into the grid, the second harmonic component is
reflected on the side of the PV source. For assuring low PV
array voltage ripple (lower than 8.5%) with the aim of not
compromising the MPPT efficiency (higher than 98%), a high
decoupling capacitor (3mF) connected in parallel to the PV
array is required (CPV). This issue can also be found in
important papers recently published [3], [4], [6], [8], [9], [11],
[13] showing that high decoupling capacitors is an inherent
characteristic of single-stage solar inverter topologies. Despite
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the good results presented, one must observe that when high
decoupling capacitors were not deployed, a switched DC
power supply was used instead of real photovoltaic modules or
solar emulators. In Section IV these works are also compared
with other topologies taking into account the number of
switches, the number of power processing stage and others
performance indicators.
Finally, to present the work developed, this paper is
organized as follows. In Section II the authors describe the
three operational stages. In Section III the authors present the
Modified P&O “Gama” MPPT Algorithm, which is based on
the disturbance of the reference current of Boost inductors.
The method used to obtain the grid-current reference Iref grid is
also presented as well as the modeling of the STBM and the
design of the P-Res current controller. In Section IV the
authors present the main experimental results corroborating to
the theoretical approach. Additionally, considering that the
leakage current is a major concern in transformerless inverter
topologies, preliminary analysis is also included. The results
of experimental evaluation of the leakage current are
presented and compared to related works found in the
specialized literature.
II. OPERATING PRINCIPLE
The operating principle of the proposed STBM can be
understood based on Fig. 2(a). Basically, the control strategy
follows two rules, i.e: PV array voltage control through the
Boost inductors current imposition, and grid current control
through the output capacitor voltage imposition. As shown in
Fig. 2 (b), the Current Control Strategy is based on the current
imposition on inductors L1 and L2, given by IREF* variable,
which is the control signal necessary for generating a current
with shape analogous to the ac instantaneous power
waveform. It is used for both inductors, and its amplitude is
adjusted by the MPPT algorithm that will be described in
Section III (Boost1 and Boost2 operational stages, for positive
and negative half-cycles, respectively). The Voltage Control
Strategy provides the VREF variable, which is the control signal
necessary for adjusting the amplitude, frequency and
waveform of the output capacitor voltage VC, as illustrated in
Fig. 2(c) (V+ operational stage).
In synthesis, we have:
 The control variable C+ defines when the half-cycle
of the output voltage is positive (C+ = 1 and C- = 0,
enabling switches S1 and S4) or negative (C+ = 0 and
C- = 1, enabling switches S2 and S3) and is generated
through the comparison between VREF and 0.
 The control variable V+ defines when is required to
increase (V+ = 1 or V- = 0, enabling switches S1 and
S4) or decrease (V+ = 0 or V- = 1, enabling switches
S3 and S4) the output voltage VC and is generated
through the comparison between VREF and VC.
 The control variable Boost1 defines when is required
to increase (Boost1 = 1, enabling switches S1, S3 and
S4) or decrease (Boost1 = 0, enabling switches S3 and
S4 or switches S1 and S4, depending on the operational
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stage), the inductor L1 current and is generated
through the comparison between signals IREF* and IL1
(for the positive half-cycle).
The control variables described above define the required
switching patterns summarized in Table I and illustrated in
Figure 3. For example, for the positive half-cycle of the grid
voltage, and Boost1 and V+ operational stage (Case 1), the
switches S1, S3 and S4 are enabled, because it is a combination
of three enabled variables (C+, Boost1 and V+).
For the STBM operating connected to the grid, a third
operational stage has been added, which is illustrated in
Fig. 2(d). Therefore, if the control signals V+ and Boost are
disabled, the reference signals IREF* and VREF are adjusted for
decoupling the input circuit from the output since there is no
requirement for increasing the output voltage magnitude.
The schematic diagram of the microinverter with the
Modified P&O “Gama” MPPT algorithm generating the
variable IREF* and the grid current control loop is presented in
Fig. 2(a). In this figure is possible to verify that the reference
current is subtracted from the grid current. Then, the resulting
error goes through the proportional, integral and resonant parts
of the controller (P-Res). The results are added generating a
reference voltage for the STBM output voltage (VREF). The
reference voltage has a sinusoidal waveform and is in
synchronism with the ac grid voltage. This reference is
adjusted by the controller in order to inject a sinusoidal current
into the grid.

(a)

(b) (c) (d)

Fig. 2. (a) Schematic diagram of the STBM with the Modified P&O “Gama” MPPT algorithm and grid current control loop composed by the
Proportional-Resonant controller; (b) Boost1 operational stage (control variable C+ = 1); (c) Operational stage of increasing the output capacitor
voltage during the positive half-cycle (control variables C+ = 1 and V+ = 1) and inductor L1 energy transference to the mains supply; (d)
Operational stage during the positive half-cycle that is performed the decoupling of PV array circuit and the output filter connected to the grid,
occurring also the complete interruption of the leakage current path.
TABLE I
OPERATIONAL STAGES AND CONTROL ACTION
Status Switches Status Control Action
Case Operational
C+ V+ Boost1 S1 S2 S3 S4
Mode
Positive Half-Cycle of VC
1 1 1 1 1 0 1 1 Boost1 and V+
2 1 1 0 1 0 0 1 V+
V- (Freewheeling
3 1 0 0 0 0 1 1
stage)
Negative Half-Cycle of VC
4 0 1 0 0 1 1 1 Boost2 and V+
5 0 1 0 0 1 1 0 V+
V- (Freewheeling
6 0 0 0 0 0 1 1
stage)

Fig 3. Switching pattern for a cycle of the grid voltage.

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A. Boost Operational Stage (Case 1)
As shown in Fig. 2(b), the Boost1 operational stage occurs in
the positive half-cycle of the output voltage VC and concerns
the current imposition in inductor L1, defined as IL1, so that it
follows IREF* waveform. For this imposition, switches S1 and
S3 are enabled. Switch S4 is also enabled maintaining the
inductor L2 in freewheeling, being a combination of Boost1 and
V+ variable operation. When the current IL1 amplitude is
greater than the reference signal IREF*, its decrease is carried
out by combining Voltage and Current Control techniques,
enabling switches S1 and S4. As illustrated in Fig. 2(c), the
decrease of IL1 occurs during the energy transference from
inductor L1 to the output capacitor C after closing switches S1
and S4.
During this operational stage occurs the interruption of
leakage current path, due to the high impedance offered. More
details referring to this matter are presented in Section IV.
B. Capacitor Output Voltage Control (Case 2)
In order to obtain a high output voltage gain, the Current
Control must ensure the appropriate current imposition for
storing the required energy in inductor L1, for the positive half-
cycle, and in inductor L2 for the negative half-cycle of the
output voltage VC. A hysteresis controller, through the
comparison of VREF and VC signals, results in two
complementary digital control variables, V+ and V-, and
performs the output voltage imposition. These variables
comprise the VC signal, which is obtained by the output
voltage sampled and follows the reference signal VREF that is
generated by the current controller, presented in Section III.
The VREF signal has a 60 Hz frequency synchronized to the
mains supply and the hysteresis controller has the following
operation:
 VREF > VC: V+ is defined with high logic level and V-
is defined with low logic level (enabling switches S1
and S4);
 VREF < VC: V+ is defined with low logic level and V-
is defined with high logic (enabling switches S3 and
S4).
The V+ variable represents the need to increase the output
voltage and V- its decrease. As presented in Table I, these
variables will only start their procedure if they are related to
the control logic that depends on variables C+ and C-,
declared with the purpose of controlling the half-cycle
operation of VC. The control variable C+ defines when the
half-cycle of the output voltage is positive (C+ = 1 and C- = 0,
enabling switches S1 and S4) or negative (C+ = 0 and C- = 1,
enabling switches S2 and S3) and is generated through the
comparison between VREF and 0. The current path created,
which is shown in Fig. 2(c) (V+ stage of operation), performs
the VC voltage increase when switches S1 and S4 are turned on.
The decrease of the output voltage VC, in its turn, occurs when
V- variable is enabled for the positive half-cycle.
C. Decoupling Operational Stage (Case 3)
The third stage consists in decoupling the PV array from the
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circuit formed by the output filter CL and the mains voltage, as
shown in Fig. 2(d). Thus, switches S3 and S4 are closed and S1
and S2 are opened, for maintaining inductors L1 and L2 currents
in freewheel, allowing its decrease through the very low
intrinsic resistances of the inductors and the semiconductor
devices, i.e., diodes and MOSFETs. Despite that, this amount
of energy proved to be very low in the light of the efficiency
levels achieved and presented in Section IV [3]. One can also
observe that the PV array charges the CPV capacitor.
One can highlight the importance of this stage since there
has not a defined circuit for discharging the excess of energy
of both inductors to follow the imposed reference and to avoid
distortions on the injected current into the grid. During this
stage, the output capacitor voltage VC decreases through the
energy transference to the inductive filter and the grid. In order
to maintain the system control stability, this stage is enabled in
both half-cycles of the output voltage and when V and Boost
control variables are disabled, characterizing the V- control
action.
Another advantage of this operational stage is the
interruption of the leakage current path, due to the high
impedance offered. More details referring to this matter are
presented in Section IV. Table I presents the three cases of
operational stages for the positive half-cycle of the output
voltage, as shown in Figs. 2 (b), (c) and (d), and the three cases
for the negative. Moreover, are presented the corresponding
switches status for each case.
III. CONTROL STRATEGY DESIGN
In this Section are presented details on the proposed MPPT
algorithm, reference current Iref grid definition control loop,
microinverter design and the P-Res compensator design.
A. Modified P&O “Gama” MPPT Technique
The Perturb and Observe (P&O) method has the function of
tracking the maximum power point (MPP) of a PV array in a
fast and reliable manner [12]. The STBM was implemented
with a Modified P&O “Gama” MPPT technique, which is
based on the perturbation of inductors L1 and L2 current
reference for controlling the PV array voltage VPV, as
portrayed in the block diagram of Fig. 4.
Fig. 4. Control loop responsible for extracting the maximum power
from the PV array by perturbing the reference current of Boost
inductors.
For each condition that a change in the variable Gama is
required, it is multiplied by an ac instantaneous power
waveform with unitary peak value (IREF) that comes from the
output of the PLL control loop [13]. This waveform promotes
higher efficiency for the structure. After the definition of a
new current reference IREF*, this is compared to the inductor
current IL1 changing Boost1 status, with high or low logic level,
for the positive half-cycle. For the negative half-cycle, variable
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Boost2 is changed. The higher the current imposition
performed in the respective Boost inductor the lower will be
the voltage VPV amplitude and, vice versa, since more power
from the PV array is required.
The operating principle of the MPPT algorithm is presented
in the flowchart of Fig. 5. After the measurement of VPV
voltage and IPV current, and obtaining the PV array power PPV,
the proposed MPPT algorithm perturbs the Gama variable for
ΔI equal to 0.1.
Fig. 5. Flowchart of the Modified P&O “Gama” MPPT algorithm.
B. Reference Current Iref grid Definition as a Function of
PV Array Power
The current reference to be injected in the grid depends on
the available power in the PV array, which is evaluated and
tracked by the MPPT algorithm. For obtaining the waveform
of grid reference current, the controller requires the peak value
of the current to be imposed in the coupling inductor Lgrid [14].
Therefore, considering the input power (PPV) equal to the
output power Pgrid, i.e., disregarding any losses, and that the
injected current is in phase with the mains voltage, it is
obtained (1).
√2. .
(1)
where is the grid reference current peak value, is the
PV array current, is the PV array voltage and
the RMS grid voltage. Figure 6 illustrates the block diagram
for generating the reference current Iref grid, which peak value
follows the previously defined conditions and it is multiplied
by a sinusoidal waveform obtained from the PLL control loop
output with the purpose of phase and frequency
synchronization to the grid.
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Fig. 6. Block diagram for obtaining the reference current Iref grid for the
injected current control loop based on the power generated by the PV
array.
C. STBM Modeling
The proposed grid-connected STBM modeling was made
using the Average State Space technique, considering the
Boost1 and V+ operational stages and its respective circuits,
for the positive half-cycle of the grid voltage. The transfer
function relating the grid injected current
with the output capacitor voltage is given by (2). This
function is necessary for modeling the current controller,
which is presented in the next topic.
1
(2)
.
D. Grid Current Controller – Design of P-Res Controller
The proportional resonant controller (P-Res) type II has
lower sensitivity to variations in grid connection impedance.
This controller has the advantage compared to an ordinary PI
compensator of tracking the sinusoidal current reference to be
injected into the grid with zero steady-state error, which would
not occur using an ordinary PI compensator. It has this
capability once the gain is high at the grid frequency (center
frequency) and has a transfer function equal to the Laplace
transform of a generic sine. It is known that the error is equal
zero when placing a reference model in the control process
gain. [15]. The respective transfer function is given
by (3). The parameters presented in Table II were determined
adjusting its gains through trial and error.
2. . . .
(3)
2. . .
where and are PI (Proportional-Integrator) compensator
gains; is the angular resonance frequency for the grid
frequency (60 Hz); is the damping factor; regulates the
width of the resonant peak ( . ).
TABLE II
P-RES CONTROLLER PARAMETERS
Parameters Value
40
300
377 rad/s (60 Hz)
Damping Factor 0.025
9.425 rad/s (1.50 Hz)
is Since the proposed STBM is a single-stage CSI structure, is
required the control of the output capacitor voltage, composing
an internal voltage loop. Therefore, the power flow to the grid
can assured. Although the proposed control strategy is not
commonly used, it can control the variable ILgrid with low
THDI, through the outer current control based on P-Res. This
controller defines the Vref, which is a sinusoidal voltage
reference, as portrayed in the block diagram illustrated in
Fig. 7. This reference voltage is compared to the sensed output
capacitor voltage VC in the hysteresis control loop that has
unitary gain (internal voltage control loop). One can note that
the higher the imposed voltage on the output capacitor, the
greater will be the grid current amplitude and, vice-versa,
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keeping the power flow from the inverter to the grid. One can
also observe that the impedance between the output capacitor
and the mains voltage is given by the coupling inductor
( . and by the local loads connected
to the point of common coupling (PCC).
Figure 8 shows the frequency response of the P-Res
controller cascaded with the transfer function in
open loop. One can identify the P-Res controller has the
characteristic response of a bandpass filter tuned to the central
frequency equal to 60 Hz (grid frequency). Moreover, one can
verify that the response gain margin is infinite and the phase
margin is 88.7 degrees at 708 Hz. During the experimental
evaluation using the DSP, the P-Res Type II controller proved
to be very robust after being tuned at the grid frequency and in
its respective operating point (nominal output current, ILgrid).
Fig. 7. Block diagram of the control loop of the injected current into the
grid.
prototype developed in laboratory, highlighting the power
circuit board and the Solar Array Simulator (SAS) E4361A
from Keysight® used during the initial stage of tests. The first
prototype was assembled with the heavy and bulky inductors
and electrolytic capacitors available in laboratory. Obviously,
for implementing a smaller final product more efforts are
required for restructuring the hardware. It is estimated that the
new prototype will have the following specifications:
300x340x100 mm and weight of, approximately, 10 kg. The
Boost inductors will be redesigned with a toroidal core, with
lower inductance not compromising is performance. It is well
known that electrolytic capacitors are responsible for lowering
the lifetime of the inverter and a solution is using film
capacitors that can provide a long lifetime and high reliability
[11].
The second part of the tests was carried out under real
operating conditions of irradiance and PV module temperature.
In Fig. 9(b) is shown a picture from the rooftop of the
laboratory where are installed the PV modules used in the
experimental tests. From 48 PV modules installed, only two
from Amerisolar 250 Wp were used.

Fig. 8. Bode magnitude and phase plots of the P-Res compensator

cascaded with the transfer function . (a)

IV. EXPERIMENTAL RESULTS

For validating the theoretical approach, experimental
analysis has been carried out. Table III presents the
specifications of the implemented prototype.
TABLE III
EXPERIMENTAL PARAMETERS FOR THE STBM
Design Specifications
RMS Output Voltage, VO(rms) = 127 V
Input Voltage, VMP = 60.6 V – Input power, PPV = 500 Wp (b)
Maximum switching frequency, fs = 25 kHz Fig. 9. (a) Illustration of the prototype assembled in laboratory and (b)
Microinverter Power Circuit Specifications PV modules installed on the roof of the laboratory, being used only two
Inductors, L1 and L2 = 360 µH, 40 A Amerisolar PV modules of 250 Wp each.
Grid Inductor, Lgrid = 9 mH
Input Capacitor, CPV = 3 mF
Output Capacitor, C = 10 µF The first experimental test was conducted through the I-V
Switches, S1 – S2, IRFP4868 and P-V curves obtained from Solar Array Simulator E4361A
Switches, S3 – S4, IRFP4768 using the specifications of two PV modules Yingli YL245P-
Diodes, D1 – D4, STTH200L04TV
Microcontroller, DSP TMS320F28335
29b connected in series under irradiance condition of 1000
W/m2 operating at 25ºC. One can observe that the grid voltage
A. Grid-Connected STBM Experimental Results and current waveforms (power factor equal to 0.993) and the
For implementing the complete control strategy, shown in inductors currents L1 and L2 and, also presents the PV array
Fig. 2(a) was used the DSP microcontroller Texas emulator screen, demonstrating the maximum efficiency of the
Instruments® TMS320F28335. Figure 9(a) shows the MPPT algorithm of 99.24% (extracting 450.27 W) in Figs. 10

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(a) and (b).
(a)
(b)
Fig. 10 STBM fed by SAS configured with two 245 Wp Yingli PV
modules operating at 25ºC and 1000 W/m2: (a) Grid voltage, injected
current and Boost inductors currents; (b) I-V and P-V curves and MPPT
efficiency.
For illustrating an irradiance transition, the SAS equipment
was configured with I-V and P-V curves from two Yingli
YL245P-29b connected in series operating at 25 ºC. The
transient irradiance test was made for a variation from
600 W/m2 to 1000 W/m2, presented in Fig. 11, increasing the
injected current amplitude and the available PV power.
Fig. 11. Irradiance step from 600 W/m2 to 1000 W/m2, showing the grid
voltage and injected current. Below, are shown the PV array voltage
and current.
The STBM converter was also tested under partial shadings
that can be caused by nearby buildings, trees, among others.
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For validating the proposed Modified P&O “Gama” MPPT
algorithm, was performed a partial shading in just one of the
two PV modules from the Amerisolar array (250Wp each), as
shown in Fig. 12 (a). The weather conditions of this test were
at 1033W/m2 and modules temperature at 55.1ºC. Both
modules are connected in series, being the string characterized
using the Solar I-V from HT Instruments® and the collected
data were inserted in the SAS for testing this condition. The
resulting I-V and P-V curves are presented in Fig. 12 (b),
which also shows the inverter extracting the maximum power,
which is the red dot on the I-V curve (Pmax = 309.05 W).
(a)
(b)
Fig. 12. (a) Partial shading in just one Amerisolar PV module of the
array and (b) the resulting I-V and P-V curves, showing the inverter
extracting the maximum power indicated by the red dot in the I-V curve.
B. Leakage Current Evaluation
As well known, there is a parasitic capacitance (CP) formed
between the terminals of the PV array and the module frame
which is generally grounded. Due to the electric potential
difference (common mode voltage) imposed by the inverter
switching actions [16], a leakage current may flow through the
galvanic connection between the grounding of the PV array
and the grid. Accordingly, as observed in [17] and considering
the case of a PV array, it is formed a resonant circuit between
the parasitic capacitance, the output filter, the inverter and the
grid impedance. This current flowing through the system can
increase the system losses, rising the electromagnetic
interference (EMI), causing safety problems and distortions in
the injected current into the grid [18]. The German standard
DIN VDE 0126-1-1 states that if the leakage current is greater
than 30 mA (rms), the inverter must be disconnected from the
grid within 0.3 seconds.
The CP of polycrystalline silicon PV modules is estimated at
50 and 150 nF/kW and up to 1μF/kW for thin film modules
considering both for large ungrounded PV arrays [18]-[19],
depending on environmental conditions. Considering that the
STBM operates with a PV array of 500 Wp (two 250 Wp PV
modules connected in series), the CP was set to 50 nF, as
shown in Table VI.
The proposed STBM topology presents two operational
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stages (freewheeling) in which is blocked the connection
between the PV array and the output filter including the grid,
i.e., the dc decoupling method is applied as illustrated in
Figs. 2(b) and (d). Therefore, these stages can avoid the high
frequency variations of common mode voltage on the parasitic
capacitance (VCP) through the leakage current path
interruption, minimizing it. This technique is also applied in
transformerless topologies, such as Highly Efficient and
Reliable Inverter Concept (HERIC), H5 and H6. The STBM
can be simplified as the equivalent circuit shown in Fig. 13
[20]-[21], presenting the ground current path.
Fig. 13. Equivalent circuit for the STBM showing the leakage current
ICm path.
It is known that the common mode voltage VCm of the
inverter is the average of voltages VAN and VBN in relation to
the ground according to (4).
(4)
2 increasing the efficiency and maintaining the ICm and dc
In case a VCm variation occurs, the leakage current will flow
through the ground path of the parasitic capacitance CP to the
grid, as illustrated in Fig. 12. In Table IV is presented the
common mode voltage determined for each operational stage,
considering the positive half-cycle: Boost1 and V+, V+ and V-.
One can observe that Cases 1 and 3 present a common mode
voltage of -VC/2, where VC is the output capacitor voltage
being the sum of -VC and -VL1, since it is a CSI topology. Case
2 presents a common mode voltage different from the previous
ones, generating a positive voltage of VC/2, where VC is the
output capacitor voltage being the sum of VPV and VL1.
TABLE IV
COMMON MODE VOLTAGE FOR EACH OPERATIONAL STAGE (POSITIVE
HALF-CYCLE)
Operational Stages Common Mode Voltage
Case 1: Boost1 and V+ ⇒
2 2
Case 2: V+ ⇒
2 2
Case 3: V- ⇒
2 2
conditions, i.e., using two Amerisolar PV modules installed at
the laboratory roof as shown in Fig. 11 (a) and the results are
presented for irradiance at 864W/m2, PV modules temperature
at 50ºC and ambient temperature at 35ºC. The leakage current
measurement has been performed on the ac side that is
connected to the grid via the line and neutral conductors
(127 Vrms). Both line and neutral conductors were involved in
the current probe from Tektronix (A622). The experimental
results presented in Fig. 15 shows that the leakage current of
the proposed topology has 22.9 mA (rms), which is in
accordance to DIN VDE 0126-1-1. It is important to
emphasize that the frame of PV modules used in this test was
grounded, reducing the CP and hence the leakage currents [18].
For comparing the analyzed transformerless topologies
presented in Section I and the ones studied in Section IV, i.e.,
H4 (conventional H-Bridge); HERIC; H5; H6; Six Switches
and Two Diodes transformerless inverters [20]-[21]; and,
finally the proposed STBM, Table V shows the parasitic
capacitance CP used in the tests, number of switches and
power stages, measured leakage current and the maximum
efficiency.
According to renowned reference [22], transformerless
topologies were exclusively developed by manufacturers for
current injection in the safety limits, such as H5 and HERIC.
However, the STBM is a novel single-stage topology and
presents similar results, as depicted in Table V. For example,
the topology HERIC presented, through simulation analysis,
132 mA rms and STBM presented 198 mA rms. Obviously, in
order to develop a commercial equipment, the authors would
have to deploy more efforts for mitigating the leakage currents
as required by standard DIN VDE 0126-1-1.

For validating the theory exposed, a simulation test was

carried out considering the estimated parasitic capacitance CP
of 50 nF installed in the positive (CP1) and negative (CP2) poles
of the PV array composed by two Amerisolar 250 Wp PV
modules connected in series, under irradiance of 864 W/m2
and PV modules temperature of 50ºC. Figure 14 shows the
grid voltage, grid current, parasitic capacitors voltages VCP1 Fig. 14. Simulation results for the STBM operating in irradiance at
and VCP2, the common mode voltage VCm and the leakage 864 W/m2, PV modules temperature at 50ºC and ambient temperature
at 35ºC, presenting the grid voltage, grid current, parasitic capacitors
current ICm, being its respective rms value around 198 mA. voltages, common mode voltage VCm and the leakage current ICm
In this paper, preliminary experimental analysis concerning waveforms.
the leakage current has been performed under real operating

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which can mitigate the predominant harmonics in the grid

current spectrum, such as the 3rd, 5th and 7th harmonic orders.
Another experimental test was carried out considering that the
grid voltage THDV is equal to 3.12% before the startup of the
STBM. The grid current THDI results of both controllers P-
Res and P-Res+HC is equal to, respectively, 4.55% and
4.07%. Therefore, it is possible to note that the performance of
both controllers is practically the same.

Fig. 15. STBM operating at irradiance at 864 W/m2, PV modules

temperature at 50ºC and ambient temperature at 35ºC. Grid and PV
array voltages and below is presented the leakage current waveform.

C. Efficiency and Grid Current Harmonic Distortion

Analysis
Finally, measurement of efficiency for different output
power values have been made. The PV array operating
conditions were kept the same, with two 245 Wp connected in
series connection at 1000 W/m2 and 25ºC (STC), as shown in
Fig. 16. Thus, for an output power range from 77 W to
Fig. 16. Efficiency curve as a function of the output power, considering
432.9 W, was found that the maximum structure efficiency is the input power a PV array with 490 Wp operating in STC.
above 90% reaching its peak at 93%, for the output power of
223 W. Furthermore, through the efficiency curve it is possible
to provide the European and CEC weighted efficiencies, being
its values respectively, 87.66% and 90.26%.
One can verify in Fig. 17 that the individual harmonic
components of odd orders up to the 33th order are following
the limits established by IEEE 1547-2008 standard. This
standard defines the minimum requirements for the
interconnection of distributed sources in Electric Power
Systems. One can note that the voltage THD at the point of
common coupling was equal to 2.76% before the inverter
connection to the grid. For the rated operating condition, the
converter presented an injected current THDI equal to 4.49 %, Fig. 17. Harmonic content of the injected current compared to the
in conformance to the IEEE 929-2000, and Brazilian standards IEEE 1547-2008 requirements.
ABNT NBR 16149 and ABNT NBR 16150.
The outer grid current control loop can be easily altered
adding the HC (Harmonic Compensator) to the P-Res [14],
TABLE V
COMPARISON OF TRANSFORMERLESS INVERTERS INCLUDING THE PROPOSED STBM
Parasitic
Number of Number of Power Measured Leakage Maximum
Topology Capacitance
Switches Stages Current (mA rms) Efficiency (%)
(CP) / kW
Non-isolated Boost Inverter [3] **** 4 1 **** ****
Buck-Boost Inverter [3] **** 4 1 **** 80
Resonant Buck-Boost Inverter [3] **** 4 1 **** ****
Voltage Source Inverter (VSI) – LCL output filter [8] **** 4 1 **** ****
Current Source Inverter (CSI) – CL output filter [8] **** 4 1 **** ****
Step-up/Step-Down [9] **** 4 1 **** 89.375
H4 [20] * 100 nF 4 1 472 ****
HERIC [20] * 100 nF 6 1 132 ****
H5 [21] ** 100 nF 5 1 27.6 94.68
H6 [20] * 100 nF 6 1 92 ****
Six Switches and Two Diodes Inverter [21] ** 100 nF 6 1 17.4 94.75
22.9 (Experimental)
STBM (Proposed Topology) ** 50 nF*** 4 1 93
198 (Simulation)
*Only simulation results.
**Simulation and Experimental results.
*** STBM tested for a PV array of 500 Wp.
**** Not reported by the authors.

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V. CONCLUSIONS
A topology of Single-Stage Transformerless Boost
Microinverter Grid-Connected (STBM) with reduced number
of switches and diodes was presented in this paper. The output
voltage VC is fully controlled and its high gain is provided
without the need of a dedicated dc-dc converter and/or a
transformer. This topology can be applied in stand-alone
installations and, also, in grid-connected systems. High
efficiency and reduced costs can be achieved due to the
reduced number of components.
Experimental results corroborated with the developed
control strategy. Fully controlled output current with low
harmonic distortion (4.49%) under rated power and transient
operation conditions were obtained and proved to be in
accordance with IEEE 1547-2008, IEEE 929-2000 and
Brazilian standards ABNT NBR 16149 and ABNT NBR
16150. In addition, the reliability of the Proportional-Resonant
(P-Res) compensator was studied and proved to be satisfactory
in tracking the sinusoidal grid reference. The MPPT efficiency
was also evaluated and the results show that values of 99%
were achieved, proving the reliability of the proposed P&O
Modified “Gama” method. The STBM topology presents two
operational stages that decouples the PV array from the output
filter and the grid. During the Boost and Decoupling stages,
the leakage current path is interrupted, therefore mitigating it.
Preliminary experimental analysis of the leakage current was
performed and satisfactory results were achieved.
ACKNOWLEDGMENT
The authors wish to thank the financial support for this
project provided by CNPq (Process 406845/2013-1,
472457/2013-6, 304252/2013-1, 304307/2013-0) and
FAPEMIG (Process APQ-01219-13, TEC-PPM-00031-14).
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Fernando C. Melo was born in Uberlândia-MG,
Brazil, in 1989. He received the B.Sc. degree in
electrical engineering and the M.Sc. degree
from the Universidade Federal de Uberlândia
(UFU), Uberlândia, Brasil, in 2012 and 2014,
respectively.
He is currently a doctoral student at the same
institution and is a member of the Núcleo de
Pesquisa em Eletrônica de Potência (NUPEP).
His research interests the following subjects:
single-stage inverters, stand-alone and grid-
connected photovoltaic systems, MPPT (Maximum Power Point
Tracking), microinverters, boost converters and power factor
correction.
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Lucas S. Garcia was born in Araraquara, São
Paulo, Brazil, in 1984. He received the B.Sc.,
M.Sc. and Ph.D. degrees in electrical
engineering from the Universidade Federal de
Uberlândia (UFU), Uberlândia, Brazil, in 2008,
2010 and 2015, respectively.
Currently he is Assistant Professor Level A of
the Universidade Estadual de Santa Cruz where
he also develops research projects and
scientific initiation. He has experience in the
area of Power Electronics and is a member of the Núcleo de Pesquisa
em Eletrônica de Potência (NUPEP), where he is a doctoral co-
advisor, working mainly in the following subjects: energy management,
stand-alone systems, photovoltaic inverters, inverters applied to fuel
cell and single-stage inverters with uninterruptible power supply.
establish research and education activities with regard to power
electronics.
His research interests include high-frequency power conversion,
active power factor correction techniques, hybrid rectifiers, power
quality, clean power applications, power electronics converter, and
control technique for renewable energies source-based systems and
microgrids.
Dr. Freitas received a Prize Paper Award from the IEEE Industry
Application Society-Industrial Automation and Control Committee for
his contribution in the hybrid rectifiers field in 2012. He is a member of
the Brazilian Society of Power Electronics (SOBRAEP).

Luiz C. de Freitas was born in Monte Alegre-

MG, Brazil, on April 1, 1952. He received the
M.Sc. and Ph.D. degrees from the Universidade
Federal de Santa Catarina, Florianópolis, Brazil,
in 1985 and 1992, respectively.
He is currently an Associate Professor at the
Universidade Federal de Uberlândia,
Uberlândia, Brazil, where since 1991, he has
been a founder member of the Núcleo de
Pesquisa em Eletrônica de Potência. He has
authored a variety of papers particularly in the areas of soft-switching,
dc–dc, dc–ac, and ac–dc converters, electronic fluorescent ballasts,
and multipulse power rectifier for clean power systems. His work has
been published at the IEEE Power Electronics Specialists Conference
(PESC) in 1992, the IEEE Applied Power Electronics Conference in
1993, the PESC in 1993, and the IEEE TRANSACTIONS ON POWER
ELECTRONICS, January 1995. His research interests include the
evolution of a zero-voltage turn ON and turn OFF commutation cell that
has been largely applied in power electronics research.

Ernane A. A. Coelho was born in Teófilo Otoni-

MG, Brazil, in 1962. He received the B.Sc.
degree in electrical engineering and the Ph.D.
degree from the Universidade Federal de Minas
Gerais, Belo Horizonte, Brazil, in 1987 and
2000, respectively, and the M.Sc. degree from
the Universidade Federal de Santa Catarina,
Florianopolis, Brazil, in 1989.
He is currently with the Núcleo de Pesquisa
em Eletrônica de Potência, Universidade
Federal de Uberlândia, Uberlândia, Brazil, where since 2001, he has
been a Professor member. His research interests include parallel
connection of pulse width modulated inverters, power factor correction,
and digital control by microcontrollers and DSPs.

Valdeir J. Farias was born in Araguari, Brazil,

in 1947. He received the B.Sc. degree in
electrical engineering from the Universidade
Federal de Uberlândia, Uberlândia, Brazil, in
1975, the M.Sc. degree in power electronics
from the Universidade Federal de Minas Gerais,
Belo Horizonte, Brazil, in 1981, and the Ph.D.
degree from Universidade Estadual de
Campinas, Campinas, Brazil, in 1989.
He is currently a Researcher with the Núcleo
de Pesquisa em Eletrônica de Potência, Universidade Federal de
Uberlândia, where since 1991, he has been a founder member. His
research interests include power electronics, in particular, soft-
switching converters and active power filters.

Luiz C. G. de Freitas received the B.Sc., M.Sc.,

and Ph.D. degrees in electrical engineering from
the Universidade Federal de Uberlândia (UFU),
Uberlandia, Brazil, in 2001, 2003, and 2006,
respectively. Since 2008, he has been with the
Núcleo de Pesquisa em Eletrônica de Potência,
(NUPEP), where he has been working to

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