RECONFIGURATION OF SRAM FOR FPGA BASED

APPLICATIONS

A Report
submitted in partial fulfilment of the requirements for
the award of the Degree of

MASTER OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION
(VLSI DESIGN)
BY: Under Guidance Of:
Anjali Kumari Tarun Varma
(2019PEV5114)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

MALAVIYA NATIONAL INSTITUTE OF TECHNOLOGY
JAIPUR
2020-21
Paper 1:
A Low-Cost and High-Throughput FPGA Implementation of the
Retinex Algorithm for Real-Time Video Enhancement :-
Retinex Algorithm is used to enhance the part of the image that is too dark to distinguish
details while maintaining the remaining part with the same brightness. Required for
video applications in a special environment such as medical imaging, space exploration,
and underwater exploration.

Fig. 1. Block diagram of the proposed architecture.

The working of each module is described as follows. The separate RGBL module
separates the intensity channel from the input image. The intensity channel is created
by taking the maximum value of the RGB channel. The Gaussian filter module
convolves the intensity channel with the predefined Gaussian kernel to create the F
channel, which is used for illumination estimation. The weighting map generation
module calculates the weight values that are used in the calculate Fm module, which
modifies the F channel to calculate the modified illumination channel (i.e., Fm
channel). The RGB creation module divides the Fm channel from the RGB channels of
the original image in a pixel-wise manner to create the reflectance channels RR, GR,
and BR, respectively. The calculate Fenh module performs adaptive gamma correction
with operations including exponentiation by using Fm and the average of intensity
channels. Finally, the Fenh channel and reflectance channels, RR, GR, and BR are
multiplied to create the output channel.

Fig. 2. Block diagram depicting output image of each module.

In this paper we can further reduce computational complexity, and improve throughput.
Required tool: FPGA

Paper 2:
Fast Content Updating Algorithm for an SRAM-Based
TCAM on FPGA:-
Static random-access memory (SRAM)-based ternary content-addressable memory
(TCAM), an alternative to traditional TCAM, where inclusion of SRAM improves the
memory access speed, scalability, cost, and storage density compared to conventional
TCAM. The proposed updating algorithm for SRAM-based TCAM consumes least
possible clock cycles to update a ternary word. 2w clock cycles are consumed to update
a single TCAM word while the updating latency of the proposed updating algorithm
varies with number of don’t care bits in TCAM word. For further improvement, Hybrid
partitioning is used. The overall architecture of the proposed updating algorithm is
composed of address generator, MUX, and UM.

Fig.3. Layer architecture of modules representing proposed updating algorithm.

Further we can improve High latency , Bits and Power consumption of Updating
Algorithm. Required Tool: FPGA.

PAPER 3:
Low Power, Reliable, and Nonvolatile MSRAM Cell for
Facilitating Power Gating and Nonvolatile Dynamically
Reconfiguration
This paper proposes a new nonvolatile magnetic random access memory (MRAM)-
backed SRAM (MSRAM) cell with the aim of fast write operation and nonvolatile data
storage. The proposed cell is composed of a high-performance SRAM cell backed by a
nonvolatile as well as high performance MRAM part. This cell can be used in
reconfigurable memory units of the future FPGAs in order to implement nonvolatile
and also high-performance designs. To have a fast enough write operation, the MTJs
are controlled by voltage during switching and the STT switching method is applied.
The proposed MSRAM cell comprising the SRAM and MRAM parts can operate in
one of the four modes of active (for read/write), holding, sleep, and restore.
Fig. 4. Proposed MSRAM cell that offers a nonvolatile and high-performance Operation.

Paper 4:
Adaptive Proactive Reconfiguration: A Technique for
Process Variability- and Aging-Aware SRAM Cache Design
Nanoscale circuits are subject to a wide range of new limiting phenomena making
essential to investigate new design strategies at the circuit and architecture level to
improve its performance and reliability. Proactive reconfiguration is an emerging
technique oriented to extend the system lifetime of memories affected by aging. Cache
memories are usually designed with several spare columns/rows to substitute the failing
ones for yield improvement purposes. Using spare parts and built-in circuit test
procedures (after manufacturing or in-field), a reconfiguring scheme allows the
substitution of defective parts by spare ones, resulting in a self repairing fault-tolerant.
This principle is called reactive configuration. Process variability is a reliability related
issue, which has gained a significant importance at nanoscale level circuit design. It is
mainly caused by advanced manufacturing process and is divided into two major types,
i.e., systematic and random deviations.
Fig. 5. (a) Architecture used for implementation of the adaptive proactive reconfiguration technique in a
1-kB SRAM cache. (b) One example of proactive SRAM column.

Adaptive proactive approach extends the system lifetime larger than the former (IBM)
proactive approach. Using monitoring circuit that tracks the time zero process variation
and BTI aging of SRAM cells during operation. With an adaptive proactive
reconfiguration it is possible to extend the memory lifetime between 2X and 5X.

Paper 5:
A Reduced Store/Restore Energy MRAM-Based SRAM Cell
for a Non-Volatile Dynamically Reconfigurable FPGA
A novel low-power, low-area nonvolatile (NV) static random access memory (SRAM)
that uses a single magnetic tunneling junction for store/restore operation. The proposed
cell is dynamically reconfigurable in the background, which makes it a proper
alternative to replace the SRAM cells of conventional field programmable gate arrays
(FPGAs) for the development of NV-FPGAs. NV-SRAM cells can be developed by
adding the features from some emerging non-volatile structures such as spin transfer
torque magnetic random access memory (STT-MRAM), resistive RAM (Re-RAM) or
phase change RAM (PC-RAM) to the standard SRAM cell

Fig.6. NV-SRAM cell (MRAM-backed SRAM cell structure).

This circuit offers a fast read/write operations and includes a nonvolatile backed part.
This cell can be employed as the memory units of the next generation FPGAs. The
FPGA can restore its last state and hence, a better power management is applicable for
that FPGA.

Paper 6:
An FPGA-Based Phase Measurement System
Phase measurement is required in electronic applications where a synchronous
relationship between the signals needs to be preserved. The phase measurement logic
can operate over a wide range of digital clock frequencies, ranging from a few kilohertz
to the maximum frequency that is supported within the FPGA fabric. High-speed serial
transceivers of FPGA’s do not maintain constant phase shift with each round of power
cycle, reset cycle, loss of lock in the transceiver [3], firmware upgrade, or aging of
clock circuitry in phase-locked loop (PLL). A logic design for phase monitoring
capability to register phase shift changes in the range of 20–100 ps is needed inside the
FPGA circuitry. This would allow to extract the relative phase information and to
recalibrate the system when needed, to maintain the constant phase relationships. In
this paper, a new approach for an accurate phase measurement in an FPGA using
subsamples collected by the systematic sampling over XOR-based phase detector (PD)
signal.

Fig. 7. VLSI architecture of phase measurement instrumentation inside FPGA.

A phase detection logic core for FPGA, having precision, accuracy, and resolution in
the range of a few picoseconds. This can be used within FPGA as a monitoring device
of phase relationship between digital clock pulses, without any additional circuitry.

Paper 7:
SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based
on 10T Low-Power SRAMs
It used the concept of temporal logic folding and fine-grain (e.g., cycle-level) dynamic
reconfiguration to increase logic density by an order of magnitude. This dynamic
reconfiguration is done intra-circuit rather than inter-circuit. However, the previous
design of NATURE required fine-grained distribution of nano RAMs throughout the
field-programmable gate array (FPGA) architecture. we present a NATURE
architecture that is based on CMOS logic and CMOS SRAMs that are used for on-chip
dynamic reconfiguration. We use fast and low-power SRAM blocks that are based on
10T SRAM cells. We hide the dynamic reconfiguration delay behind the computation
delay through the use of shadow SRAM cells. A hybrid CMOS/ nanotechnology
reconfigurable architecture, called NATURE, was proposed to solve two main
problems: logic density and efficiency of run-time reconfiguration. NATURE is based
on CMOS logic and high-speed, high density nano RAMs. It enables the concept of
temporal logic folding, which is similar to the temporal pipelining concept used in
dynamically programmable gate arrays, but is based on a comprehensive FPGA
architecture that facilitates fine-grain run-time reconfigurability.

Fig. 8. 10T SRAM cell.

Fig. 9. High-level view of the SRAM-based NATURE architecture.

The architecture uses low-power 10T SRAM as storage for the configuration bits. The
peripheral circuits of the 10T SRAM were simplified to reduce power consumption.

From above study I conclude that we can reconfigure SRAM cell to improve
performance.
Our Proposed Work:
CIRCUIT:

Fig.10. Schematic of single inverter. Fig.11. VTC curve and current of single inverter.

Fig.12. The schematic of single SRAM cell model. Fig.13. The VTC curve of SRAM in write operation.