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Digital Systems: 14.1 Latches and Flip-Flops
Digital Systems: 14.1 Latches and Flip-Flops
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Timing Diagram RS Flip-Flop (cont’d.)
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• Preset, P
• Clear, C
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Data Latch (Delay) D Flip-Flop
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JK Flip-Flop
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JK Flip-Flop Rules JK Flip-Flop (cont’d.)
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• Counter • 23 = 8 possible
– Sequential logic device states
– Takes one of N possible states • Reset input can
• Steps through the states sequentially force the counter
– Resets to zero after reaching the last state outputs low
• Decade counter
– Counts from zero to nine and then resets
– Can be cascaded to represent any series of
decimal digits
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3-Bit Binary Ripple Counter Divide-By-8 Circuit
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Parallel-Input Parallel-Output Register
Registers
(cont’d.)
• Cascade of flip-flops each storing one bit • Load input pulse causes the parallel inputs
of binary data b0b1b2b3 to be transferred to the respective
• Parallel input-parallel output register flip-flops
– Load input pulse acts on all clocks • Binary word b3b2b1b0 is stored
simultaneously – Each bit represented by flip-flop state
• Register preserves stored word until new
load input appears
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State Diagram Example State Transition Table Example
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Example: Design of a Modulo-4 Binary Up- Example: Design of a Modulo-4 Binary Up-
Down Counter Down Counter (cont’d.)
• Specification given in the state diagram • Choose two RS flip-flops
shown • Create the state transition table shown
– Counter output limited to integers 0 to 3 – First five columns match information in state
– Counter can increment or decrement diagram
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14.4 Computer System Architecture Computer System Architecture (cont’d.)
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