Analog and Digital VLSI Design

(EEE/ INSTR F313)

BITS Pilani Instructor : Dr. KAVINDRA KANDPAL

Pilani Campus
Note:

Dear Students follow Kang section 3.5 for short channel

effects.

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Example SCE

Consider a case of generalized scaling, where moving from

technology node A to B, all the dimensions are scaled down
by a factor of 8 and electric field scales up by a factor of 4.

Consider technology node A faces velocity saturation.

Find out power density and frequency of operation of new

process technology B in terms of power density and
frequency A.

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Example SCE
Consider a case of generalized scaling, where moving from
technology node A to B, all the dimensions are scaled down by
a factor of 8 and electric field scales up by a factor of 8.

Consider technology node A in nominal operation does not

face velocity saturation.

Find out power density and frequency of operation of new

process technology B in terms of power density and frequency
A.

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Limitation imposed by Technology Scaling

● Drain Induced Barrier lowering (DIBL)

● Subthreshold leakage (as VT is reduced)

 
2
W  kT  q (Vgs VT ) / m kT
I ds   eff C ox (m  1)  e 1  e  qVds / kT
L  q 
● Threshold voltage roll-off. 𝑆𝑆 = 𝑉𝑡ℎ𝑒𝑟𝑚𝑎𝑙 𝑙𝑛10 1 +
𝐶𝑑𝑚
𝐶𝑜𝑥

● Hot electron injection, VT shift

● Oxide breakdown, Oxide leakage

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DIBL

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Gate dielectric for ultra-thin gate MOSFET

 Within the next few years gate dielectric thickness will be scaled
to below 20 Å
 This is approaching the fundamental limit for proper circuit
operation.
 Supply voltage has not scaled proportionately according to the
classical scaling theory.
 Degradation and breakdown is caused due to electrical stress.
Therefore lifetime and reliability of such ultrathin dielectric
films may be a show stopper in the evolution of the current
technology.
The content of this lecture in its currernt form are taken from
https://web.stanford.edu/class/ee311/NOTES/GateDielectric.pdf, Prof. K. Sarswat, Stanford university lecture
notes . Text book : 2.5.2 - 2.5.6

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Quantum mechanical tunneling

a) Fowler-Nordheim tunneling (b) Direct tunneling.

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Estimation of Interconnect Parasitics

 Main components of the

output load

 Internal parasitic capacitances

of transistors
 Interconnect capacitances
 Input capacitances of the fan-
out gates

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The Transmission-line Models

l
 rise  fall   2.5     transmission-line modeling
 v
l  l  either transmission-line 
2.5      rise  fall   5      
v  v  or lumped modeling 
l
 rise  fall   5     lumped modeling
  v

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Interconnect Delay

100
Gate delay

Local wire
Relative Delay 10 Global wire w/ repeaters

Global wire

0.1
250 180 130 90 65 45 32

Process Technology Node (nm)

 Dealing with the implications and optimizing a system for

speed
 Estimating the interconnect parasitics in a large chip
 Simulating the transient effects.
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Interconnect Capacitance Estimation

 The total parasitic capacitance

 The section of a single interconnect

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Interconnect Resistance Estimation

 Total resistance in indicated current direction

l l 
Rwire    Rsheet  
wt  w

 The sheet resistivity


of the line
Rsheet   
t 

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RC Delay Models

 Simple lumped RC model & T-model

  t 
Vout  t   VDD 1  exp   
  RC  
   
V50%  VDD 1  exp   PLH 
  RC 

 PLH  0.69 RC

 Distributed RC ladder network model

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Various RC Models

R R/2 R/2
Vin Vout Vin Vout

C C

(a) lumped RC model (b) T-model

R/4 R/2 R/4 R

Vin V out Vin Vout

C/2 C/2 C/2 C/2

(c) T2-model (d) π-model

R/2 R/2 R/3 R/3 R/3

Vin Vout Vin Vout

C/4 C/2 C/4 C/6 C/3 C/3 C/6

(e) π2-model (f) π3-model

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