Topstar S42C - Rev A

5 4 3 2 1
Topstar Digital technologies Co.,LTD

D D
Board name: Mother Board Schematic 1. System Block Diagram & Schematic page description;
Project name: S42G 2. Power Block Diagram & Discription;
Version: VerD 3. Annotations & information;
Release Date: Jan.08, 2008 4. Schematic modify Item and history;
5. Power on & off Sequence;
C
6. ACPI Mode Switch Timings; C
7. Power On Sequence Map;

8. CLOCK Distribution;
9. Power Distribution;
Topstar Confidential
B
Hardware drawing by: Hardware check by: EMI Check by: B
Power drawing by: Power check by:
Manager Sign by:
TOPSTAR TECHNOLOGY
A Echo liu A
Page Name Title
Size Project Name Rev
B S42C
A
Date: Saturday, September 27, 2008 Sheet 1 of 51
PROPERTY NOTE: this document contains information confidential and property to
TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
to others or used for any purpose other than that for which it was obtained without
the expressed written consent of TOPSTAR
5 4 3 2 1
hexainf@hotmail.com
GRATIS - FOR FREE
5 4 3 2 1
Topstar Confidential
D
ShenZhen Topstar Industry Co.,LTD D
INDEX
01 Title
S42C SYSTEM BLOCK Ver:A 02 System Block & Index
03 PWR Block & Description
04 Notes and Annotations
05 Sch Modify and History
06 CLK_Gen_Buffer(CLK)
CPU Merom/ 07 Merom CPU(Host BUS)(1of 2)
Thermal Merom_Lite 08 Merom CPU(PWR&GND)(2 of 2)
Sensor 09 SiS672_HOST_PCIE(1/5)
F75393S CLK Generator: CLK buffer
478 uFCPGA RTM870T-670
10 SiS672_DDRII(2/5)
+V3.3S
Backlight PG 7 +VCC_CORE,+VCCP +V3.3S PG 6 +V1.8 PG 6 11 SiS672_MuTIOL_VGA(3/5)
Connector +VCCA1.5
+VDC 12 SiS672_PWR(4/5)
PG 7,8 13 SiS672_GND(5/5)
FSB 14 DDR2 SODIMM0
TFT 1066/800/667MHz 15 DDR2 SODIMM1
@8.5/6.4GB/s 16 DDR2 Termination_decoupling
+V3.3S LVDS
VGA BRD DDR2 SODIMM0 17 307LVDS
SIS672DX DDR2 533/667 533/667
+V0.9S,+V1.8,+V3.3S 18 LVDS&Inverter CONN
BGA 847 PG 15,17,18
C
Camera @5.3GB/s 19 CRT&S-VIDEO CONN & LIDR C
VGA BOARD
1.3M pixel R/G/B DDR2 SODIMM1 20 968-1 PCI/IDE/MuTIOL/SPI
DDR2 533/667 533/667 21 968-2 Host/LPC/PCIE/MAC/GPIO
+V5AL +V5S +V1.8S, +1.05S, +V0.9S,+V1.8,+V3.3S
+V1.2S,+V1.8AL,
+V1.8,+V1.2AL
PG 16,17,18 22 968-3 USB/SATA
PG 9,10,11,
23 968-4 Power
LAN Phy
12,13,14 8201CL 24 IDE/SATA CONN(SATA&DVD)
+V3.3AL/+V3.3S, 25 Card Reader(UB6232 USB)
PWFBOUT(1.8V/Internal) RJ45 26 NEW CARD
MutioL
16bit*133MHZ*4Mode PG 32 27 MII LAN PHY (RTL8201CL 100M)
S-ATAII
PCIE mini Card DVD
@1GB/s 28 MPCIE SLOT(WLAN)
+V5S
WLAN
PG 33 PG 28 29 USB PORTX&TP&LED&QB Con
MII 30 KBC(PC87541L)
SIS968
570 BGA S-ATAII 31 ALC662 Azalia codec
2.5" HDD
+V1.05S,+V3.3S 32 MDC&BT/FAN/OTP
+V5S,+V3.3S SD/MMC/MS CARD
+V1.8S,+V5S @300MB/s 33 ADAPTER IN
PCIE 1X PCIE 1X +V3.3AL,+V1.8AL PG 28 CardReader
+V2.5AL_LAN
USB2.0 RTS5158 34 BATTERY IN/OVP
ICH_EC_RTC
PCIE 1X USB1.1/2.0 +V3.3S,+V3.3AL
35 +V3.3AL +V5AL
PG 25,26,27
@480Mb/s PG 29,30 36 +V1.8/+V0.9S DDR
USB PORT1 37 +V1.2S
BLUE +V5AL LPC 38 V5S/V3.3S/V1.8S Power
TOOTH(V1.2) 2 PORT PG 34 AZALIA
MDCBTASC32 39 2.5AL/1.8AL/1.5S/1.05S LDO
B USB&LAN B
NEW CARD(Type II)
+V5AL +V3.3AL
+V3.3S PG 38 DAUGHTER
40 Power Good Logic/OVP
PG 31 41 DISCHARGE Circuit
BOARD
KB Controller/EC 42 +VCC_CORE
ENE KB3310B0 43 CHARGER
+V3.3S Speaker 44 THROUGH HOLE/EMI
SPI PG 35 Bass 45 Clock Distribution
46 Power Distribution
47 Power ON/OFF Timing
BIOS L
8Mbit 48 ACPI mode switch timings
+V3.3AL 49 PowerOnSequence & Reset Map
PG 35 R 50 ResetMap/NMI/SMI/THERMAL
MiC 51 CPU C STATE/GPIO
AZALIA
LED & TouchPAD QButton ALC883
+V5S,+V3.3S Audio Jack
DAUGHTER DAUGHTER PG 37
PG 37
BOARD BOARD
Azalia
M
D
C
C
A
R
D
+V3.3S
KB Matrix
PG 38 RJ11
A A
TOPSTAR TECHNOLOGY
Echo liu
Page Name System Block & Index
C S42C
A
Date: Sunday, September 28, 2008 Sheet 2 of 51
5 4 3 2 1
5 4 3 2 1
S42C POWER BLOCK Ver:A

D D
Charger Battery Platform

ISL6251
PU9 Logic
VR_ON
VR_TT#
Adapter VCC_CORE 44A VIN
Power +VDC ISL6262A Vcc_core
18.5-19.5V +VCC_CORE
Switch PU5 V_5 VID[6...0]
IMVP-6
PSI#
V_3
DPRSTP#
CLK_ENABLE#
IMVP6_PWRGD
DPRSLPVR
Vcc_sense
Vss_sense
Always_On
C
VGA/+V1.2S PWR DDR Power C
Power
TPS51124 TPS51116
TPS51120 PU2
PU3 PU1
DPRSTP# PSI# PROCHOT#
SIS968 CPU_PWRGD CPU-M

MOSFET MOSFET
+V1.2S +V3.3AL Switch +V1.8 Switch LDO
+V5S +V0.9S +V1.8S
+VGA_CORE +V5AL +V1.5S
+V3.3S
LDO LDO
LDO LDO CLK

+V1.05S +V_LAN CHIP
+V1.8AL +V1.2AL
(+V2.5AL)
B B
BATT+ +V5AL +V3.3AL +V1.8 +V1.5S +V1.05S +VCC_CORE +VGA_CORE
OVP Circuit
Page 43,52
A A
TOPSTAR TECHNOLOGY
Echo liu
Page Name PWR Block & description
Size
OVP OVP OVP OVP OVP OVP OVP OVP A3
Project Name
S42C
Rev
A
16.5V 5.6V 3.6V 2.0V 2.0V 2.0V 2.0V 2.0V Date: Sunday, September 28, 2008 Sheet 3 of 51
hexainf@hotmail.com 5 4 3 2 1
GRATIS - FOR FREE
5 4 3 2 1
Voltage Rails I2C SMB Address
+VDC Primary DC system power supply(9V-19V)
Device Address Hex Bus Master
+VCC_CORE Core voltage for processor Clock Generator 1101 111x D2 SMB_ICH_S SIS968
SO-DIMM0 1010 000x A0 SMB_ICH_S SIS968
+V1.5S 1.5V for CPU PLL
SO-DIMM1 1010 001x A2 SMB_ICH_S SIS968
D +V1.05S 1.05V for FSB VTT NEW CARD Variable Variable SMB_ICH_S SIS968 D
PCIE Mini CARD Variable Variable SMB_ICH_S SIS968
+V0.9S 0.9V DDR2 Termination voltage
+V1.8 1.8V power rail for DDR2 Embeded Controller(EC)
Smart Battery 0001 011x 16 I2C_591 Pin169/170
+V3.3AL 3.3V always on power rail CPU Thermal 1001 100x 98 I2C_591 Embeded Controller(EC)
Sensor(F75383S) Pin163/164
+V3.3S 3.3V main power rail
+V5AL 5V for USB Device
+V5S 5V main power rail
+V1.2S 1.2V PCIE IO,PLL,SIS671DX Core PCI Devices
Bus # Device # Function # Device ID IDSEL INTX Device Function
+V1.8S 1.8V SIS672/SIS968 Core/SATA/USB/PCIE
SIS968:
Bus 0 Device 2 Function 0 0008h AD13 N/A LPC
Bus 0 Device 2 Function 5 5513h/1180h/1181h AD13 INTA IDE
Bus 0 Device 3 Function 0 7001h AD14 INTE USB 1.1 #0
Board stack up description Bus 0 Device 3 Function 1 7001h AD14 INTF USB 1.1 #1
C Bus 0 Device 3 Function 3 7002h AD14 INTG USB 2.0 C
PCB Layers Bus 0 Device 4 Function 0 0191h AD15 INTD LAN
Bus 0 Device 5 Function 0 1183h/1184h/1185h AD16 INTB SATA
TOP
Bus 0 Device 6 Function 0 000Ah AD17 INTA/B/C/D PCI Express 0
VCC
Bus 0 Device 7 Function 0 000Ah AD18 INTA/B/C/D PCI Express 1
Bus 0 Device F Function 0 7502h AD26 INTC HD Audio
IN1 SIS672:
Bus 0 Device 0 Function 0 0671h AD11 North Bridge
Trace Impedence:55ohm +/-15%(Default) Bus 0 Device 31 Function 0 0004h AD31 Virtual PCI-to-PCI Bridge for
PCI-Express device
Onboard Devide:NON
IN2
GND Power States/AC mode

Bottom Signal SLP_S3# SLP_S4# SLP_S5# +V*AL +V* +V*S Clock
B S0(Full On) HIGH HIGH HIGH ON ON ON ON B

USB Table S3(STM) LOW HIGH HIGH ON ON OFF OFF
USB Port# Function Description S4(STD) LOW LOW HIGH ON OFF OFF OFF
0 USB Port(on Main Board) S5(SoftOff) LOW LOW LOW ON OFF OFF OFF
1 Mini PCIE Card(WLAN & ROBSON)
2 Express Card
Wake up Events
3 USB CAMERA(On VGA Board)
Wake up by LAN/968GMAC Internal
4 Bluetooth
LID switch from EC
5 UB6232 CARD Reader Power switch from EC
6 USB Port(on I/O Board)

A 7 USB Port(on I/O Board) ns: Component marked "ns" is not stuff TOPSTAR TECHNOLOGY A
Echo liu
Page Name
NOTE
A3 S42C
This is a lead free project,all component must be LF A
5 4 3 2 1
Schematic modify Item and history:

2007-08-31 Ver A initial release
2007-02-09 Ver B Change List
1.PG6 C218,C212,C331,C341 footprint from 1206 to 0805.Add C622,C623,C119,C120,C128 for EMI reserved.
2.PG6 Clock Enable : change R156 from 10K to 51K,ns C344,install C142
3.PG6 FSB : Add R673 and R674, ns R148,R151 ,R145,install R155 and R147.
D 4.PG11 : Change C573 and C574 net from DACAVDD2 to DACAVDD1 D
5.PG15 Add DIMM2 and surrounding Capacitor
6.PG21 : Add clear_cmos point.
7.PG22 : Change R421 value from 127 to 130 Ohm
8.PG26 Power Switch: Add Power Switch and surrounding circuit.
9.PG29 USB: Delete CHK3, and R331 and R329
10.PG30: PCB version from A to B
2007-03-09 Ver C Change List

1.PG19: Change VGA Connector
2.PG30: PCB version from B to C
2007-04-29 Ver D Change List

1. PG32 & PG21:Add modem and surrounding circuit
2. PG30: PCB version from C to D,Reserved R691
3. PG44:Change H3,H7 and H9 footprint from TH_315_112 to TH_315_118
4. PG33:Co-lay PD5 and PD8

C C
5. PG36:Co-lay PC164
2007-05-28 Ver E Change List

1.改了板边,升级PCB的料号从VerD到VerE.
2008-09-11 Ver F Change List

1.改了板边,升级PCB的料号从VerD到VerE.
2008-09-22 S42C Ver A Change List,主要换了realtek clock和新EC（KB3310B）

1. Delete CLKGEN_PWRGD circuit, NS R124,pull high PECLK2/3/5_REQ# and STOP_PCI_L#.
2. pull high CPU_STOP# because of no C3 and C4 function to realtek clock,change 56 ohm parallel resistor to 0 ohm paraller resistor.
3. R24,R26 footprint from 0603 to 0402
4. Delete paraller DVD net,and pull down or up according to SIS FAE suggest.
5. Reserved SPI BIOS ROM for SIS968, add R170
6. Delete LDRQ# off connector and R148,Delete reserved power on/S3/S4 control circuit.
7. Delete parallel DVD net add pull down or up according to SIS FAE suggest
8. Add reserved SPI ROM
9. Add SATA ODD,NS Q40 and R481,NS PQ58 and R489
10. 添加SATA DVD的Connector
B 11. Delete Co-layout card reader connector. B
12. Delete Co-layout Newcard powerswitch circuit
13.Change minipcie according to minipcie 1.2 spec
14. change EC form 87541 to KB3310B
15. Delete CD_IN circuit.

16.删掉BAT_TEM circuit
17.根据采购以及CE的意见，更改F75383 to F75393, U16 from ATMEL to SEIKO,U15 from RICHON to ENE,PU5 from KIA to APEC.
18.根据采购意见，更换CPU Vcore的Mosfet。
A A
TOPSTAR TECHNOLOGY
Echo liu
Page Name Sch Modify and history
Custom S42C
A
5 4 3 2 1
hexainf@hotmail.com
GRATIS - FOR FREE
5 4 3 2 1
+V1.05S 7,8,9,12,22,23,32,39,40,41,42
+V3.3S
+V3.3S 7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
1. ICS9LPR600_TSSOP-56P +V1.8 10,12,14,15,16,36,38,40,41,44
2. RTM870T-670 +V3.3AL 18,20,21,22,23,26,27,28,29,30,32,33,34,35,36,37,38,39,40,42,44
2
+VCC_CORE 8,40,42,44
FB37 3. SLG8LP701B
100ohm@100MHz,3A
1 FB0805 U2 When mount RTM870, use 0 Ohm
CLKGEN_VDD
CLKGEN_VDD CPU_BCLK RN8 2 0 RA0402_4
0.1uF/25V,Y5V
0.1uF/25V,Y5V
0.1uF/25V,Y5V
0.1uF/25V,Y5V
0.1uF/25V,Y5V
0.1uF/25V,Y5V
0.1uF/25V,Y5V
0.1uF/25V,Y5V
2 VDDREF CPUT_L0 55 1 CLK_CPU_BCLK 7
CPU_BCLK#
10uF/6.3V,X5R
14 VDDPCI_1 CPUC_L0 54 3 4 CLK_CPU_BCLK# 7

19 52 NB_BCLK RN7 1 2 0 RA0402_4
VDDPCI_2 CPUT_L1 CLK_NB_BCLK 9
23 51 NB_BCLK# 3 4
VDDZ CPUC_L1 CLK_NB_BCLK# 9
D 24 VDD48 D
56 44 PCIET_L0 RN5 1 2 0 RA0402_4 These Caps and serial resistors are for
VDDCPU PCIET_L0 NB_PCIE_CLK 9 impedance match and adjust clock's skew
C331 C332 C328 C334 C342 C333 C329 C343 C330 39 43 PCIEC_L0 3 4
VDDPCIEX_1 PCIEC_L0 NB_PCIE_CLK# 9
C0805 29 41 PCIET_L1 RN21 1 2 0 RA0402_4 Add C119,C120 and C128.LJ080223
VDDPCIEX_2 PCIET_L1 307_PCIE_CLK 17
40 PCIEC_L1 3 4
PCIEC_L1 307_PCIE_CLK# 17
7 38 PCIET_L2 RN3 1 2 0 RA0402_4 NB_ZCLK C120 10pF/50V,NPO
GNDREF PCIET_L2 CLK_PCIE_ICH 21
8 37 PCIEC_L2 3 4
GNDPCI_1 PCIEC_L2 CLK_PCIE_ICH# 21
13 36 SB_ZCLK C119 10pF/50V,NPO
GNDPCI_2 PCIET_L3
20 GNDZ PCIEC_L3 35
27 34 PCIET_L4 RN2 1 2 0 RA0402_4 CLK_ICHPCI C129 10pF/50V,NPO ns
GND48 PCIET_L4F CLK_PCIE_NEWCARD 26
53 33 PCIEC_L4 3 4
GNDCPU PCIEC_L4F CLK_PCIE_NEWCARD# 26
42 31 PCIET_L5F RN1 1 2 0 RA0402_4
GNDPCIEX_1 PCIET_L5F CLK_PCIE_MINICARD 28
32 30 PCIEC_L5F 3 4 MinipciE
GNDPCIEX_2 PCIEC_L5F CLK_PCIE_MINICARD# 28
CLK_591PCI C123 10pF/50V,NPO ns
49 SATACLKT_L RN6 1 2 0 RA0402_4
SATACLKT_L CLK_ICH_SATA 22
SIS_CLK_EN 1 48 SATACLKC_L 3 4 CLK_DEBUGPCI C128 10pF/50V,NPO
VTTPWRGD/PD#/(CLK_STOP#) SATACLKC_L CLK_ICH_SATA# 22
R107 0 ns 21 ZCLK0 R115 22 CLK14_REF1 C130 10pF/50V,NPO ns
21,30,40 SB_PWRGD ZCLK0 NB_ZCLK 11
22 ZCLK1 R114 22
ZCLK1 SB_ZCLK 20
R110 0 CPUSTOPIN#_SYSRSTOUT#28 R538 33 CLK14_REF2 C622 10pF/50V,NPO ns
22 CPUSTP# *(CPU_STOP#)/RESET# CLK14_REF2 11
+V3.3S Realtek:ns/ICS: install 3 _FSL0_CLK14 R518 33
*FSL0/REF0_2x CLK14_307 17
4 _FSL1_CLK14 R146 33 CLK14_307 C623 10pF/50V,NPO ns
**FSL1/REF1_2x CLK14_REF1 21
S42C/Delete CLKGEN_PWRGD circuit.LJ080912 FB38 120ohm@100MHz,500mA
2 1 CLK_VDDA 50 9 _FSL2_PCICLK0R144 33 add C622 and C623.lj080201
VDDA **FSL2/PCICLK0_2x CLK_ICHPCI 20 MODE=1(NB MODE)
_FSL3_PCICLK1R138 33
10uF/6.3V,X5R
**FS3/PCICLK1_2x 10 CLK_DEBUGPCI 28
FB0603 C335 C338 11 PCI_CLK2 R134 33 This works as PCIE CLK REQ#!
**FS4/PCICLK2 CLK_591PCI 30
C341
C0805 12 STOP_PCI_L# R468 0 ns
*(PCI_STOP#)/PCICLK3 STOP_PCI# 21 CLKGEN 's FSL[0:3] Vih/Vil:
15 CLKGEN_MODE
**MODE/PCICLK4 PECLK0/1/4_REQ# R127 0 +FSLS Vih_fs=0.7~~1.5V
47 GNDA (PECLKREQ0#)/PCICLK5 16 NEWCARD_CLKREQ# 26
C 0.1UF/25V,Y5V 0.01uF/16V,X7R 17 PECLK2/3/5_REQ# R124 0 ns Vil_fs=-0.3~~0.35V C
(PECLKREQ1#)/PCICLK6 PCIE_MINICARD_CLKREQ# 21,28
18 S42C/ns R124.LJ080912
PCICLK7 R155 2.7K _FSL0_CLK14
R130 0 45 26 SEL24_48M
14,15,21,26,28 SMB_DATA_S R133 0 SDATA **SEL24_48#/24_48MHz R154 ns 2.7K
14,15,21,26,28 SMB_CLK_S 46 SCLK
+V3.3S 25 USB_12M R111 33 3.3V-->2.72V
12MHz CLK_USB_12M 22
R159 0
R118 75 ns 1.8V-->1.7V
CLK_CR_12M 25
+V3.3AL
X1
X2
R119 R150 ns 2.7K _FSL1_CLK14
RTM870T-670 100
6
TSSOP56_0D5_6D1 ns +V3.3S +V1.05S R147 2.7K
R156 C143
51K 0.1UF/10V,X7R Layout note:
5
R369 R673 0 R142 ns 2.7K

10K 1 VCC Y2 14.31818M 3.0mm +FSLS
4 SIS_CLK_EN 1 2 XS2 ns R674 0 R141 2.7K _FSL2_PCICLK0
ns 2
3
GND SOT23_5 Reserved +V3.3S according to Demo board R132 2.7K _FSL3_PCICLK1
C133 C132
Q32 SN74AHC1G08DBV
3
2N7002 U3 33pF/50V,NPO 33pF/50V,NPO

R367 1K 1 SOT23
42 SIS_CLK_EN#
ns
C142 MP:Change footprint from 0603 to 0402.LJ0308
2
C344 change to 3.0mm Height Crystal Pin 11 only works as an pci output clk.
ns
0.1UF/25V,Y5V
0.1UF/25V,Y5V _FSL0_CLK14 R148 1K ns
CLK_CPU_BSEL0 7
_FSL1_CLK14 R151 1K ns
B CLK_CPU_BSEL1 7 B
_FSL2_PCICLK0R145 1K ns
CLK_CPU_BSEL2 7
+V1.8
Please base on your design to choose the appropriate capacitor vaule.
FSC FSB FSA HOST Clock
ns C344,change R156 value from 10K to 51K.080401LJ C210+C_X1+C_trace1=C1 BSEL2 BSEL1 BSEL0 frequency
2
FB26 C211+C_X2+C_trace2=C2
100ohm@100MHz,3A C_load(refer to the crystal datasheet)=(C1*C2)/(C1+C2)
FB0805 0 0 1 133
1
CLKBUF_VDD +V3.3S
1. ICS9P935_SSOP-28P CPUSTOPIN#_SYSRSTOUT#
R104 10K Realtek:install/ICS: ns
0 1 1 166
0.1UF/25V,Y5V
0.1UF/25V,Y5V
0.1UF/25V,Y5V
0.1UF/25V,Y5V
0.1UF/25V,Y5V
2. RTM683-910 CLKGEN_MODE R126 10K

C217
10uF/6.3V,X5R
3. SLG74201 0 1 0 200
C215
C222
C216
C223
C0805 PECLK2/3/5_REQ# R691 10K

C218
U17 STOP_PCI_L# R692 10K
CLKBUF_VDD 3 7 CLKBUF_AVDD
VDD1.8_1 VDDA1.8 S42C/add R691 and R692.LJ080912
11 VDD1.8_2
C218 footprint from 1206 to 0805.lj080201 25 1
VDD1.8_3 DDRC0 MEM_CHA_CLK#0 14
21 VDD1.8_4 DDRT0 2 MEM_CHA_CLK0 14
SEL24_48M R108 10K ns
+V1.8 10 5
10 DDR_FWD_CLK# CLK_INC DDRC1 MEM_CHA_CLK#2 15
120ohm@100MHz,500mA 9 4 USB_12M R125 10K ns
10 DDR_FWD_CLK CLK_INT DDRT1 MEM_CHA_CLK2 15
FB25
2 1 CLKBUF_AVDD R459 0 ns 20 13
14,15,21,26,28 SMB_DATA_S SDATA DDRC2 MEM_CHA_CLK#1 14
FB0603 R458 0 ns 19 12
14,15,21,26,28 SMB_CLK_S SCLK DDRT2 MEM_CHA_CLK1 14 CPUSTOPIN#_SYSRSTOUT#:
0.1UF/25V,Y5V
0.1UF/25V,Y5V
DDR_FBIO R457 0 DDR_FBIN Mobile mode default used as CPUSTOPIN#

10uF/6.3V,X5R
A 18 FB_IN DDRC3 15 MEM_CHA_CLK#3 15 A

R456 22 DDR_FBOUT 17 16 TOPSTAR TECHNOLOGY
FB_OUT DDRT3 MEM_CHA_CLK3 15 CLKGEN_MODE
C0805 C463 Echo liu
C214
C213
C212 8 23 =HIGH for Mobile mode

10pF/50V,NPO GND_1 DDRC4 =LOW for desktop mode Page Name
6 GND_2 DDRT4 22 CK-505M
28 GND_3
24 27 SEL24_48M 内部下拉120k Size Project Name Rev
GND_4 DDRC5 1=24MHz, 0 = 48MHz. A3
14 26 S42C A
C212 footprint from 1206 to 0805.lj080201 GND_5 DDRT5
USB_12M for Realtek Clock，内部下拉120k Date: Sunday, September 28, 2008 Sheet 6 of 51
RTM683-910
0 = P4 0.8V push-pull CPU clock PROPERTY NOTE: this document contains information confidential and property to
SOP28_0D65_5D3 1 = K8 3.3V push-pull CPU clock TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
5 4 3 2 1
5 4 3 2 1
+V3.3S 6,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
+V1.05S 6,8,9,12,22,23,32,39,40,41,42
CPU TO SB Interface +V1.05S

+V3.3AL 6,18,20,21,22,23,26,27,28,29,30,32,33,34,35,36,37,38,39,40,42,44
R364
H_FERR# 56 R0402
R359
PM_THRMTRIP#56 R0402
R368
H_STPCLK# 56 R0402
R362
H_A20M# 56 R0402
R372
H_IGNNE# 56 R0402
U13A ICTP ns R370
9 H_A#[3:35] T48
H_A#3 J4 H1 +V1.05S H_NMI 56 R0402
A[3]# ADS# H_ADS# 9
ADDR GROUP 0
H_A#4 L5 E2 R371
A[4]# BNR# H_BNR# 9 9 H_D#[63:0]
H_A#5 L4 G5 H_SMI# 56 R0402 U13B
D A[5]# BPRI# H_BPRI# 9 H_D#[63:0] 9 D
H_A#6 K5 R63 R363 H_D#0 E22 Y22 H_D#32
H_A#7 A[6]# 56 H_INTR 56 R0402 H_D#1 D[0]# D[32]# H_D#33
M3 A[7]# DEFER# H5 H_DEFER# 9 F24 D[1]# D[33]# AB24
H_A#8 N2 F21 R0402 H_D#2 E26 V24 H_D#34
A[8]# DRDY# H_DRDY# 9 D[2]# D[34]#
H_A#9 J1 E1 Place testpoint on H_D#3 G22 V26 H_D#35
A[9]# DBSY# H_DBSY# 9 D[3]# D[35]#
DATA GRP 0
H_A#10 N3 H_IERR# with a GND R366 H_D#4 F23 V23 H_D#36
H_A#11 A[10]# 0.1" away H_DPSLP# 56 R0402 H_D#5 D[4]# D[36]# H_D#37
P5 A[11]# BR0# F1 H_BREQ#0 9 G25 D[5]# D[37]# T22
H_A#12 P2 R373 H_D#6 E25 U25 H_D#38
A[12]# D[6]# D[38]#
CONTROL
H_A#13 L2 D20 H_IERR# H_INIT# 56 R0402 H_D#7 E23 U23 H_D#39
H_A#14 A[13]# IERR# R360 H_D#8 D[7]# D[39]# H_D#40
P4 B3 H_INIT# 21 K24 Y25
DATA GRP 2
H_A#15 A[14]# INIT# H_CPUSLP# 56 R0402 H_D#9 D[8]# D[40]# H_D#41
P1 A[15]# G24 D[9]# D[41]# W22
H_A#16 R1 H4 R374 H_D#10 J24 Y23 H_D#42
A[16]# LOCK# H_LOCK# 9 D[10]# D[42]#
M1 ICTP ns H_DPRSTP# 56 R0402 H_D#11 J23 W24 H_D#43
9 H_ADSTB#0 ADSTB[0]# T47 D[11]# D[43]# H_DSTBN#/H_DSTBP# should route
C1 R122 H_D#12 H22 W25 H_D#44
9 H_REQ#[4:0] RESET# H_CPURST# 9 D[12]# D[44]# as differential pair
H_REQ#0 K3 F3 H_RS#0 H_BREQ#0 56 R0402 H_D#13 F26 AA23 H_D#45
REQ[0]# RS[0]# H_RS#0 9 D[13]# D[45]#
H_REQ#1 H2 F4 H_RS#1 R123 H_D#14 K22 AA24 H_D#46
REQ[1]# RS[1]# H_RS#1 9 D[14]# D[46]#
H_REQ#2 K2 G3 H_RS#2 H_CPURST# 56 R0402 ns H_D#15 H23 AB25 H_D#47
REQ[2]# RS[2]# H_RS#2 9 D[15]# D[47]#
H_REQ#3 J3 G2 J26 Y26
REQ[3]# TRDY# H_TRDY# 9 9 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 9
H_REQ#4 L1 H26 AA26
REQ[4]# 9 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 9
9 H_A#[35:3]
H_A#17 HIT# G6 H_HIT# 9 Check if Need Level shift circuit? 9 H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 9
Y2 A[17]# HITM# E4 H_HITM# 9
H_A#18 U5 H_DPSLP# 9 H_D#[63:0] H_D#[63:0] 9
H_A#19 A[18]# H_BPM#0 ICTP ns H_D#16 H_D#48
R3 A[19]# BPM[0]# AD4 T41 H_DPRSTP# N22 D[16]# D[48]# AE24
ADDR GROUP 1
H_A#20 W6 AD3 H_BPM#1 ICTP ns H_D#17 K25 AD24 H_D#49
A[20]# BPM[1]# T45 H_CPUSLP# D[17]# D[49]#
H_A#21 U4 AD1 H_BPM#2 ICTP ns H_D#18 P26 AA21 H_D#50
A[21]# XDP/ITP SIGNALS BPM[2]# T116 D[18]# D[50]#
H_A#22 Y5 AC4 H_BPM#3 ICTP ns H_D#19 R23 AB22 H_D#51
A[22]# BPM[3]# T43 D[19]# D[51]#
H_A#23 U1 AC2 H_PRDY# T117 ICTP ns H_D#20 L23 AB21 H_D#52
A[23]# PRDY# D[20]# D[52]#
DATA GRP 1
H_A#24 R4 AC1 H_FREQ# T118 ICTP ns +V1.05S H_D#21 M24 AC26 H_D#53
H_A#25 A[24]# PREQ# H_TCK H_D#22 D[21]# D[53]# H_D#54
T5 A[25]# TCK AC5 L22 D[22]# D[54]# AD20
H_A#26 T3 AA6 H_TDI H_DBR# R61 150 R0402 ns H_D#23 M23 AE22 H_D#55
H_A#27 A[26]# TDI H_TDO H_TMS H_D#24 D[23]# D[55]# H_D#56
W2 A[27]# TDO AB3 T46 ICTP ns R139 39 R0402 P25 D[24]# D[56]# AF23
H_A#28 W5 AB5 H_TMS H_D#25 P23 AC25 H_D#57 Layout note:
H_A#29 A[28]# TMS H_TRST# H_TDI R140 150 R0402 H_D#26 D[25]# D[57]# H_D#58 Comp0,2 connec with Zo=27.4ohm,make
Y4 AB6 P22 AE21
DATA GRP 3
H_A#30 A[29]# TRST# H_DBR# H_D#27 D[26]# D[58]# H_D#59
U2 C20 T24 AD21 trace length shorter than 0.5"
H_A#31 A[30]# DBR# H_TCK R128 27.4,1%R0603 H_D#28 D[27]# D[59]# H_D#60
V4 A[31]# R24 D[28]# D[60]# AC22 Comp1,3 connec with Zo=55ohm,make
H_A#32 W3 H_TRST# R129 680 R0402 +V1.05S Add decoupling Caps H_D#29 L25 AD23 H_D#61 trace length shorter than 0.5"
H_A#33 A[32]# H_D#30 D[29]# D[61]# H_D#62
AA4 A[33]# THERMAL T25 D[30]# D[62]# AF22
H_A#34 AB2 ns H_D#31 N25 AC23 H_D#63
H_A#35 A[34]# VR_PROCHOT# H_TDO Pull VCCP by 54.9ohm D[31]# D[63]#
C AA3 A[35]# PROCHOT# D21 C289 9 H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 9 C
V1 A24 H_THERMDA Layout Note: Z=55ohm, M26 AF24
9 H_ADSTB#1 ADSTB[1]# THERMDA 0.01uF/25V,X7R 9
0.5" max for GTLREF H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 9
B25 H_THERMDC R325 N24 AC20
THERMDC 9 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 9
A6 1K,1%
21 H_A20M# A20M#
ICH
A5 C7 R0402 H_GTLREF AD26 R26 COMP_CPU0 R320 27.4,1% R0603 +V1.05S

21 H_FERR# FERR# THERMTRIP# PM_THRMTRIP# 21,32 GTLREF COMP[0]
C4 C23 MISC U26 COMP_CPU1 R321 54.9,1% R0603
21 H_IGNNE# IGNNE# TEST1 COMP[1]
ns T119 ICTP C482 COMP_CPU2 R136 27.4,1% R0603
D5 R326 C286 C287 ns ICTP T28 CPU_TEST3
D25
C24
TEST2 COMP[2] AA1
Y1 COMP_CPU3 R137 54.9,1% R0603 BOM:change to 0402
21 H_STPCLK# STPCLK# TEST3 COMP[3]
C6 H CLK C0402 2K,1% 0.1UF/10V,X7R CPU_TEST4 AF26 R117
21 H_INTR LINT0 R0402 TEST4
B4 A22 0.1UF/10V,X7R C0402 ns ICTP T113 CPU_TEST5 AF1 E5 200,1%
21 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 6 TEST5 DPRSTP# H_DPRSTP# 22,42
A3 A21 PM_THRMTRIP# should ns ICTP T97 CPU_TEST6 A26 B5 R0402
21 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 6 TEST6 DPSLP# H_DPSLP# R33022
connect to ICH8 and 0.01uF/25V,X7R D24 DPWR# 10 ns ns
DPWR# HDPWR# 9
ns ICTP T42 TP_CPU_RSVD01 M4 GMCH without B22 D6 R0402
RSVD[01] 6 CLK_CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD 9
ns ICTP TP1 TP_CPU_RSVD02 N5 T-ing(No stub) B23 D7
RSVD[02] 6 CLK_CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 21
ns ICTP TP2 TP_CPU_RSVD03 T2 R67 R319 C288 C21 AE6
RSVD[03] 6 CLK_CPU_BSEL2 BSEL[2] PSI# PM_PSI# 42 For SiSM672/M671
ns ICTP T44 TP_CPU_RSVD04 V3
ns ICTP T121 TP_CPU_RSVD05 RSVD[04] 1K 1K C0402 Merom Ball-out Rev 1a VerB:Del R328 for 671MX Remove R627, R642 10 ohm pull low.
B2 B1
RESERVED
ns ICTP T123 TP_CPU_RSVD06 RSVD[05] NC R0402 R0402 0.1UF/10V,X7R 071019 Due to PinE21 is NC
C3 RSVD[06]
ns ICTP T120 TP_CPU_RSVD07 D2 ns ns ns Place C461 close to DPWR# R648 10 For SiSM672MX/M671MX :
ns ICTP T33 TP_CPU_RSVD08 RSVD[07] the CPU_TEST4 pin. R627 mount 0ohm, Remove R642(10ohm).
D22 RSVD[08]
ns ICTP T122 TP_CPU_RSVD09 D3 Make sure CPU_TEST4
ns ICTP T40 TP_CPU_RSVD10 RSVD[09] routing is reference VerB:Del R69 for 671MX
F6 RSVD[10] to GND and away from 071024
other noisy signals. H_DPRSTP#/H_DPSLP# NEED LEVEL SHIFT!!
Merom Ball-out Rev 1a
FROM CPU TO SB
length:<0.5 inch
A#[32-39],APM3[0-1]:Leave escape BSEL[2] BSEL[1] BSEL[0] BCLK frequency
routing on for future width>7mil,Space>10mil H_CPUSLP# input from SB : force enter C2 sleep
functionality L L L 266 MHz
H_DPSLP# input from SB : indicate enter C3 sleep,stop CPU clock.
L H L 200 MHz
H_DPRSTP# input from SB : indicate enter C4 sleep,lower CPU voltage.
L H H 166 MHz
L H H RESERVED
B Note: B
VerC:CPU Socket改为Foxconn的 SIS671DX: 10 pull down,E21 is NC pin

071227
SIS671MX: used
CPU Thermal Sensor

BI-DIRECTIONAL
PROCESSOR HOT +V3.3S
S42C/ change F75383 to F75393.LJ080923
VDD_1 R311
220
C252 R0603
+V3.3S 0.1UF/25V,Y5V
C0402
H_THERMDA
1
+V1.05S R355 +V1.05S EC SMBUS ADD:1001 100X

VCC
10K C273 2 8
DXP SMBCLK I2C_CLK 30
R0402
2200PF/25V,X7R 3 7
C0402 DXN SMBDATA I2C_DATA 30
R350 R357
EC_PROCHOT# 30
+V1.05S H_THERMDC G781
1K
Q31
1K
ADM1032AR 6
OD
R0402 R0402 ALERT# OVT_SHUTDOWN# 32
3
Q30 SOT23 LM86CIM

1 MMBT2222A 1 MAX6657MSA 4 THERM#
GND
SOT23 R196 SOIC-8 THERM#

A A
MMBT2222A C253 C255
1K OD
2
R0402 U9 R324 R323

5
F75393S 10K 10K 27pF/50V,NPO 27pF/50V,NPO

SO8_50_150 R0402 R0402 C0402 C0402
VR_PROCHOT# 21,42
611375393002 ns ns TOPSTAR TECHNOLOGY
C321 CPU Vcore power Output to CPU to startup TCC circuit
NOTE Echo liu
C0402 OD output 1.H_THERMDA/C线宽10 MILS,并配对走线, Page Name Merom CPU(1of2)(Host BUS)
0.1UF/10V,X7R
CMOS Input Vilmax=0.3*VCCP 然后再包地处理.
ns BOM:NS for GPU OVT# Pull high Size Project Name Rev
2.H_THERMDA/C走线远离19V及VGA或高速线走线 C S42C
+V3.3S VerB:加上GPU的GPIO8 10K上拉 A
GPU端上拉ns Date: Saturday, September 27, 2008 Sheet 7 of 51
071012 PROPERTY NOTE: this document contains information confidential and property to
hexainf@hotmail.com the expressed written consent of TOPSTAR
GRATIS - FOR FREE 5 4 3 2 1

5 4 3 2 1
+V1.05S 6,7,9,12,22,23,32,39,40,41,42
U13D
+VCC_CORE 40,42,44
+V1.5S 11,26,28,32,39,40,41 A4 VSS[001] VSS[082] P6
A8 VSS[002] VSS[083] P21
A11 VSS[003] VSS[084] P24
A14 VSS[004] VSS[085] R2
+VCC_CORE +VCC_CORE +VCC_CORE Demo:22uF*32 3mOhm 0.6nH Caps Note: BOM cost down by Layout placement A16
A19
VSS[005] VSS[086] R5
R22
VSS[006] VSS[087]
A23 VSS[007] VSS[088] R25
AF2 VSS[008] VSS[089] T1
U13C C93 C311 C104 C91 C88 C81 C105 C98 C87 B6 T4
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R VSS[009] VSS[090]
A7 VCC[001] VCC[068] AB20 B8 VSS[010] VSS[091] T23
A9 AB7 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 B11 T26
VCC[002] VCC[069] VSS[011] VSS[092]
D A10 VCC[003] VCC[070] AC7 B13 VSS[012] VSS[093] U3 D
A12 VCC[004] VCC[071] AC9 B16 VSS[013] VSS[094] U6
A13 VCC[005] VCC[072] AC12 B19 VSS[014] VSS[095] U21
A15 VCC[006] VCC[073] AC13 ns ns ns B21 VSS[015] VSS[096] U24
A17 VCC[007] VCC[074] AC15 B24 VSS[016] VSS[097] V2
A18 AC17 +VCC_CORE C5 V5
VCC[008] VCC[075] VSS[017] VSS[098]
A20 VCC[009] VCC[076] AC18 C8 VSS[018] VSS[099] V22
B7 VCC[010] VCC[077] AD7 C11 VSS[019] VSS[100] V25
B9 AD9 C309 C293 C322 C296 C325 C301 C295 C14 W1
VCC[011] VCC[078] 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R VSS[020] VSS[101]
B10 VCC[012] VCC[079] AD10 C16 VSS[021] VSS[102] W4
B12 AD12 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C19 W23
VCC[013] VCC[080] VSS[022] VSS[103]
B14 VCC[014] VCC[081] AD14 C2 VSS[023] VSS[104] W26
B15 VCC[015] VCC[082] AD15 C22 VSS[024] VSS[105] Y3
B17 VCC[016] VCC[083] AD17 C25 VSS[025] VSS[106] Y6
B18 VCC[017] VCC[084] AD18 ns ns ns D1 VSS[026] VSS[107] Y21
B20 VCC[018] VCC[085] AE9 D4 VSS[027] VSS[108] Y24
C9 VCC[019] VCC[086] AE10 D8 VSS[028] VSS[109] AA2
C10 AE12 +VCC_CORE D11 AA5
VCC[020] VCC[087] VSS[029] VSS[110]
C15 AE17 C100 C327 C101 C83 C298 C86 C324 C303 D19 AA14
VCC[023] VCC[090] 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R VSS[032] VSS[113]
C18 AE20 C0805 C0805 C0805 C0805 C0805 C0805 C0805 C0805 D26 AA19
VCC[025] VCC[092] VSS[034] VSS[115]
D9 VCC[026] VCC[093] AF9 E3 VSS[035] VSS[116] AA22
D10 VCC[027] VCC[094] AF10 E6 VSS[036] VSS[117] AA25
D12 VCC[028] VCC[095] AF12 E8 VSS[037] VSS[118] AB1
D14 VCC[029] VCC[096] AF14 ns ns ns ns ns E11 VSS[038] VSS[119] AB4
D17 AF17 VerA:Remove C615, C616, C617, C618, C619, C620 E16 AB11
C VCC[031] VCC[098] +V1.05S VSS[040] VSS[121] C
E7 VCC[033] VCC[100] AF20 E21 VSS[042] VSS[123] AB16
E9 VerB:Del 22uF TANT CAP E24 AB19
VCC[034] 071024 VerB:ns 4个10uF电容for cost down VSS[043] VSS[124]
E10 VCC[035] VCCP[01] G21 F5 VSS[044] VSS[125] AB23
E12 V6 071025 F8 AB26
VCC[036] VCCP[02] Socket内6个，背面7个，Socket内去掉中间一排6个位置 VSS[045] VSS[126]
E13 VCC[037] VCCP[03] J6 C516 C281 C280 F11 VSS[046] VSS[127] AC3
E15 K6 +V1.05S 071026 F13 AC6
VCC[038] VCCP[04] ns 10uF/6.3V,X5R10uF/6.3V,X5R 10uF/6.3V,X5R VSS[047] VSS[128]
E17 VCC[039] VCCP[05] M6 F16 VSS[048] VSS[129] AC8
E18 J21 C0805 C0805 C0805 F19 AC11
VCC[040] VCCP[06] +V1.5S Generated from +V1.8S VSS[049] VSS[130]
E20 VCC[041] VCCP[07] K21 F2 VSS[050] VSS[131] AC14
F7 M21 +V1.5S C49 C51 C110 C50 C108 C109 F22 AC16
VCC[042] VCCP[08] VSS[051] VSS[132]
F9 VCC[043] VCCP[09] N21 F25 VSS[052] VSS[133] AC19
F10 N6 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R 0.1UF/10V,X7R G4 AC21
VCC[044] VCCP[10] +VCCA_CPU R318 0 C0402 C0402 C0402 C0402 C0402 C0402 VSS[053] VSS[134]
F12 VCC[045] VCCP[11] R21 G1 VSS[054] VSS[135] AC24
F14 R6 R0603 G23 AD2
VCC[046] VCCP[12] C285 C279 VSS[055] VSS[136]
F15 VCC[047] VCCP[13] T21 G26 VSS[056] VSS[137] AD5
F17 T6 0.01uF/16V,X7R 10uF/6.3V,X5R Place near PIN B26 within 100mils. VerB:CPU Socket改为TYCO的 H3 AD8
VCC[048] VCCP[14] C0402 C0805 071019 VSS[057] VSS[138]
F18 VCC[049] VCCP[15] V21 H6 VSS[058] VSS[139] AD11
F20 VCC[050] VCCP[16] W21 H21 VSS[059] VSS[140] AD13
AA7 BRACKET BRACKET1_Mylar H24 AD16
VCC[051] VSS[060] VSS[141]
AA9 VCC[052] VCCA[01] B26 J2 VSS[061] VSS[142] AD19
AA10 VCC[053] VCCA[02] C26 J5 VSS[062] VSS[143] AD22
AA12 VCC[054] J22 VSS[063] VSS[144] AD25
AA13 VCC[055] VID[0] AD6 H_VID0 42 J25 VSS[064] VSS[145] AE1
AA15 AF5 +VCC_CORE K1 AE4
VCC[056] VID[1] H_VID1 42 VSS[065] VSS[146]
AA17 VCC[057] VID[2] AE5 H_VID2 42 K4 VSS[066] VSS[147] AE8
AA18 VCC[058] VID[3] AF4 H_VID3 42 K23 VSS[067] VSS[148] AE11
AA20 VCC[059] VID[4] AE3 H_VID4 42 K26 VSS[068] VSS[149] AE14
AB9 AF3 R358 L3 AE16
B VCC[060] VID[5] H_VID5 42 VSS[069] VSS[150] B
AC10 AE2 100,1% L6 AE19
VCC[061] VID[6] H_VID6 42 VSS[070] VSS[151]
AB10 R0402 L21 AE23
VCC[062] VSS[071] VSS[152]
AB12 VCC[063] L24 VSS[072] VSS[153] AE26
AB14 VCC[064] VCCSENSE AF7 VCCSENSE 42 M2 VSS[073] VSS[154] A2
AB15 VCC[065] M5 VSS[074] VSS[155] AF6
AB17 VCC[066] M22 VSS[075] VSS[156] AF8
AB18 VCC[067] VSSSENSE AE7 VSSSENSE 42 M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
Merom Ball-out Rev 1a N4 AF16
Layout Note: VCCSENSE and VSSSENSE VSS[078] VSS[159]
N23 VSS[079] VSS[160] AF19
lines should be of equal length R361 N26 AF21
100,1% VSS[080] VSS[161]
P3 VSS[081] VSS[162] A25
Route VCCSENSE and VSSSENSE traces R0402 AF25
at 27.4 Ohms with 50 mil spacing VSS[163]
Merom Ball-out Rev 1a
Place PU and PD within 1 CPU_BRACKET Mylar
inch of CPU. Assy Assy
HCPU1 HCPU2 HCPU3 HCPU4

VerC:CPU Socket改为Foxconn的
071227
CPU_HOLE CPU_HOLE CPU_HOLE CPU_HOLE

ns ns ns ns
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
A A
TOPSTAR TECHNOLOGY
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Echo liu
Page Name Merom CPU(2of2)(Host BUS)
VerC：螺丝孔footprint改为M42共用的 Size Project Name Rev
071227 A3 S42C
A
5 4 3 2 1
5 4 3 2 1
U12C H_D#[0:63] 7 +V1.2S 12,37,39,40,41,44

+V1.05S 6,7,8,12,22,23,32,39,40,41,42
+V1.8S C1XAVDD B16 N29 H_D#0
C1XAVDD HD0# +V1.8S 10,11,12,17,20,21,22,23,38,39,44
25mA@+1.8V for estimated C1XAVSS C17 M30 H_D#1
FB36 C1XAVSS
Hostbus PLL HD1#
HD2# M28 H_D#2
1 2 C4XAVDD C4XAVDD A17 L30 H_D#3
C4XAVSS C4XAVDD HD3# H_D#4
B18 C4XAVSS HD4# L29
C89 120ohm@100MHz,500mA K28 H_D#5
C276 NB_GTLREF HD5# H_D#6
C284 W24 HVREF_01 HD6# K31
10uF/6.3V
FB0603 0.1UF/10V,X7R U24 K30 H_D#7
ns C0402 HVREF_02 HD7# H_D#8
R24 HVREF_03 HD8# H31 77mA@+1.2V for estimated
C4XAVSS N24 G34 H_D#9
0.01uF/25V,X7R HVREF_04 HD9# H_D#10
L21 HVREF_05 HD10# H32
D G32 H_D#11 D
T100 HD11# FB13
ICTP K32 H_D#12 120ohm@100MHz,500mA
T36 HD12#
+V1.8S ns R34 F34 H_D#13 +V1.2S 1 2 PCIEAVDD
VerB：DVT没有671MX配置，NC ns PCREQ# HD13# H_D#14 FB0603
FB35 25mA@+1.8V for estimated P32 EDRDY# HD14# F33
071024 F32 H_D#15 C71 C84
HD15# C76
1 2 C1XAVDD ICTP E21 H28 H_D#16 ns
7 HDPWR# DPWR# HD16#
J30 H_D#17 C0603 0.1UF/10V,X7R 0.01uF/25V,X7R
HD17# H_D#18 1uF/10V,X7R C0402
120ohm@100MHz,500mA HD18# H30
C124 C283 C275 F18 G29 H_D#19
6 CLK_NB_BCLK CPUCLK HD19# U12D
FB0603 0.1UF/10V,X7R G18 J29 H_D#20
10uF/6.3V 6 CLK_NB_BCLK# CPUCLK# HD20#
C0402 G30 H_D#21 PCIEAVDD P7
C1XAVSS HD21# H_D#22 PCIEAVDD_01
7 H_LOCK# L32 HLOCK# HD22# F30 R7 PCIEAVDD_02 REFCLK+ T5 NB_PCIE_CLK 6
0.01uF/25V,X7R P30 D33 H_D#23 PCIE anolog Power T7 T4
7 H_DEFER# DEFER# HD23# PCIEAVDD_03 REFCLK- NB_PCIE_CLK# 6
ns P31 D34 H_D#24 U7
7 H_TRDY# HTRDY# HD24# PCIEAVDD_04
F21 B32 H_D#25 V7
7 H_CPURST# CPURST# HD25# PCIEAVDD_05
P28 B33 H_D#26
7 H_PWRGD CPUPWRGD HD26#
N30 C34 H_D#27 R74 0 R0402 D7
7 H_BPRI# BPRI# HD27# 26,28,30 PCIE_WAKE# PME#
P33 D31 H_D#28 R77 0 R0402G16
7 H_BREQ#0 BREQ0# HD28# 11,17,20 PCI_INTA# INTX#
A32 H_D#29
H_RS#0 HD29# H_D#30
7 H_RS#0 K34 RS0# HD30# A31 E4 PERP0 PETP0 G6
H_RS#1 M31 C31 H_D#31 E5 H6
7 H_RS#1 RS1# HD31# PERN0 PETN0
H_RS#2 K33 B30 H_D#32 F1 G4
7 H_RS#2 RS2# HD32# PERP1 PETP1
C30 H_D#33 G1 G5
+V1.05S HD33# H_D#34 PERN1 PETN1
7 H_ADS# M34 ADS# HD34# A30 H3 PERP2 PETP2 J6
N34 D28 H_D#35 H2 K6
7 H_HITM# HITM# HD35# PERN2 PETN2
N32 G28 H_D#36 H1 J4
7 H_HIT# HIT# HD36# PERP3 PETP3
M33 C29 H_D#37 J1 J5
7 H_DRDY# DRDY# HD37# PERN3 PETN3
L34 C28 H_D#38 K1 L6
7 H_DBSY# DBSY# HD38# PERP4 PCIE PETP4
M32 E28 H_D#39 K2 M6
7 H_BNR# BNR# HD39# PERN4 PETN4
C R96 C73 E27 H_D#40 L1 M4 C
7 H_REQ#[0:4] HD40# PERP5 PETP5
75,1% H_REQ#0 T34 C27 H_D#41 M1 M5
0.01uF/25V,X7R H_REQ#1 HREQ0# Host HD41# H_D#42 PERN5 PETN5
R0402 R30 HREQ1# HD42# G26 N1 PERP6 PETP6 P6
H_REQ#2 R29 E26 H_D#43 N2 R6
NB_GTLREF H_REQ#3 HREQ2# HD43# H_D#44 PERN6 PETN6
R32 HREQ3# HD44# D26 P1 PERP7 PETP7 P4 To 307ELV
H_REQ#4 P34 B26 H_D#45 R1 P5
HREQ4# HD45# H_D#46 PERN7 PETN7
HD46# A26 T1 PERP8 PETP8 V6
C26 H_D#47 T2 W6
R100 C85 HD47# H_D#48 PERN8 PETN8
C77 7 H_ADSTB#0 U34 HASTB0# HD48# G22 U1 PERP9 PETP9(HDVBP2) W4 HDVBP2 17
150,1% 0.1UF/10V,X7R AA34 C24 H_D#49 V1 W5
7 H_ADSTB#1 HASTB1# HD49# PERN9 PETN9(HDVBN2) HDVBN2 17
R0402 C0402 A25 H_D#50 W1 Y6
7 H_A#[3:35] HD50# PERP10 PETP10(HDVBP1) HDVBP1 17
H_A#3 T32 B24 H_D#51 W2 AA6
HA3# HD51# PERN10 PETN10(HDVBN1) HDVBN1 17
0.01uF/25V,X7R H_A#4 T28 C25 H_D#52 Y1 AA4
HA4# HD52# PERP11 PETP11(HDVBP0) HDVBP0 17
H_A#5 T31 A24 H_D#53 AA1 AA5
HA5# HD53# PERN11 PETN11(HDVBN0) HDVBN0 17
H_A#6 T33 E23 H_D#54 AB1 AB6
H_A#7 HA6# HD54# H_D#55 PERP12 PETP12
T30 HA7# HD55# E25 AB2 PERN12 PETN12 AC6
H_A#8 U32 G24 H_D#56 AC1 AC4
HA8# HD56# PERP13 PETP13(HDVAP2) HDVAP2 17
H_A#9 U30 D22 H_D#57 AD1 AC5
HA9# HD57# PERN13 PETN13(HDVAN2) HDVAN2 17
H_A#10 V34 C22 H_D#58 AE1 AD6
H_A#11 U29 E22 H_D#59 AE2 AE6
H_A#12 V33 C23 H_D#60 AF1 AE4
H_A#13 V32 A23 H_D#61 AG1 AE5
H_A#14 V28 A22 H_D#62
H_A#15 HA14# HD62# H_D#63
V31 HA15# HD63# B22 M672 A1
H_A#16 W34
H_A#17 HA16# BGA847
Y33 HA17#
H_A#18 W32 J32
HA18# DBI0# H_DINV#0 7
H_A#19 V30 E32
H_A#20 W30 F27
B HA20# DBI2# H_DINV#2 7 B
H_A#21 Y34 F23
H_A#22 Y28
H_A#23 HA22#
W29 HA23# HDSTBN0# H33 H_DSTBN#0 7
Layout Note:For FSB533/400 issue(Copy data,Hang up) H_A#24 Y32 E31
The clock skew between ZCLK and CPUCLK must be more than 1ns. HA24# HDSTBN1# H_DSTBN#1 7
H_A#25 Y30 B28
Trace length of CPUCLK + X(inches) < or = Trace length of ZCLK HA25# HDSTBN2# H_DSTBN#2 7
H_A#26 Y31 D24
0<X<10inch HA26# HDSTBN3# H_DSTBN#3 7
H_A#27 AA32
H_A#28 HA27#
AA30 HA28# HDSTBP0# H34 H_DSTBP#0 7
H_A#29 AA29 D32
HA29# HDSTBP1# H_DSTBP#1 7
H_A#30 AB33 A28
H_A#31 AB34 E24
H_A#32 AB32
H_A#33 HA32#
AC34 HA33# HPCOMP A21 H_SCOMP
R317 110,1%R0402
H_A#34 AB30 C21 H_SCOMP#
R62 12.1,1%R0402 +V1.05S
H_A#35 HA34# HNCOMP
AB31 HA35#
M672 A1
BGA847
A A
TOPSTAR TECHNOLOGY
Echo liu
Page Name Crestline(HOST)
A3 S42C A
GRATIS - FOR FREE
5 4 3 2 1
+V1.8 6,12,14,15,16,36,38,40,41,44
U12B SiS671DX Only Support Signle channel!!!
+V1.8S 9,11,12,17,20,21,22,23,38,39,44
MA_DATA0 AD31 +V1.8S 20mA@+1.8V for estimated
MA_DATA1 MD0A
AD30 MD1A
MA_DATA2 AG34 A15 D1XAVDD FB34 120ohm@100MHz,500mA
MA_DATA[63:0] 14,15 MD2A D1XAVDD
MA_DATA3 AE29 B15 D1XAVSS 1 2 D1XAVDD
MA_DATA4 MD3A D1XAVSS FB0603
MA_DM[0:7] 14,15 AE32 MD4A Memory PLL
MA_DATA5 AF34 AP11 D4XAVDD
MA_DATA6 MD5A D4XAVDD
MA_DQS[0:7] 14,15 AF31 MD6A D4XAVSS AP10 D4XAVSS C112 C282 C274
MA_DATA7 AE30 0.1UF/10V,X7R
MA_DM0 MD7A 10uF/6.3V 0.01uF/25V,X7R C0402
MA_DQS#[0:7] 14,15 AD28 DQM0A
MA_DQS0 AF32 ns D1XAVSS
MA_DQS#0 DQS0A
D AF33 DQS0A# layout note: D
MA_A_A[10:0] 14,15,16
MA_DATA8 AF28 MD8A MA0A AH24 MA_A_A0 Place close to 671DX,
MA_DATA9 AJ34 AP25 MA_A_A1
MA_DATA10 AH31
MD9A MA1A
AM25 MA_A_A2 D1XAVSS TRACE RETURN TO C'S GND
MA_DATA11 MD10A MA2A MA_A_A3
AG30 MD11A MA3A AL25
MA_DATA12 AF30 AP26 MA_A_A4
MA_DATA13 MD12A MA4A MA_A_A5
AG32 MD13A MA5A AM26
MA_DATA14 AJ32 AN26 MA_A_A6 20mA@+1.8V for estimated
MA_DATA15 MD14A MA6A MA_A_A7 +V1.8S
AJ31 MD15A MA7A AK25
MA_DM1 AH34 AP27 MA_A_A8
MA_DQS1 DQM1A MA8A MA_A_A9 FB40 120ohm@100MHz,500mA
AH32 DQS1A MA9A AP28
MA_DQS#1 AH33 AK24 MA_A_A10 1 2 D4XAVDD
DQS1A# MA10A FB0603
MA11A AN24 MA_A_BS#0 14,15,16
MA_DATA16 AK34 AP24
MD16A MA12A MA_A_BS#1 14,15,16
MA_DATA17 AH30 AM28 C111 C336 C3390.1UF/10V,X7R
MD17A DRAM MA13A MA_A_BS#2 14,15,16
MA_DATA18 AL32 AM27 MA_A_A11
MD18A MA14A MA_A_A11 14,15,16 10uF/6.3V
MA_DATA19 AM33 AN28 MA_A_A12 0.01uF/25V,X7R
MD19A MA15A MA_A_A12 14,15,16
MA_DATA20 AK32 AP21 MA_A_A13 ns D4XAVSS C0402
MD20A MA16A MA_A_A13 14,15,16
MA_DATA21 AG29 AP29 MA_A_A14
MD21A MA17A MA_A_A14 14,15,16
MA_DATA22 AM34
MA_DATA23 MD22A
AL31 MD23A RASA# AM23 MA_A_RAS# 14,15,16
MA_DM2 AJ30 AP22
DQM2A CASA# MA_A_CAS# 14,15,16
MA_DQS2 AK33 AJ23
DQS2A WEA# MA_A_WE# 14,15,16
MA_DQS#2 AL34 DQS2A#
MA_DATA24 AM32 AK12 +V1.8
MD24A FWDSDCLKOA DDR_FWD_CLK 6
MA_DATA25 AP32 AH12
MD25A FWDSDCLKOA# DDR_FWD_CLK# 6
MA_DATA26 AP31
C MA_DATA27 MD26A C
AM29 MD27A
MA_DATA28 AK30
MA_DATA29 MD28A
AK29 MD29A CS0A# AP23 M_CS#0 14,16
MA_DATA30 AJ27 AH22
MD30A CS1A# M_CS#1 14,16
MA_DATA31 AK28 AM22
MD31A CS2A# M_CS#2 15,16
MA_DM3 AN32 AM21
DQM3A CS3A# M_CS#3 15,16
MA_DQS3 AM30 R135 C127
MA_DQS#3 DQS3A 1K,1% 0.1UF/10V,X7R
AM31 DQS3A#
AK22 R0402 C0402
ODT0A M_ODT0 14,16
MA_DATA32 AK20 AP20 ns
MD32A ODT1A M_ODT1 14,16
MA_DATA33 AM20 AN22 0 R208 M_DDRVREF
MD33A ODT2A M_ODT2 15,16 14,36 SM_VREF
MA_DATA34 AM19 AL21 R0603
MD34A ODT3A M_ODT3 15,16
MA_DATA35 AJ19
MA_DATA36 MD35A
AN20 MD36A C116 C118
MA_DATA37 AJ21 AN30 R116
MD37A CKEA0 M_CKE0 14,16 0.1uF/10V,X7R 1uF/10V,X7R
MA_DATA38 AP19 AP30 1K,1%
MD38A CKEA1 M_CKE1 14,16 R0402
MA_DATA39 AH20 AH26 C0402 C0603
MD39A CKEA2 M_CKE2 15,16
MA_DM4 AK21 AK27 ns
DQM4A CKEA3 M_CKE3 15,16
MA_DQS4 AK19
MA_DQS#4 DQS4A Place Under 671DX solder side.
AL19 DQS4A#
MA_DATA40 AK18
MA_DATA41 MD40A
AJ17 MD41A
MA_DATA42 AK17
MA_DATA43 MD42A M_DDRVREF
AP16 MD43A DDRVREF0 AD18
MA_DATA44 AH18 AD23
MA_DATA45 MD44A DDRVREF1
AP18 MD45A
MA_DATA46 AN18
MA_DATA47 MD46A
AP17 MD47A
B MA_DM5 R0402 B
AM18 DQM5A
MA_DQS5 AL17 AJ25 M_DDRCOMP R106 35.7,1%
MA_DQS#5 DQS5A DDRCOMP M_DDRCOMN R113 35.7,1%
AM17 DQS5A# DDRCOMN AK26 +V1.8
R0402
MA_DATA48 AN16
MA_DATA49 MD48A +V1.8 +V1.8
AK16 MD49A
MA_DATA50 AN14 AH28 M_OCDVREF_P
MA_DATA51 MD50A OCDVREFP
AJ15 MD51A OCDVREFN AJ29 M_OCDVREF_N
MA_DATA52 AP15
MA_DATA53 MD52A R103 R112
AM16 MD53A
MA_DATA54 AK15 40.2,1% 35.7,1%
MA_DATA55 MD54A +0.853V +0.947V
AP14 MD55A S42C/Delete S3AUXSW#. LJ080916 R0402 R0402
MA_DM6 AH16 DQM6A T125
MA_DQS6 AL15 ICTP M_OCDVREF_P M_OCDVREF_N
MA_DQS#6 DQS6A ns
AM15 DQS6A# S3AUXSW# B6
R102 R105
MA_DATA56 AL13 35.7,1% 40.2,1%
MA_DATA57 MD56A
AM13 MD57A R0402 R0402
MA_DATA58 AM12
MA_DATA59 MD58A
AJ13 MD59A
MA_DATA60 AM14
MA_DATA61 MD60A
AK14 MD61A
MA_DATA62 AN12
MA_DATA63 MD62A
MA_DM7
AH14 MD63A Demo: 36ohm,1% 0402 for 35.7ohm,
AK13 DQM7A
MA_DQS7 AP12
MA_DQS#7 DQS7A
AP13 DQS7A#
A A
TOPSTAR TECHNOLOGY
Echo liu
M672 A1 Page Name Crestline(DDRII)
BGA847
A3 S42C A
5 4 3 2 1
5 4 3 2 1
+V1.8 6,10,12,14,15,16,36,38,40,41,44
+V1.8S 9,10,12,17,20,21,22,23,38,39,44
+V3.3S 6,7,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
+V1.5S 8,26,28,32,39,40,41
U12A R70
AH10 F15 NB_ENTEST 4.7K R0402
6 NB_ZCLK ZCLK ENTEST
D AP8 D16 TM0 T24 ICTP ns D
20 ZDREQ ZDREQ TESTMODE0
AN8 E16 TM1 T27 ICTP ns
20 ZUREQ ZUREQ TESTMODE1
F16 TM2 T30 ICTP ns
TESTMODE2 TRAP0 ICTP ns
20 ZSTB_DP0 AM7 ZSTB0 TRAP0 D17 T25
AL7 E17 TRAP1 T26 ICTP ns
20 ZSTB_DN0 ZSTB0# TRAP1
AP4 F17 TRAP2 T29 ICTP ns
20 ZSTB_DP1 ZSTB1 TRAP2
20 ZSTB_DN1 AP5 ZSTB1# Leave as test point!
ZAD0 AK10 AC32 TRAP3 T109 ICTP ns
ZAD1 ZAD0 TRAP3 TRAP4 ICTP ns
AM6 ZAD1 TRAP4 AD34 T111
ZAD2 AK11 AB28 TRAP5 T37 ICTP ns
20 ZAD[0:16] ZAD2 TRAP5
ZAD3 AJ11 AD32 TRAP6 T103 ICTP ns
AP7 ZAD4 TRAP7 AD33 T110
ZAD5 AJ9 AE34 TRAP8 T112 ICTP ns
AP6 ZAD6 TRAP9 AC30 T38
ZAD7 AN6 AC29 TRAP10 T39 ICTP ns
ZAD8 ZAD7 TRAP10
AK9 ZAD8
20mA@+1.8V for 671DX estimated ZAD9 AM4
+V1.8S ZAD10 ZAD9 R313 4.7K
AK6 ZAD10
ZAD11 AK8 AGP_BUSY# +V3.3S
FB39 ZAD11
ZAD12 AN4 A5 R0402
ZAD12 AUXOK ALW_PWROK 21,30,40
1 2 Z4XAVDD ZAD13 AK7 C6
ZAD13 PWROK NB_PWRGD 30,40
ZAD14 AL5 A7
ZAD14 PCIRST# NB_RST# 17,20
ZAD15 AM5
120ohm@100MHz,500mA C340 ZAD16 ZAD15 ASL C272
C107 C337 AM8 ZAD16
FB0603 0.1UF/10V,X7R ALW_PWROK 0.1uF/10V,X7R
10uF/6.3V C0402 Demo SCH: 56ohm,1% NZVREF AL9 C0402
Z4XAVSS 56.2,1% R365 R0402 NZCOMP ZVREF
AP9 ZCMP_P
0.01uF/25V,X7R +V1.8S 56.2,1% R120 R0402 NZCOMP# AM9 C56
ZCMP_N NB_PWRGD 0.1uF/10V,X7R
C AGPSTOP# G14 AGP_STOP# 21 C
MuitIOL Power A6 C0402
AGPBUSY# AGP_BUSY# 21
Z4XAVDD AM10 D8
Z4XAVDD VBVSYNC VBVSYNC 17
Z4XAVSS
D13/C12/C13/D15/C15/C14 are left as NC for 671DX! AN10 Z4XAVSS VBHSYNC F7 VBHSYNC 17
E12/D11/F12/G12/F11/ are used as Vss for 671DX! VBHCLK E7 VBHCLK 17
19 CRT_RED D13 ROUT VBCLK C8 VBCLK 17

19 CRT_GREEN C12 GOUT VBCAD E9 VBCAD 17
+V1.8S C13
19 CRT_BLUE BOUT
VACLK D9 VACLK 17
R520 0 F12
19 CRT_HSYNC HSYNC
R519 0 G12
19 CRT_VSYNC VSYNC
这四个信号都是OD信号，在Connector已经上拉到＋V3.3S
R131 R521 0 D11
Vzvref=0.45V 19 CRT_DDC_CLK VGPIO0
C122 150,1% R522 0 E12 AH2
19 CRT_DDC_DATA VGPIO1 NC0
0.1UF/10V,X7R
R0402 AG3
C0402 DACAVDD1 C574 0.1uF/10V,X7R VCOMP NC1
D15 VCOMP
C573 0.1uF/10V,X7R WBWN C15
NZVREF R539 130,1% WREST VVBWN
C14 VRSET
R79 0 F13
9,17,20 PCI_INTA# INTA#
C121 R121
0.1UF/10V,X7R R540 0 CLK14_REF2_R F11
6 CLK14_REF2 VOSCI
C0402 49.9,1%
R0402 DACAVDD1 A12
CRT_RED R669 150,1% DACAVDD1
B12 DACAVSS1
VGA DAC Power
B CRT_GREEN R670 150,1% DACAVDD2 A13 B
DACAVDD2
B13 DACAVSS2
CRT_BLUE R671 150,1%
DCLKAVDD B10 DCLKAVDD
A11 DCLKAVSS VGA DOCK Power
ECLKAVDD A9 ECLKAVDD
B8 ECLKAVSS VGA engine Power
M672 A1
BGA847
+V1.8S +V1.8S
FB55 120ohm/100MHz,500mA DACAVDD2 FB56 120ohm/100MHz,500mA DCLKAVDD

FB0603 FB0603
C575 C576 C577 C579 C580

C0805 C578
10uF/6.3V,X5R 0.1uF/10V,X7R 1uF/10V,X7R C0805 0.1uF/10V,X7R 0.01uF/25V,X7R
C0603 10uF/6.3V,X5R
+V1.5S
A +V1.8S A
FB60 120ohm/100MHz,500mA TOPSTAR TECHNOLOGY
FB0603
S42C/Delete 1.8v supply.LJ0912 DACAVDD1 FB58 120ohm/100MHz,500mA ECLKAVDD Echo liu
FB0603 Page Name Crestline(DMI&CLK)
C581 C582 C583 C584 C585 C586 Size Project Name Rev
C0805 C0805 Custom S42C
10uF/6.3V,X5R 0.1uF/10V,X7R 1uF/10V,X7R 10uF/6.3V,X5R 0.1uF/10V,X7R 0.01uF/25V,X7R A
C0603 Date: Saturday, September 27, 2008 Sheet 11 of 51
5 4 3 2 1
+V1.2S timing behind +V3.3S

+V1.8 6,10,14,15,16,36,38,40,41,44
+V1.8 U12E
+V1.2S
+V1.8S 9,10,11,17,20,21,22,23,38,39,44
+V1.8AL 21,22,23,39,40
Memory controller Power +V1.2AL 39,40
+V1.8 NB Core Power +V1.2S 9,37,39,40,41,44
667mA@FSB1066+DDR2667 W23 VCCM_01 +V1.05S 6,7,8,9,22,23,32,39,40,41,42
Y23 M13 +V1.2S IVDD:834mA for 671DX estimated
VCCM_02 IVDD_01
Place AA23 VCCM_03 IVDD_02 M14
AB23 VCCM_04 IVDD_03 M15
C94 AC23 M16 Place
C117 C106 C102 C115 C96 C114 C471 C472 VCCM_05 IVDD_04
AC18 VCCM_06 IVDD_05 M17
0.1UF/10V,X7R C0805 C0805 AC20 M18
10UF/6.3V,X5R C0603 C0603 C0603 C0402 C0402 C0603 4.7uF/6.3V,X5R
4.7uF/6.3V,X5R VCCM_07 IVDD_06 C113 C69 C65 C64 C75 C72 C63 C473 C474
D AC16 VCCM_08 IVDD_07 M19 D
C0805 1uF/10V,X7R1uF/10V,X7R1uF/10V,X7R0.1UF/10V,X7R 1uF/10V,X7R AD16 N16 C0805 C0805
VCCM_09 IVDD_08 10UF/6.3V,X5R C0603 C0603 C0603 C0402 0.1UF/10V,X7R C0603 4.7uF/6.3V,X5R
4.7uF/6.3V,X5R
AD17 VCCM_10 IVDD_09 N17
AD19 N18 C0805 1uF/10V,X7R1uF/10V,X7R1uF/10V,X7R0.1UF/10V,X7R C0402 1uF/10V,X7R
VCCM_11 IVDD_10
AD20 VCCM_12 IVDD_11 N20
Place these capacitors AD21 VCCM_13 IVDD_12 R22
under 671DX solder side AD22 VCCM_14 IVDD_13 N22
AJ22 VCCM_15 IVDD_14 N13 Place these capacitors
AJ24 VCCM_16 IVDD_15 P13 under 671DX solder side
AL23 VCCM_17 IVDD_16 Y13
AL26 VCCM_18 IVDD_17 Y22
AN21 VCCM_19 IVDD_18 T13
AN23 VCCM_20 IVDD_19 U13
AN25 VCCM_21 IVDD_20 U22
AN27 VCCM_22 IVDD_21 V13
AN29 VCCM_23 W13
PWR IVDD_22 W22
IVDD_23
+V1.8S AP3 VCC1.8_01 IVDD_24 AA13
AB12 VCC1.8_02 IVDD_25 AA22
VCC1.8/VDDVB1.8/PVDDH(Total): AB13 VCC1.8_03 IVDD_26 AB14
160mA@+1.8V for 671DX estimated AC12 VCC1.8_04 IVDD_27 AB15
AC13 VCC1.8_05 IVDD_28 AB16
AC14 VCC1.8_06 IVDD_29 AB18
IO driving power AC15 VCC1.8_07 IVDD_30 AB20
AH6 VCC1.8_08 IVDD_31 AB22
AH7 VCC1.8_09 IVDD_32 AF6
AJ4 VCC1.8_10 IVDD_33 AF7
+V1.8S AJ5 AK3
VCC1.8_11 IVDD_34
AJ6 VCC1.8_12 IVDD_35 AG4
C AJ7 AG5 C
VCC1.8_13 IVDD_36
AN2 VCC1.8_14 IVDD_37 AG6
C103 C95 C67 C125 C126 C66 AK4 AG7
VCC1.8_15 IVDD_38
AK5 VCC1.8_16 IVDD_39 R13
10UF/6.3V,X5R C0603 0.1UF/10V,X7R C0603 C0603 0.1UF/10V,X7R AL1 AH3
C0805 1uF/10V,X7R C0402 1uF/10V,X7R1uF/10V,X7R C0402 VCC1.8_17 IVDD_40
AL2 VCC1.8_18 IVDD_41 AH4
AL3 VCC1.8_19 IVDD_42 AH5
AL4 VCC1.8_20 IVDD_43 AJ1
AM1 VCC1.8_21 IVDD_44 AJ2
Place these capacitors AM2 VCC1.8_22 IVDD_45 AJ3
under 671DX solder side AM3 VCC1.8_23 IVDD_46 AK1
AN3 VCC1.8_24 IVDD_47 AK2
AN5 VCC1.8_25 IVDD_48 AC22
+V1.2S_PCIE connect to +V1.2S. IO driving power AC17
timing behind +V1.8S IVDD_51
+V1.8S E8 VDDVB1.8_01
Layout note: F9 A19
VDDVB1.8_02 VTT_01 +V1.05S
将VDDPEX[0~11]单独切一Shape,与其他+1.2S连接! F8 A20
VDDVB1.8_03 VTT_02
+V1.2S VTT_03 B19 CPU VTT power
E10 VDD1.8_01 VTT_04 B20
F10 VDD1.8_02 VTT_05 C19
VTT_06 C20
IO driving power VTT_07 D19
C90 C74 C82 C99 C92 C97 +V1.8S N19 D20
PVDDH_01 VTT_08
N21 PVDDH_02 VTT_09 E19
10UF/6.3V,X5R C0603 0.1UF/10V,X7R C0603 C0603 0.1UF/10V,X7R P20 E20 +V1.05S
C0805 1uF/10V,X7R C0402 1uF/10V,X7R1uF/10V,X7R C0402 PVDDH_03 VTT_10
P22 PVDDH_04 VTT_11 F19
R21 PVDDH_05 VTT_12 F20
B B
T22 PVDDH_06 VTT_13 G19
U21 G20 C58 C55 C57 C47 C59 C61
PVDDH_07 VTT_14
V22 PVDDH_08 VTT_15 L18
Place these capacitors L19 10UF/6.3V,X5R C0603 0.1UF/10V,X7R C0603 C0603 0.1UF/10V,X7R
VTT_16 C0805 1uF/10V,X7R C0402 1uF/10V,X7R1uF/10V,X7R C0402
under 671DX solder side +V1.2S M11 VDDPEX_01 VTT_17 L20
N11 VDDPEX_02 VTT_18 M20
600mA@+1.2V for 671DX estimated P11 VDDPEX_03 VTT_19 M21
R11 VDDPEX_04 VTT_20 M22
T11 VDDPEX_05 VTT_21 M23
+V1.2AL generated from +V1.8AL PXE digital power U11 VDDPEX_06 VTT_22 N23
+V1.2AL +V1.8AL
V11 VDDPEX_07 VTT_23 P23 Place these capacitors
W11 VDDPEX_08 VTT_24 R23 under 671DX solder side
Y11 VDDPEX_09 VTT_25 T23
AA11 VDDPEX_10 VTT_26 U23
AB11 VDDPEX_11 VTT_27 V23
C54 C48 C60 C62 M12 +V1.8S
VTTP_01
VTTP_02 N12
C0603 C0603 C0603 C0603 +V1.2AL B5 P12 IO driving power
1uF/10V,X7R1uF/10V,X7R 1uF/10V,X7R1uF/10V,X7R AUX_IVDD_01 VTTP_03
C5 AUX_IVDD_02 VTTP_04 R12
+V1.2AL:38mA D6 AUX_IVDD_03 VTTP_05 T12
VTTP_06 U12
VTTP_07 V12
+V1.8AL G8 AUX1.8 VTTP_08 W12
Place these capacitors VTTP_09 Y12
under 671DX solder side +V1.8AL:38mA VTTP_10 AA12
A A
TOPSTAR TECHNOLOGY
M672 A1
Echo liu
BGA847
Page Name Crestline(VSS&NCTF)
A3 S42C A
5 4 3 2 1
5 4 3 2 1
AG31
AG33
AC31
AC33
AD29
AH29
AN11
AN13
AN15
AN17
AA16
AA17
AA18
AA19
AA20
AA21
AA31
AA33
AB29
AE31
AE33
AK31
AF29
AL10
AL12
AL14
AL16
AL18
AL20
AL28
AL30
AL33
AJ10
AJ12
AJ14
AJ16
AJ18
AJ20
AJ26
AJ28
AJ33
AG2
AC2
AC3
AD2
AD3
AD4
AD5
AD7
AH1
AB3
AB4
AB5
AB7
AE3
AF2
AF3
AF4
AF5
AL6
AL8
AJ8
U12F
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
A3 VSS_64
B2 VSS_65 VSS_125 T29
B3 VSS_66 VSS_126 U2
D D
B4 VSS_67 VSS_127 U3
VSS_128 U4
B21 VSS_68 VSS_129 U5
B23 VSS_69 VSS_130 U6
B25 VSS_70 VSS_131 U14
B27 U15 PCB10
VSS_71 VSS_132 PCB S42G MB VerA L6 215.14*285.9*1.2 NPB
B29 VSS_72 VSS_133 U16
B31 VSS_73 VSS_134 U17
C1 U18
C2
VSS_74
VSS_75
VSS_135
VSS_136 U19 PCB
C3 U20 PCB
VSS_76 VSS_137
C4 VSS_77 VSS_138 U31
U33 PCBA10
VSS_139 PCBA S42G MB VerA NPB
VSS_140 V2
C9 VSS_78 VSS_141 V3
C10 V4
C11
VSS_79
VSS_80
VSS_142
VSS_143 V5 PCBA
C16 V14 PCBA
VSS_81 VSS_144
C18 VSS_82 VSS_145 V15
C32 VSS_83 VSS_146 V16
C33 VSS_84 VSS_147 V17
D1 VSS_85 VSS_148 V18
D2 VSS_86 VSS_149 V19
C D3 VSS_87 VSS_150 V20 C
D4 VSS_88 VSS_151 V29
D5 VSS_89 VSS_152 AN33
D10 GND AN31
VSS_90 VSS_153
D12 VSS_91 VSS_154 AN19
D21 VSS_92 VSS_155 W3
D23 VSS_93 VSS_156 W14
D25 VSS_94 VSS_157 W15
D27 VSS_95 VSS_158 W16
D29 VSS_96 VSS_159 W17
E1 VSS_97 VSS_160 W18
E2 VSS_98 VSS_161 W19
E3 VSS_99 VSS_162 W20
E6 VSS_100 VSS_163 W21
E11 VSS_101 VSS_164 W31
E13 VSS_102 VSS_165 W33
E14 VSS_103 VSS_166 Y2
E18 VSS_104 VSS_167 Y3
E29 VSS_105 VSS_168 Y4
E30 VSS_106 VSS_169 Y5
E33 VSS_107 VSS_170 Y7
F2 VSS_108 VSS_171 Y14
F3 VSS_109 VSS_172 Y15
F4 VSS_110 VSS_173 Y16
B F5 VSS_111 VSS_174 Y17 B
F6 VSS_112 VSS_175 Y18
F14 VSS_113 VSS_176 Y19
F22 VSS_114 VSS_177 Y20
F24 VSS_115 VSS_178 Y21
F26 VSS_116 VSS_179 Y29
F28 VSS_117 VSS_180 AA2
G2 VSS_118 VSS_181 AA3
G3 VSS_119 VSS_182 AA14
G7 VSS_120 VSS_183 AA15
G10 VSS_121 VSS_184 AB17
P21 VSS_122 VSS_185 AB19
T21 VSS_123 VSS_186 AB21
V21 VSS_124 VSS_187 P19
VSS_01
VSS_02
VSS_03
VSS_04
VSS_05
VSS_06
VSS_07
VSS_08
VSS_09
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
M672 A1
G31
G33
H4
H5
H29
J2
J3
J7
J31
J33
K3
K4
K5
K29
L2
L3
L4
L5
L7
L31
L33
M2
M3
M29
N3
N4
N5
N6
N7
N14
N15
N31
N33
P2
P3
P14
P15
P16
P17
P18
P29
R2
R3
R4
R5
R14
R15
R16
R17
R18
R19
R20
R31
R33
T3
T6
T14
T15
T16
T17
T18
T19
T20
BGA847
TOPSTAR TECHNOLOGY
A Echo liu A
Page Name Crestline(POWER)
B S42C A
5 4 3 2 1
hexainf@hotmail.com
GRATIS - FOR FREE
5 4 3 2 1
+V3.3S 6,7,11,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
DIM1
+V1.8 6,10,12,15,16,36,38,40,41,44
+V1.8 DDR2_SODIMM200
DDR200RVS_5D2
SO-DIMM 0
112
111
117
118
103
104
187
178
190
155
132
144
156
168
149
161
138
150
162
96
95
81
82
87
88
21
33
34
15
27
39
28
40
9
2
3
10,15,16 MA_A_A[10:0]
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
MA_DATA[63:0] 10,15
D MA_A_A0 MA_DATA0 D
102 A0 D0 5
MA_A_A1 101 7 MA_DATA1 Change into 0.1uF CAP. x4 and 470uF x1 Per DIMM
MA_A_A2 A1 D1 MA_DATA2
100 A2 D2 17
MA_A_A3 99 19 MA_DATA3
MA_A_A4 A3 D3 MA_DATA4 +V1.8 +V1.8
98 A4 D4 4
94 A6 D6 14
1
MA_A_A7 92 16 MA_DATA7 C178
MA_A_A8 A7 D7 MA_DATA8 C625 C626 C627 C628 C629 C630
93 23 +
1
91 A9 D9 25
MA_A_A10 105 35 MA_DATA10 CT7343_19 C0402 C0402 C0402 C0402 C0402 C0402
2
A10/AP D10 MA_DATA11
10,15,16 MA_A_A11 90 A11 D11 37
89 20 MA_DATA12 0.1UF/25V,Y5V
220UF/2.5V,POSCAP 0.1UF/25V,Y5V0.1UF/25V,Y5V0.1UF/25V,Y5V
0.1UF/25V,Y5V0.1UF/25V,Y5V
10,15,16 MA_A_A12 A12 D12
116 22 MA_DATA13 ns
10,15,16 MA_A_A13 A13 D13
86 36 MA_DATA14
10,15,16 MA_A_A14 A14 D14
84 38 MA_DATA15
A15 D15 MA_DATA16
10,15,16 MA_A_BS#2 85 A16_BA2 D16 43
45 MA_DATA17
D17 MA_DATA18 +V1.8
10,15,16 MA_A_BS#0 107 BA0 D18 55
106 57 MA_DATA19
10,15,16 MA_A_BS#1 BA1 D19
44 MA_DATA20
D20 MA_DATA21
10,16 M_CS#0 110 CS0 D21 46
115 56 MA_DATA22
10,16 M_CS#1 CS1 D22 MA_DATA23
C D23 58 C
MA_DM0 10 61 MA_DATA24 C165 C163 C166 C208 C179 C171
MA_DM1 DQM0 D24 MA_DATA25
26 DQM1 D25 63
MA_DM3 DQM2 D26 MA_DATA27 2.2UF/10V,X7R
67 DQM3 D27 75
MA_DM4 130 62 MA_DATA28 0.1UF/25V,Y5V0.1UF/25V,Y5V0.1UF/25V,Y5V
0.1UF/25V,Y5V
0.1UF/25V,Y5V
147 DQM5 D29 64
MA_DM6 170 74 MA_DATA30 Layout note:电容靠近DDR slot VDD PIN
10,15 MA_DM[7:0] MA_DM7 DQM6 D30 MA_DATA31
185 DQM7 D31 76
DDRII
123 MA_DATA32
D32 MA_DATA33
10,15,16 MA_A_WE# 109 WE D33 125
113 135 MA_DATA34
10,15,16 MA_A_CAS# CAS D34
108 137 MA_DATA35
10,15,16 MA_A_RAS# RAS D35
124 MA_DATA36
D36 MA_DATA37
10,16 M_CKE0 79 CKE0 D37 126
80 134 MA_DATA38 Note:
10,16 M_CKE1 CKE1 D38 MA_DATA39 +V1.8 Selected by layout to seperated from
D39 136
30 141 MA_DATA40 other sensitive signal trace.
6 MEM_CHA_CLK0 CK0 D40 MA_DATA41
6 MEM_CHA_CLK#0 32 CK0 D41 143
164 151 MA_DATA42 C190
6 MEM_CHA_CLK1 CK1 D42 MA_DATA43 R213 0.1UF/25V,Y5V
6 MEM_CHA_CLK#1 166 CK1 D43 153
140 MA_DATA44 1K,1% C0402
D44 MA_DATA45 R0402
10,16 M_ODT0 114 ODT0 D45 142
119 152 MA_DATA46 ns 0
10,16 M_ODT1 ODT1 D46
B 154 MA_DATA47 DIMM_VREF_A R209 B
D47 15 DIMM_VREF_A SM_VREF 10,36
MA_DQS0 13 157 MA_DATA48 R0603
MA_DQS1 DQS0 D48 MA_DATA49
31 DQS1 D49 159
MA_DQS2 51 173 MA_DATA50 R214 C191
MA_DQS3 DQS2 D50 MA_DATA51 1K,1% 0.1UF/25V,Y5V
70 DQS3 D51 175
MA_DQS4 131 158 MA_DATA52 R0402 C0402
MA_DQS5 DQS4 D52 MA_DATA53 ns
148 DQS5 D53 160
MA_DQS6 169 174 MA_DATA54
10,15 MA_DQS[7:0] MA_DQS7 DQS6 D54 MA_DATA55
188 DQS7 D55 176
179 MA_DATA56 close to DDR pin
D56 MA_DATA57
D57 181
195 189 MA_DATA58
6,15,21,26,28 SMB_DATA_S SDA D58 MA_DATA59
6,15,21,26,28 SMB_CLK_S 197 SCL D59 191
180 MA_DATA60
R207 10K R0402 D60 MA_DATA61
198 SA0 D61 182
Note: R206 10K R0402 MA_DATA62
SO-DIMM0 SPD Address is 0xA0
200 SA1 1010 000x D62 192
MA_DATA63
D63 194
+V3.3S SO-DIMM0 TS Address is 0x30 ??///?????
199 11 MA_DQS#0
VDDSPD DQS#0 MA_DQS#1
DQS#1 29
DIMM_VREF_A 1 49 MA_DQS#2
0.1UF/25V,Y5V C173 VREF1 DQS#2 MA_DQS#3
DQS#3 68
C170 C172 129 MA_DQS#4 TOPSTAR TECHNOLOGY
ns DQS#4 MA_DQS#5
83 NC1 DQS#5 146
A C0402 2.2UF/10V,X7R C0603 MA_DQS#6 Echo liu A
120 NC2 DQS#6 167
C0805 1uF/10V,X7R 50 186 MA_DQS#7 Page Name
NC3 DQS#7 DDRII SODIMM0
69 MA_DQS#[7:0] 10,15
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
NC4
GND0
GND1
Size
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
163 NCTEST Project Name Rev

B S42C
A
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
201
202
5 4 3 2 1
5 4 3 2 1
+V3.3S 6,7,11,14,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
DIM2
+V1.8 6,10,12,14,16,36,38,40,41,44
+V1.8 DDR2_SODIMM200
DDR200RVS_9D2C
SO-DIMM 1
112
111
117
118
103
104
187
178
190
155
132
144
156
168
149
161
138
150
162
96
95
81
82
87
88
21
33
34
15
27
39
28
40
9
2
3
10,14,16 MA_A_A[10:0]
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
MA_DATA[63:0] 10,14
D MA_A_A0 MA_DATA0 D
102 A0 D0 5
MA_A_A1 101 7 MA_DATA1 +V1.8
100 A2 D2 17
98 A4 D4 4
1
MA_A_A5 97 6 MA_DATA5 C167
94 14 +
1
92 A7 D7 16
MA_A_A8 93 23 MA_DATA8 CT7343_19
2
91 A9 D9 25
MA_A_A10 105 35 MA_DATA10 220UF/2.5V,POSCAP
A10/AP D10 MA_DATA11
10,14,16 MA_A_A11 90 A11 D11 37
89 20 MA_DATA12
10,14,16 MA_A_A12 A12 D12
116 22 MA_DATA13
10,14,16 MA_A_A13 A13 D13
86 36 MA_DATA14
10,14,16 MA_A_A14 A14 D14
84 38 MA_DATA15
A15 D15 MA_DATA16 +V1.8
10,14,16 MA_A_BS#2 85 A16_BA2 D16 43
45 MA_DATA17
D17 MA_DATA18
10,14,16 MA_A_BS#0 107 BA0 D18 55
106 57 MA_DATA19
10,14,16 MA_A_BS#1 BA1 D19
44 MA_DATA20
D20 MA_DATA21
10,16 M_CS#2 110 CS0 D21 46
115 56 MA_DATA22 C210 C162 C134 C164 C209 C207
10,16 M_CS#3 CS1 D22 MA_DATA23 DIMM2 DIMM2 DIMM2 DIMM2 DIMM2 DIMM2
C D23 58 C
MA_DM1 DQM0 D24 MA_DATA25 2.2UF/10V,X7R0.1UF/25V,Y5V0.1UF/25V,Y5V0.1UF/25V,Y5V0.1UF/25V,Y5V0.1UF/25V,Y5V
26 DQM1 D25 63
MA_DM2 52 73 MA_DATA26
67 DQM3 D27 75
MA_DM4 130 62 MA_DATA28 Layout note:电容靠近DDR slot VDD PIN
147 DQM5 D29 64
MA_DM6 170 74 MA_DATA30
10,14 MA_DM[7:0] MA_DM7 DQM6 D30 MA_DATA31
185 DQM7 D31 76
DDRII
123 MA_DATA32
D32 MA_DATA33
10,14,16 MA_A_WE# 109 WE D33 125
113 135 MA_DATA34
10,14,16 MA_A_CAS# CAS D34
108 137 MA_DATA35
10,14,16 MA_A_RAS# RAS D35
124 MA_DATA36
D36 MA_DATA37
10,16 M_CKE2 79 CKE0 D37 126
80 134 MA_DATA38
10,16 M_CKE3 CKE1 D38 MA_DATA39
D39 136
30 141 MA_DATA40
6 MEM_CHA_CLK#2 32 CK0 D41 143
164 151 MA_DATA42
6 MEM_CHA_CLK#3 166 CK1 D43 153
140 MA_DATA44
D44 MA_DATA45
10,16 M_ODT2 114 ODT0 D45 142
119 152 MA_DATA46
10,16 M_ODT3 ODT1 D46
B 154 MA_DATA47 B
MA_DQS0 D47 MA_DATA48
13 DQS0 D48 157
51 DQS2 D50 173
131 DQS4 D52 158
10,14 MA_DQS[7:0] 169 DQS6 D54 174
DQS7 D55 MA_DATA56
D56 179
181 MA_DATA57
D57 MA_DATA58
6,14,21,26,28 SMB_DATA_S 195 SDA D58 189
197 191 MA_DATA59
6,14,21,26,28 SMB_CLK_S SCL D59 MA_DATA60
D60 180
DIMM2 R438 10K R0402 198 182 MA_DATA61
Note: DIMM2 R439 10K R0402 SA0 D61 MA_DATA62
+V3.3S SO-DIMM1 SPD Address is 0xA2
200 SA1 1010 001x D62 192
MA_DATA63
D63 194
SO-DIMM1 TS Address is 0x3X ????////??
199 11 MA_DQS#0
VDDSPD DQS#0 MA_DQS#1
DQS#1 29
0.1UF/25V,Y5V DIMM_VREF_A 1 49 MA_DQS#2
14 DIMM_VREF_A VREF1 DQS#2
C189 C183 68 MA_DQS#3
DIMM2 C188 DQS#3 MA_DQS#4
DQS#4 129 TOPSTAR TECHNOLOGY
C0402 ns/DIMM2 DIMM2 83 146 MA_DQS#5
A 2.2UF/10V,X7R C0603 NC1 DQS#5 MA_DQS#6 Echo liu A
120 NC2 DQS#6 167
C0805 1uF/10V,X7R 50 186 MA_DQS#7 Page Name
NC3 DQS#7 DDRII SODIMM0
69 MA_DQS#[7:0] 10,14
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
NC4
GND0
GND1
Size
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
163 NCTEST Project Name Rev

B S42C
A
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
201
202
5 4 3 2 1
DIMM2
hexainf@hotmail.com
GRATIS - FOR FREE
5 4 3 2 1
+V0.9S 36,41
+V1.8 6,10,12,14,15,36,38,40,41,44
D D
+V0.9S RA0402_8
+V0.9S
每4个电阻两个0.1UF电容
56x4
1 2 MA_A_BS#1
3 4 C193 C192 C198 C202
M_CS#2 10,15 C195 C200 C199 C194 C201
5 6 MA_A_RAS# 10,14,15 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
0.1UF/25V,Y5V C0805 C0805
7 8 M_ODT2 10,15 C0402 C0402 C0402 C0402 C0402 C0402
C0402
RN19 4.7uF/10V,X5R 4.7uF/10V,X5R
RN20 56x4 RA0402_8
1 2 MA_A_A13
3 4 M_ODT1 10,14
5 6 M_ODT0 10,14
7 8 M_CS#1 10,14
+V0.9S
RN14 56x4 RA0402_8

C 1 2 MA_A_A1 C
3 4 MA_A_A5 C184 C187 C175
C181 C174 C186 C185
5 6 MA_A_A8
0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
7 8 MA_A_A9
C0402 C0402 C0402 C0402 C0402 C0402 C0402
RN18 56x4 RA0402_8

1 2 MA_A_A6
3 4 MA_A_A4 +V1.8
5 6 MA_A_A2
7 8 MA_A_A0 +V0.9S
1 2 M_CKE3 10,15 C502 C501 C500

3 4 MA_A_A14
MA_A_A11 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
5 6 C0402 C0402 C0402
7 8 MA_A_A7
RN17 56x4 RA0402_8

B RN16 56x4 RA0402_8 B
1 2 +V1.8
M_CS#3 10,15
3 4 M_ODT3 10,15
5 6 MA_A_CAS# 10,14,15
7
RN13 56x4
8
RA0402_8
M_CS#0 10,14 Layout note:
1 2 MA_A_A12 1.Place one cap every 2 terminated resistors;
MA_A_BS#2
3
5
4
6
2.Place +V1.8 to +V0.9 Caps by their power shape;
M_CKE0 10,14
7 8 M_CKE1 10,14 3.BOM costdown by layout or by test.
RN15 56x4 RA0402_8
1 2 MA_A_WE# 10,14,15
3 4 MA_A_BS#0
10,14,15 MA_A_A[10:0]
5 6 MA_A_A10
10,14,15 MA_A_BS#0
7 8 MA_A_A3
10,14,15 MA_A_BS#1
10,14,15 MA_A_BS#2
10,14,15 MA_A_A11 TOPSTAR TECHNOLOGY
R212 56 R0402
M_CKE2 10,15 10,14,15 MA_A_A12
10,14,15 MA_A_A13 Echo liu
10,14,15 MA_A_A14 Page Name
A DDRII Series Termination A
A4 S42C
A
5 4 3 2 1
5 4 3 2 1
+V1.8S 9,10,11,12,20,21,22,23,38,39,44
+V5S 18,19,24,25,29,30,31,32,37,38,39,41,42,44
+V3.3S 6,7,11,14,15,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
C526 0.1UF/10V,X7R
HDVBN2 9
C527 0.1UF/10V,X7R
HDVBP2 9
C528 0.1UF/10V,X7R
HDVBN1 9
+V1.8S +V1.8S
C529 0.1UF/10V,X7R
HDVBP1 9
FB49 120ohm/100MHz,500mA PCIEVDD FB50 120ohm/100MHz,500mA 307PCIEAVDD C530 0.1UF/10V,X7R
HDVBN0 9
FB0603 FB0603
C539 0.1UF/10V,X7R
HDVBP0 9
C531 C532 C533 C534 C535 C536 C605 C537 C538 C540 C606
C0805 C0805 C0805 C0805 C541 0.1UF/10V,X7R
D HDVAN2 9 D
10uF/6.3V,X5R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R0.1uF/10V,X7R 0.1uF/10V,X7R ns 10uF/6.3V,X5R 0.1uF/10V,X7R0.01uF/25V,X7R ns
10uF/6.3V,X5R 10uF/6.3V,X5R C542 0.1UF/10V,X7R
HDVAP2 9
C543 0.1UF/10V,X7R
HDVAN1 9
C544 0.1UF/10V,X7R
HDVAP1 9
307PCIEAVDD
C545 0.1UF/10V,X7R
HDVAN0 9
PCIEVDD
C546 0.1UF/10V,X7R
HDVAP0 9
+V3.3S
M13
M12
M11
M10
N12
N13
N10
N11
K10
K12
L11
L10
M9
M8
M7
M6
M5
M4
M3
M2
M1
N1
N8
N9
N6
N7
N4
N5
N2
N3
K5
K6
K7
K8
K9
K3
K4
L9
L6
L1
L2
L3
J5
J6
J7
J8
J9
R523 0 PCIEVDD3V U23
HDVPLLVSS
VSS37
VSS16
VSS17
VSS36
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
HDVPHYVDD1
HDVPHYVDD2
HDVPHYVDD3
HDVPHYVDD4
HDVPHYVDD5
HDVPHYVDD6
HDVPHYVDD7
HDVPHYVDD8
HDVPHYVDD9
HDVPHYVDD10
HDVPHYVDD11
HDVBN2
HDVBP2
HDVBN1
HDVBP1
HDVBN0
HDVBP0
HDVAN2
HDVAP2
HDVAN1
HDVAP1
HDVAN0
HDVAP0
HDVPLLVDD
C547 C607
C0805
0.1uF/10V,X7R ns
10uF/6.3V,X5R
+V1.8S PCIEVDD3V G10 VDD33
G4 IVDD0 HDVREFCLKN L7 307_PCIE_CLK# 6
H4 IVDD1 HDVREFCLKP L8 307_PCIE_CLK 6
J4 L4 R524 R0603 499,1% 307ELV: install R639.
C548 C550 C549 C551 C608 IVDD2 HDVRSET0 R525 124,1%
H10 IVDD3 HDVRSET1 L5
C0805 H11 C552 0.1uF/10V,X7R AGND
0.1uF/10V,X7R0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R ns IVDD4 ns
H12 IVDD5 VACLK K13 VACLK 11
10uF/6.3V,X5R R638 0
H13 IVDD6 VBCLK J12
K11
VBCLK 11 Side-Band V2COMP R639 0
VBHSYNC VBHSYNC 11
F5 VSS0 VBVSYNC J11 VBVSYNC 11 signals +V3.3S
F6 VSS1 VBHCAD L13 VBCAD 11
F7 VSS2 VBHCLK L12 VBHCLK 11
F8 VB_DACVDD 120ohm/100MHz,500mA FB51
VSS3 R641 0 FB0603
F9 VSS4 EXTRSTN F13 NB_RST# 11,20
G5 E11 VB_GPIOF R640ns 0
VSS5 GPIOF/DVINTN PCI_INTA# 9,11,20
C G6 E10 C554 C555 C604 C
VSS6 PFTESTO C0805
G7 F10 307LV/ELV: NS R640
ADD 307ELV
G8
G9
H5
VSS7
VSS8
VSS9
VSS10
307LV/ELV//307DV/307CP PFTEST1
PFTEST2
DACRSET
G11
B2 V2RSET R526
307LV/ELV: NS R527,install R526
0 VB_DACVDD
0.1uF/10V,X7R 0.01uF/25V,X7R 10uF/6.3V,X5R
H6 B1 V2COMP
VSS11 DACCOMP R527 ns 115 这个电阻没有partnumber
H7 VSS12 TVDACR D2
H8 D1 AGND +V3.3S
VSS13 TVDACG
H9 VSS14 TVDACB E2
J10 E1 AGND
VSS15 TVCSYNC VB_PLL1VDD 120ohm/100MHz,500mA FB52
G2 C2 VB_DACVDD FB0603
GPIOA DACVDD R642 0 R0603
H2 GPIOB DACVSS1 C1
1.8V CMOS output H1 D3 C609 C558 C559 C560
GPIOC DACVSS2 C0805 C0805
G1 GPIOD DACVSS3 E3
R649 0 G13 E4 ns 0.1uF/10V,X7R 0.01uF/25V,X7R 10uF/6.3V,X5R
18 307LVDS_VDDEN R650 0 LCDVDD_EN//GPIOG DACVSS4 AGND 10uF/6.3V,X5R
18 LVDS_BKLTEN G12 BL_EN//GPIOH DACVSS5 F4
F11 AGND
LVDSPHYVSS//TMDSPHYVSS10
GPIOI
LVDSPHYVDD//TMDSPHYVDD1
VB_PLL1VDD
F3 GPIOJ COREPLLVDD K2
LVDSPLLVDD//TMDSPLLVDD
VBRCLK R528 0 +V5S +V3.3S
LVDSPLLVSS//TMDSPLLVSS
G3 GPIOK VBRCLK J2 CLK14_307 6
F2 J1 VBOSCO
GPIOL VBOSCO
F1 GPIOM COREPLLVSS K1
H3 GPION
J3 GPIOO LDIDDCCLK//DVIDDCCLK F12 LDDCCLK 18
E13 R529 R530 R667 R668
LDIDDCDATA//DVIDDCDATA LDDCDATA 18
LXC2N//DXC1N
LXC2P//DXC1P
E12 VB_GPIOE R643 ns 0 2.2K 2.2K 2.2K 2.2K

BL_ADJ//DVIHPD LVDS_BKLTPWM 18
LXC1N//NC2
LXC1P//NC1
LX4N//DX0N
LX5N//DX1N
LX6N//DX2N
LX2N//NC12
LX0N//NC10
LX4P//DX0P
LX5P//DX1P
LX6P//DX2P
LX2P//NC11
EXTSWING
LX3N//NC6
LX1N//NC4
LX7N//NC8
LX3P//NC5
LX1P//NC3
LX0P//NC9
LX7P//NC7
3.3V CMOS output ns ns
LDDCCLK LDDCCLK
LDDCDATA LDDCDATA
NC1
NC2
Y7 14.31818M 3.0mm
VBRCLK R644 10 ns 1 2 XS2 VBOSCO
BGA169 ns
C13
A12
A13
C11
C12
A10
A11
C9
C10
A8
A9
C7
C8
A6
A7
C5
C6
A4
A5
C3
C4
E5
E6
E7
E8
E9
D10
D11
D12
D13
B3
A2
A3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
D4
D5
D6
D7
D8
D9
A1
J13
VB_LAVDD R531 ns 1.65K,1% 确认LDCCLK到底是5V或者是3.3V的电平
C561 C562
R532 R0603 6.04K,1% EXTSWING 33pF/50V,NPO 33pF/50V,NPO
307LV/ELV//307DV/307CP C0603 C0603
R533 23.7K,1% ns ns
B B
Demo是24K，现在用23.7K代替
C563 VB_LVDSPLLVDD
1uF/10V,Y5V VB_LAVDD +V3.3S
C0603
FB53 120ohm/100MHz,500mA VB_LAVDD

FB0603
18 LVDS_YAP2 LVDS_YBM2 18
18 LVDS_YAM2 R534 ns 200,1% C564 C565 C566 C567 C568 C569 C610
C0805 C0805
18 LVDS_YAP1 LVDS_YBP2 18
10uF/6.3V,X5R 0.1uF/10V,X7R0.1uF/10V,X7R0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R ns
18 LVDS_YAM1 10uF/6.3V,X5R
LVDS_YBM1 18
18 LVDS_YAP0 R535 ns 200,1%
18 LVDS_YAM0
LVDS_YBP1 18
+V3.3S
18 LVDS_CLKAP
18 LVDS_CLKAM LVDS_YBM0 18 307LV/ELV: NS R534,R535,R536 and R537.
R536 ns 200,1% FB54 120ohm/100MHz,500mA VB_LVDSPLLVDD
FB0603
LVDS_YBP0 18
C570 C571 C572 C611
C0805 C0805
LVDS_CLKBM 18
10uF/6.3V,X5R 0.1uF/10V,X7R 0.01uF/25V,X7R ns
R537 ns 200,1% 10uF/6.3V,X5R
LVDS_CLKBP 18
A A
TOPSTAR TECHNOLOGY
Echo liu
Page Name 307LVDS
C S42C
A

5 4 3 2 1
+V3.3AL
R651
10K
BKLT_Control
BKLT_ON
+V3.3S 6,7,11,14,15,17,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
+VDC 28,33,35,36,37,38,41,42,44
+V3.3AL 6,20,21,22,23,26,27,28,29,30,32,33,34,35,36,37,38,39,40,42,44
Level shift.1.8V to 3.3V +V5AL 25,27,29,32,35,36,38,39,40
+V5S 17,19,24,25,29,30,31,32,37,38,39,41,42,44
3
D
1.8V CMOS input D
R663 1K 2 5 BKLT_Control LCDVDD
17 LVDS_BKLTEN
Q52 +V3.3S
R652 ns 100K MMDT3904
4
SC70_6
307IC内部有下拉 LCDCON1
R288
1K 1 2
R0402 1 2
3 3 4 4
17 LVDS_YAM0 LVDS_YAM0 5 6 LVDS_YAM1 LVDS_YAM1 17
17 LVDS_YAP0 LVDS_YAP0 5 6 LVDS_YAP1 LVDS_YAP1 17
7 7 8 8
D35 2 1 1N4148WS BKLT_ON 9 10
29,30 LIDR# 9 10
SOD323 17 LVDS_YAM2 LVDS_YAM2 11 12 LVDS_CLKAP LVDS_CLKAP 17
17 LVDS_YAP2 LVDS_YAP2 11 12 LVDS_CLKAM LVDS_CLKAM 17
13 13 14 14
D13 2 1 1N4148WS C237 15 16
30 HW_OFF_BKLT# SOD323 17 LVDS_YBM0 LVDS_YBM0 15 16 LVDS_YBM1 LVDS_YBM1 17
17 17 18 18
1000pF/50V,X7R 17 LVDS_YBP0 LVDS_YBP0 19 20 LVDS_YBP1 LVDS_YBP1 17
C0402 19 20
21 21 22 22
17 LVDS_YBM2 LVDS_YBM2 23 24 LVDS_CLKBP LVDS_CLKBP 17
LCDVDD 17 LVDS_YBP2 LVDS_YBP2 23 24 LVDS_CLKBM LVDS_CLKBM 17
25 25 26 26
F1 ns 1.5A T-Fuse EDID_CLK 27 28
R0603 EDID_DATA 27 28 EDID PWR
A06409 29 29 30 30
+V3.3S LVDS_CAM_USB_PN3 31 32 +5VAL_Camera
+V3.3AL FB1 0 R0805 LCDVDD F2 ns 1.5A T-Fuse LVDS_CAM_USB_PP3 31 32 BKLT_PWM
6 1 33 33 34 34
5 D 2 +VDC R0603 35 36 BKLT_ON
FB9 35 36
4 S 3 30 IVT_I_ADJ
IVT_I_ADJ 37 37 38 38
G C2 C228 C1 R1 1 2 INVT_VDD 39 40
2.2K 39 40
Q1
R4 R3 C3 C4 C0402 10UF/6.3V,X5R C0805 R0402
41
42
100ohm@100MHz,3A
LCDVDD_EN#
10K 100K C0402 0.1UF/25V,Y5V C0805 10UF/6.3V,X5R ns C17 C0603 C16

R0402 ns C0402 ns FB0805 88242-4001
C C
41
42
ns 0.1uF/25V,X7R 0.1uF/25V,X7R
0.047uF/16V,X7R 0.01uF/16V,X7R C0603 CNS40_LCD_R1
R6 LVDS_VDDGON# ns
100K
R0402
3
Q4 +V3.3AL +V3.3S
2N7002 VerB:ns FB ,add 0ohm for cost down
LVDS_VDDEN 1 SOT23 R664 10K VDD_Control R665 10K 071025 VerB:Reverse Camera PWR control Circuit 071026
F4 0
LVDS_VDDEN ns R0603 +V5AL
2
R10
100K Level shift.1.8V to 3.3V R506 0
3
R0402 +5VAL_Camera R0603 E4
1
R666 1K 2 5 VDD_Control nsFB28
ns FB28 EMI
17 307LVDS_VDDEN ns
Q57 300ohm@100MHz,1.5A
1
MMDT3904 C231 C518 Q43 FB0805
1
4
307IC内部有下拉 SC70_6 ns AO3415
R672 C0402 10UF/6.3V,X5R
100K 0.1UF/25V,Y5V C0805 3 2
ns
LCDVDD
+VDC R64
VerB:Add 0.1uF，预留一个10uF C278 10K
1
071025
R2 C0402
VerC:change the Camera control circuit
100 R8 0.01uF/16V,X7R
R289 0 R0402 R0603 100K R69 R0402
30 EC_LVDS_BKLTCTL
1K
B B
3
FB30 ns 0 R0402 BKLT_PWM Q3
17 LVDS_BKLTPWM
6
SC70_6 Q11
2N7002
R291 LVDS_VDDEN 2 5 SOT23 1
C238 CAM_PWRON 30
10K 2N7002DW
100pF/50V,NPO
1
R0402 100pF/50V,NPO
2
C0402 C5 R9 R52
100K 100K
R0402
R11 R0603 0
R14 R0603 0
+V3.3S +V3.3AL
R279 0 R0603 EDID_CLK CHK1
17 LDDCCLK
R278 0 R0603 EDID_DATA 1 2 LVDS_CAM_USB_PN3
17 LDDCDATA 22 CAM_USB_PN3
R292 0 R0603 ns 4 3 LVDS_CAM_USB_PP3
R0402 ns 1K R280 22 CAM_USB_PP3
21 PANEL_ID1
R0402 ns 1K R277 R290 0 R0603 EDID PWR L4_0805 90ohm@100MHz,0.5A
D1 D2
21 PANEL_ID0
1
C236 ns EGA10603V05A1-B EGA10603V05A1-B
ESDPAD_R0603 ESDPAD_R0603
EDID PWR +V5S Level shift 线路 EDID PWR 0.1UF/10V,X7R ns ns
2
+V5S C0402
Q53 R655 Q54 R657

A R654 BSS138 10K R656 BSS138 10K A
10K SOT23 ns 10K SOT23 ns TOPSTAR TECHNOLOGY
ns ns
LDDCCLK ns 2 EDID_CLK LDDCDATA ns 2 EDID_DATA Echo liu
3 3
Page Name
LVDS
Custom S42C
1
A
+V3.3S +V3.3S PROPERTY NOTE: this document contains information confidential and property to
5 4 3 2 1
5 4 3 2 1
AD+ 33,38
+V5S 17,18,24,25,29,30,31,32,37,38,39,41,42,44
+V3.3S +V3.3S
+V3.3S 6,7,11,14,15,17,18,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
88242_3001
R = C
G = Y 32 R24 R26
B = NOT USED/BS CRT_RED_R 32 390,5% 390,5%
30 30 29 29
WHEN NOT USE, 75 OHM TO GND 28 27 CRT_BLUE_R R0402 R0402
CRT_GREEN_R 28 27
26 26 25 25
24 24 23 23 CRT_HSYNC 11
22 22 21 21 CRT_VSYNC 11
20 19 5VDDCCK
20 19 5VDDCDA S42C/Change 0603 to 0402.LJ0912
Place close to VGA_CONN2 18 18 17 17
16 16 15 15
D +V5S 14 14 13 13 +V5S D
FB8 12 11
47ohm@100MHz,500mA 12 11
10 10 9 9
1FB0603 2 CRT_RED_R 8 7
11 CRT_RED 8 7
AD+ 6 6 5 5 AD+
C12 4 4 3 3
2 2 1 1
5.6pF/50V,NPO 31
C0402 31
ns
CNS30_LCDB
VGA_CONN1
FB10
47ohm@100MHz,500mA
1FB0603 2 CRT_GREEN_R
11 CRT_GREEN
C14
5.6pF/50V,NPO
C0402
ns
FB6
Video Board CONN
47ohm@100MHz,500mA
1FB0603 2 CRT_BLUE_R
11 CRT_BLUE
C10
5.6pF/50V,NPO
C0402
ns +V3.3S
R7 Q5
C 8.2K BSS138 C
R0402 SOT23
2 3 5VDDCCK
11 CRT_DDC_CLK
+V3.3S
1
+V3.3S
R5 Q2
8.2K BSS138
R0402 SOT23
2 3 5VDDCDA
11 CRT_DDC_DATA
+V3.3S
1
B B
A A
TOPSTAR TECHNOLOGY
Echo liu
Page Name CRT CONN & S TV OUT & LIDR SWITCH
C S42C
A

5 4 3 2 1
+V3.3S 6,7,11,14,15,17,18,19,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
+V3.3AL 6,18,21,22,23,26,27,28,29,30,32,33,34,35,36,37,38,39,40,42,44
+V1.8S 9,10,11,12,17,21,22,23,38,39,44
====>> Cost down
+V3.3S
RN12 1.Place the circuit of noise filters as close to 671DX as possible.

1 2 PCI_INTC#
3 4 PCI_INTD# 2.Every trace depicted in the figures should be kept as short as possible.
5 6 PCI_INTB# 3.The recommend trace width in the figures is at least 15 mil whenever possibly.
7 8 PCI_INTA#
D D
8.2K
RA0603_8
RN9
1 2 PCI_IRDY#
3 4 PCI_STOP# +V1.8S
5 6 PCI_LOCK# 8mA@+V1.8S/SO
7 8 PCI_SERR# U5A
M1
M2
M4
H5
R1
R2
R4
R3
U1
U2
U4
U3
IDEAVDD FB0603 1FB43
K1
K2
K4
K3
K5
P3
P5
V1
T1
T2
T4
T3
T5
L2
L4
L3
L5
2
J4
J3
J5
4.7K
RA0402_8 120ohm/100MHz,500mA
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
V3 IDEAVDD +V3.3S C374 C382
AVDD_IDE C375
RN10 PCI_REQ4# H2 V4 IDEAVSS
PCI_REQ1# PCI_REQ3# PREQ4# AVSS_IDE 0.01uF/16V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R
1 2 H1 PREQ3#
3 4 PCI_TRDY# PCI_REQ2# G3 AE20 R752 ns 10K
PCI_DEVSEL# PCI_REQ1# PREQ2# ICHRDYA R753 ns 10K IDEAVSS
5 6 G4 PREQ1# IDREQA AB18
7 8 PCI_FRAME# PCI_REQ0# G2 AB19 R754 ns 10K
PREQ0# IIRQA R755 ns 10K
CBLIDA AC20
4.7K J2 PGNT4#
RA0402_8 J1 PGNT3# IIORA# AF20
H3 AD19 R784 ns 10K +V3.3S
PGNT2# IIOWA#
H4 PGNT1# IDACKA# AC19
RN11 G5
PCI_REQ0# PGNT0#
1 2 IDSAA2 AD21
3 4 PCI_REQ2# L1 AD20
PCI_REQ3# C/BE3# IDSAA1
5 6 M3 C/BE2# IDSAA0 AB20
7 8 PCI_REQ4# N5
4.7K
RA0402_8 9,11,17 PCI_INTA# PCI_INTA#
R5
F5
C/BE1#
C/BE0#
INTA#
PCI IDECSA1#
IDECSA0#
AC21
AB21
add pull down or up according to SIS FAE suggest.
PCI_INTB# F4
PCI_INTC# INTB# S42/Delete parallel DVD net,LJ080911
F3 INTC# IDA0 AE19
PCI_INTD# G1 AD18
INTD# IDA1
IDA2 AC17
PCI_FRAME#
The DG recommends the value is 4.7Kohm PCI_IRDY#
N1
N2
FRAME# IDA3 AF18
AB16
PCI_TRDY# IRDY# IDA4
M5 TRDY# IDA5 AE17
IDE
C PCI_STOP# N3 AD16 C
STOP# IDA6 R756 10K
IDA7 AF16
T59 PCI_SERR# P2 AE16
ns PCI_PAR SERR# IDA8
P4 PAR IDA9 AF17
ICTP PCI_DEVSEL# N4 AC16
PCI_LOCK# DEVSEL# IDA10
P1 PLOCK# IDA11 AD17
IDA12 AE18
CLK_ICHPCI V2 AB17
6 CLK_ICHPCI PCICLK IDA13
SB_PCI_RST# D5 AF19
R432 33 R0402 PCIRST# IDA14
11,17 NB_RST# IDA15 AC18
+V3.3S +V3.3AL
6 SB_ZCLK AC26 ZCLK
11 ZSTB_DP0 V22 ZSTB0
11 ZSTB_DN0 V23 ZSTB0# R694 R695
+V1.8S 11 ZSTB_DP1 V25 ns 10K R693 0 0
ZSTB1 ns ns
11 ZSTB_DN1 V26 ZSTB1#
ICTP T58 ns R696 ns 0 SB_CE# U24
SPI_CS0N AE21
R200 56.2,1% SZCMP_N 11 ZUREQ AA23 AF21 1 8 SB_VDD
R0402 ZUREQ SPI_CS1N CE# VDD
11 ZDREQ AA24 ZDREQ
ns AD22 R697 ns 0 SB_SI 5 3 SB_WP# R698 ns 4.7K
R201 56.2,1% SZCMP_P ICTP T57 SPI_DO R699 ns 0 SB_SO SI WP#
AE22 2
R0402
MuTIOL SPI_DI SO
7 SB_HOLD# R700 ns 4.7K
VSS
SZCMP_N R701 ns 0 SB_SCK HOLD#
AB24 ZCMP_N SPI_CLK AF22 6 SCK S42C reseved SPI ROM,LJ080911
SZCMP_P AB25 W25X80A
4
ZCMP_P
SPI
ns SOIC8_50_208
AF23 SPI_STRAP +V3.3S
+V1.8S SPI_HARDWARE_TRAP
16mA@+V1.8S/SO
MutioL power
FB421 2 FB0603 AVDD_SZ4X R171
AVDD_SZ4X AA22 4.7K BIOS ROM cycle select
B
C389 120ohm/100MHz,500mA AVSS_SZ4X AVDD_Z4X B
AB23 AVSS_Z4X R0402
10uF/6.3V,X5R C367 C368 ns 1. LPC Interface: Internal Pull-down
C0805 SZVREF AB26 SPI_STRAP
0.1uF/10V,X7R 0.01uF/16V,X7R ZVREF 2. SPI Interface: External Pull-up
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16
AVSS_SZ4X R170
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
4.7K
R0402
968 B0
Y22
Y25
Y23
W21
Y26
W22
W24
W25
U21
U24
U22
T22
U25
T23
T25
T26
AA26
BGA570 S42C/ install R170,LJ080911
+V1.8S
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
R202
150,1%
11 ZAD[0:16]
SZVREF
R203 C169 1.Place the circuit of noise filters as close to 671DX as possible.
49.9,1%
0.1uF/10V,X7R 2.Every trace depicted in the figures should be kept as short as possible.
3.The recommend trace width in the figures is at least 15 mil whenever possibly.
+V3.3AL
C219
A A
0.1UF/25V,Y5V
C0402
5
VCC 1 SB_PCI_RST#
26,27,28,30 PCI_RST# 4 TOPSTAR TECHNOLOGY
2 <OrgAddr1>
GND
U6 R217 Page Name <Title>
3
R248 SN74AHC1G08DBV 10K

100K SOT23_5 R0402 Size Project Name Rev
R0402 C S42C A
to others or used for any purpose other than that for which it was obtained with the
expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
A20M# will go active based on either setting
U5B
the bit in Port 46h register,or based on the EC_RTC 35
+V1.8AL 12,22,23,39,40
A20GATE input being active. AVSS_GMACCMP18 C8 AVSS_GMACCMP
+V3.3AL 6,18,20,22,23,26,27,28,29,30,32,33,34,35,36,37,38,39,40,42,44
D9 AVDD_GMACCMP
AVDD_GMACCMP18 +V3.3S 6,7,11,14,15,17,18,19,20,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
7 H_INIT# AC23 INIT# +VLAN 22,23,39
Vih_gtl>=VTT/2+0.3V=0.825V MOSC25MHO
Vil_gtl<=VTT/2-0.3V=0.225V 7 H_A20M# AE26
AD23
A20M# OSC25MHO B8
A8 MOSC25MHI
GMAC/MAC +V1.8S 9,10,11,12,17,20,22,23,38,39,44
Vol_gtl<0.4V 7 H_SMI# SMI# OSC25MHI +V1.05S 6,7,8,9,12,22,23,32,39,40,41,42
AC22
7 H_INTR
7 H_NMI
7 H_IGNNE#
AE25
AE24
INTR
NMI
IGNNE#
CPU_S GTXCLK
EXTCLK
A12
F14
T71
T68
ICTP
ICTP
ns
ns +V1.8AL
8mA@+V1.8AL/SO
8mA@+V1.8AL/S3
+V5S 17,18,19,24,25,29,30,31,32,37,38,39,41,42,44
7 H_FERR# AF24 FERR#

AF25 B11 MOSC25MHO
7 H_STPCLK# STPCLK# TXCLK TX_CLK 27
7 H_CPUSLP# AD24 CPUSLP#
For p4 used, works as AGP_BUSY# C12 FB471 2 FB0603 AVDD_GMACCMP MOSC25MHI R452
TXEN TXEN 27 TXD[0:3] 27
R172 0 R0402 AE23 C11 T72 ICTP ns 10M
11 AGP_BUSY# BMBUSY# TXER 120ohm/100MHz,500mA ns R451
AC24 D12 TXD0_968 R234 22 R0402 TXD0 C451 C450 R0402 0
D
7,42 VR_PROCHOT#
7,32 PM_THRMTRIP# AD25
PROCHOT#
THERMTRIP# APIC TXD0
TXD1 A13
B13
TXD1_968
TXD2_968
R232
R233
22
22
R0402
R0402
TXD1
TXD2 0.1uF/10V,X7R 0.01uF/16V,X7R Y6
D
28,30 LPC_AD0 Y5 LAD0

GMAC TXD2
TXD3 C13 TXD3_968
RGMCMP_N
R231 22 R0402 TXD3
AVSS_GMACCMP
1
25MHz
2
28,30 LPC_AD1 AA4 LAD1 RGMCMP_N A14

AB2 B14 RGMCMP_P XS2
28,30 LPC_AD2 LAD2 RGMCMP_P
AB3 C14 RGMVREF C458 C457
+V3.3S R167 4.7K
R0402
LDRQ#
28,30
28,30 LPC_FRAME#
LPC_AD3
LDRQ#
AB1
LAD3
LFRAME#
LPC RGMVREF
RXCLK A11
VerB:Del T74
RXCLK 27
22pF/50V,NPO
C0402
22pF/50V,NPO
C0402
AB4 LDRQ#
30 LPC_SIRQ AA5 SIRQ RXDV C10 RXDV 27
RXER E12 RXER 27
S42C/Delete R148. LJ080916 VerB:将27pF电容改为22pF，提高晶振振幅
A10 071019
RXD0 RXD0 27
RXD1 C9
B9
RXD1 27 EEPROM
RXD2 RXD2 27
A9 +V3.3AL
RXD3 RXD3 27
+VLAN
OSC32KHO E2 E10 U16
OSC32KHO COL COL 27
During the period of PWROK being low, PCIRST# will all OSC32KHI E1 E11 GPIO24 1 8
OSC32KHI CRS CRS 27 CS VCC
be asserted until after PWROK goes high for 12 ms. E14 GPIO21 2 7
MDC MDC 27 SK NC1
E13 GPIO22 3 6
MDIO MDIO 27 DI NC2
BAT_PWRGD F1 GPIO23 4 5 R227
BATOK GPIO21 +V3.3AL DO GND 150,1%
6,30,40 SB_PWRGD E4 PWROK GPIO21 D8
ICH_EC_RTC F8 GPIO22 AT93C46 R0402
Place close to SB pin D1 GPIO22 GPIO23 R429 4.7K R0402
E8 Port1 is for Minicard SO8_50_150
C426 0.01uF/16V,X7R
ICH_EC_RTC C436 D1
<1mA@S0/S3/S5/G3 RTCVDD
0.1uF/10V,X7R
RTC GPIO23
GPIO24 A7 GPIO24
Port0 is for Newcard 610609346001 RGMVREF
D2 RTCVSS PRX0+ M26 SB_PCIE_RX_DP0 26 S42C/ change from ATMEL to SEIKO.LJ080923
C0402 C0402 M25
PRX0- SB_PCIE_RX_DN0 26
C429 0.1uF/10V,X7R N24
PTX0+ SB_PCIE_TX_DP0 26
C0402 N23 C211 R228
PTX0- SB_PCIE_TX_DN0 26
E5 K26 150,1%
31 AZALIA_SDATAIN0 HDA_SDIN0 PRX1+ SB_PCIE_RX_DP1 28 注意信号名
C4 K25 0.01uF/16V,X7R R0402
32 AZALIA_SDATAIN1 HDA_SDIN1 PRX1- SB_PCIE_RX_DN1 28
PTX1+ L24 SB_PCIE_TX_DP1 28
Place close to SiS968 PTX1- L23 SB_PCIE_TX_DN1 28 PCI-Express
R187 33 R0402 HDA_SDOUT Y3
C
31 AZALIA_CODEC_SDOUT
32 AZALIA_MDC_SDOUT
MDC R683
R177
33
33
R0402
R0402 HDA_SYNC Y2
HDA_SDOUT
PCI NC11 F26
F25
T66
T67
ICTP
ICTP
ns
ns
+V1.8S
30mA@+V1.8S/SO C
31 AZALIA_CODEC_SYNC
32 AZALIA_MDC_SYNC
31 AZALIA_CODEC_RST#
MDC
MDC
R684
R222
R685
33
33
33
R0402
R0402
R0402
HDA_RST# B3
HDA_SYNC
HDA_RESET#
HD Audio Express
NC10
NC9
NC8
G24
G23
T65
T64
T62
ICTP
ICTP
ICTP
ns
ns
ns FB221 AVDD_PEXTRX
32 AZALIA_MDC_RST# NC7 H26 2 FB0603
H25 T63 ICTP ns
C153 5.6pF/50V,NPO NC6 T60 ICTP ns 120ohm/100MHz,500mA +VLAN
NC5 J24
ns J23 T61 ICTP ns C176 C177
R180 33 HDA_BIT_CLK NC4
31 AZALIA_CODEC_BITCLK Y1 HDA_BIT_CLK
R686 33 MDC 0.1uF/10V,X7R 0.01uF/16V,X7R RGMCMP_N R229 56 R0402
32 AZALIA_MDC_BITCLK
MDC P26
PCLK100P CLK_PCIE_ICH 6
C631 22pF/50V,NPO P25 AVSS_PEXTRX RGMCMP_P R230 56 R0402
PCLK100N CLK_PCIE_ICH# 6
R25 AVDD_PEXTRX
AVDD_PEXTRX AVSS_PEXTRX
6 CLK14_REF1 AA2 OSCI AVSS_PEXTRX R26
R215 0 SENTEST F2 P22 PEX_RSET0 R416 499,1% R0402
ENTEST RSET0 PEX_RSET1 R420 124,1% R0402 +V1.8S
Test Mode Enable Pin 31 AC_SPKR AA1 P21
SPK RSET1 sis demo board use 20pf
30 PM_PWRBTN# E6 PWRBTN#
R255 0 ns PME# A6 R21 MINICARD_PRST1# EXP_CPPE#_D R409 10K
30 EC_RUNTIME_SCI#
PSON# E7
PME#
PSON# ACPI/Others PCIEPRSNT1
PCIEPRSNT0 R23 EXP_CPPE#_D 2 3 EXP_CPPE# 26
MINICARD_PRST1# R412
R0402
0
R0402
11,30,40 ALW_PWROK C3 AUXOK
RSMRST# R220 0 ns Vilmax=ZVREF-0.1=0.25*1.8-0.1=0.35V 2N7002E-T1
27,29,30 POWERLED A5 ACPILED Q36
For PCIE Mini Card
1
与EC控制S3 power LED共layout +V3.3AL
SLP_S4# C2 Demo: +V3.3S When use on board PCIE device or PCIE mini card at port
EC_RUNTIME_SCI#默认用GPIO9来实现，预留使用PME# pin SLP_S3# GPIO10/SLP_S5# GPIO0 used for PCIEX16 present detected!
C7 GPIO15/SLP_S3# 0/1, because they didn't define the PRSNT# pin, so the
U5 DPSLP# PCIEPRSNT 0/1 should be tie to GND.
GPIO0/STPCPU# DPSLP# 22
PM_BATLOW# D6 AB5 R501 0 R0402
30 PM_BATLOW# GPIO7/GPWAK# GPIO1/LDRQ1#/PCIE_HOTPLUG Presence Detect Input of Hot-Plug Pins for PCI Express Port
STOP_PCI# SB_RING A4 V5 PM_THRM# H_RCIN# R430 10K
R250 0 GPIO9 C6 GPIO8/RING GPIO2/THERM# VerB:去掉测试点,连到EXP_CPPE#_EC R0402
30 EC_RUNTIME_SCI# GPIO9/HDA_SDIN2 GPIO3/EXTSMI# W4 SB_EXTSMI# 30
W3 PM_CLKRUN# 071025 GPIO9 R251 4.7K
R447 GPIO4/CLKRUN# PANEL_ID1
F6 GPIO11/STP_PCI#/AGPSTOP# OD停PCI的clock W2 Note:VR
0
ns
AGP_STOP#
6 STOP_PCI#
22 STOP_CPU_DPSLP#
22,42 SB_DPRSLPVR
R445 0 SB_AGPSTOP#_S3SW#
D4
D3
GPIO12/CPUSTP#/DPSLP# OD停止cpu的clock
GPIO13/DPRSLPVR OD降低Vcore的电平
GPIO GPIO5/PREQ5#
GPIO6/PGNT5# W1 PANEL_ID0
PANEL_ID1 18
PANEL_ID0 18 Pin45/DPRSLPVR: 3.3V level
PM_BATLOW#
PME#
R247
R252
4.7K
4.7K
11 AGP_STOP# B5 GPIO14/AGPSTOP#/S3AUXSW# OD停AGP的clock SMB_CLK +V1.8S
Vih=2.3V;Vil=1.0V
GPIO19 Y4
22 SB_DPRSTP#
SB_DPRSTP# B7 OD降低Vcore的电平 W5 SMB_DATA Pin46/DPRSTP#:1.0V Level SB_AGPSTOP#_S3SW#R246 4.7K
GPIO16/DPRSTP# GPIO20 MINICARD_PRST1# ns 10K R499
B 30 H_A20GATE# D7 GPIO17/GA20# R0402
ViL=0.3V;Vih=0.7V DPSLP# R426ns 4.7K B
30 H_RCIN# B4 GPIO18/KBDRST#
SB_RING S42C/Delete PM_THRM# and
STOP_PCI# R422 4.7K
SIS968 Pin B5 used for S3AUXSW#: 968 B0 PM_CLKRUN# offpage connecotr. LJ080916 MINICARD_PRST1#
2 3 ns
Open drain :3.3/5V AUX PCIE_MINICARD_CLKREQ# 6,28
R221 BGA570 PM_SLP_S4# R239 4.7K ns
220K SIS671 Pin is 1.8V AUX IO logic
R0402 2N7002E-T1 PM_SLP_S3# R265 4.7K ns
ns/GPO_BIOS VerB:present连到MiniPCIE的CLKREQ Q42
1
071025 SB_DPRSTP# R260 4.7K
ALW_PWROK +V3.3S STOP_CPU_DPSLP# R199 1K R0402

Pull high +V3.3AL +V3.3S
C438
0.1uF/10V,X7R VerB:ns R239 and R265 SB_EXTSMI# R403 4.7K
C0402 SMB_DATA R391 0 071011
SMB_DATA_S 6,14,15,26,28 VerC:del ns
R194 ns 4.7K PANEL_ID1 R195 ns 4.7K
SMB_CLK R394 0 R197 ns 4.7K PANEL_ID0 R198 ns 4.7K

SMB_CLK_S 6,14,15,26,28
+V3.3AL R257 10K ns PSON#
R0402 SMB_DATA R392 1K
R0402
SMB_CLK R395 1K
R0402
PM_THRM# R399 4.7K
PM_CLKRUN# R181 4.7K
R261 0 SLP_S3# STOP_CPU_DPSLP# R681ns 1K R0402

26,30,40 PM_SLP_S3# sis demo board RC use 10K R 10uf cap and one 1N4148
EC_RTC D11 ICH_EC_RTC
BAT54C tICH_EC_RTC-BATPWRGD>1ms DPSLP# R682 4.7K
26,30,41 PM_SLP_S4#
R224 0 SLP_S4#
RTC 1
SOT23 VerC:Del D22 for no layout space
R419
SB_DPRSLPVR R446 4.7K
3 20K
C224
1
S42C/Delete control circuit.LJ0912 2 10uF/6.3V,X5R C406 R0402

A C0805 1uF/10V,X7R CLEAR_COMS C196 This signal will be at input mode after the Clear RTC operation, A
C0603 JOPEN_2 18pF/50V,NPO an external pulled down resistor is required for this signal.
SPONGE_RTC1 RESISTOR_1 C0402 High= Deeper Sleep Voltage
RTCBAT GLUE ns Low= Normal Voltage(Default)
2
ns/ASSY_with Cable R253 R216
1
BAT_PWRGD 10M TOPSTAR TECHNOLOGY
RTC_BAT1 1K Y4 R0402
3
R0402
w/o Cable <OrgAddr1>
1
+ ns/ASSY_with Cable 32.768KHz

RTCBAT1 BATT1 C395 CLEAR_COMS1 Assy xd3_2X6 Page Name <Title>
2
1
- CONN2_R C399 10uF/6.3V,X5R JOPEN_2 OSC32KHI

3
RTCBAT with Cable CNS2_R 1uF/10V,X7R C0805 RESISTOR_1 C197 Size

+
Project Name Rev

ns/ASSY_with Cable BAT_B RTC_BAT2 C0603 ns ns 18pF/50V,NPO OSC32KHO C
1 1 S42C
3
Co-lay C0402 A
2 2 +
根据机构
4
Date: Sunday, September 28, 2008 Sheet 21 of 51

-
- PROPERTY NOTE: this document contains information confidential and property to

4
定Cable尺寸 RTCBAT-SOCKET-TopyangRTCBAT w/o Cable

ASSY_RTC w/o Cable ASSY_RTC w/o Cable
hexainf@hotmail.com expressed written consent of TOPSTAR

5 4 3 2 1
+V1.8AL 12,21,23,39,40
+V3.3AL 6,18,20,21,23,26,27,28,29,30,32,33,34,35,36,37,38,39,40,42,44
+V3.3S 6,7,11,14,15,17,18,19,20,21,23,24,26,27,28,29,31,32,37,38,40,41,42,44
+VLAN 21,23,39
+V1.8S 9,10,11,12,17,20,21,23,38,39,44
U5C
+V1.05S 6,7,8,9,12,23,32,39,40,41,42
29 USB_PP0 D26 UV0+ OSC12MHI A22 CLK_USB_12M 6

29 USB_PN0 D25 UV0-
28 MINICARD_USBP1 E24 B22 T73 ICTPns
UV1+ OSC12MHO VerC:Change R421 value from 127 to
28 MINICARD_USBN1 E23 UV1-
26 NEWCARD_USBP2 A20 F20 USB_REF R421 130,1% R0402 130 Ohm,LJ080327 7mA@+V1.8AL/SO
UV2+ USBREF +V1.8AL
26 NEWCARD_USBN2 B20
18 CAM_USB_PP3 C19
UV2-
B26 AVDD_USBPLL18 1mA@+V1.8AL/S3
UV3+ AVDD_USBPLL18 AVSS_USBPLL18
18 CAM_USB_PN3 D19 UV3- AVSS_USBPLL18 B25
32 BT_USBP4 A18 AVDD_USBPLL18 FB0603 2 1FB23
UV4+ USBCMPAVDD18
32 BT_USBN4 B18 E21
D 25 CR6232_USBP5
25 CR6232_USBN5
27 USB_PP6
C17
D17
A16
UV4-
UV5+
UV5-
UV6+
USB AVDD_USBCMP18
AVSS_USBCMP18
AVDD_USBCMP33
E20
D21
USBCMPAVSS18
UVDD33
C206
0.01uF/16V,X7R
C205120ohm/100MHz,500mA
0.1uF/10V,X7R
D
27 USB_PN6 B16 C21 USBCMPAVSS33 AVSS_USBPLL18

+V3.3AL 27 UV6- AVSS_USBCMP33
USB_PP7 C15 UV7+
27 USB_PN7 D15 9mA@+V1.8AL/SO +V1.8AL
UV7-
A23
1mA@+V1.8AL/S3
29 USB_OC0# OC0#
R423 10K R0402 F21 add SATA DVD,LJ080911,需要确认DVD接0，Hdd接1会不会有什么问题。 USBCMPAVDD18 FB0603 2 1FB46
OC1#
A24 OC2#
B24 S42C/ Add SATA ODD.LJ080920 120ohm/100MHz,500mA
OC3# C445
C23 OC4# C441
C24 AC13 C634 C0402 0.01uF/25V,X7R
OC5# STX0+ SATA_TXP0 24 0.01uF/16V,X7R
A25 AD13 C635 C0402 0.01uF/25V,X7R 0.1uF/10V,X7R
OC6# STX0- SATA_TXN0 24
FB44 27 USB_OC67# B23 OC7# SRX0+ AF12 SATA_RXP0 24
AE12 SATA_RXN0 24 USBCMPAVSS18
USB_UVDD18 SRX0- C250 C0402 3300pF/50V,X7R
+V1.8AL 1 2 E16 UVDD18_01 STX1+ AC6 SATA_TXP1 24
E18 AD6 C249 C0402 3300pF/50V,X7R UVDD33
UVDD18_02 STX1- SATA_TXN1 24
100ohm@100MHz,3A C434 C428 F15 UVDD18_03 SRX1+ AF5 SATA_RXP1 24
FB0805 F16 UVDD18_04 SRX1- AE5 SATA_RXN1 24
0.1uF/10V,X7R 0.01uF/16V,X7R J19 UVDD33
UVDD18_05
284mA@+V1.8AL/SO MAX H18 UVDD18_06
H17 let XIN link to GND,and Xout NC depend on SIS FAE Hermes. C442
15mA@+V1.8AL/SO IDLE UVDD18_07 C443
H16 UVDD18_08
5mA@+V1.8AL/S3 UVDD33 H15 AE8 25M_IN R182 0 R0402 0.01uF/16V,X7R 0.1uF/10V,X7R
UVDD18_09 XIN 25M_OUT T49 ICTPns
J15 UVDD18_10 XOUT AF8
+V3.3S USBCMPAVSS33
FB45
8mA@+V3.3S/SO
+V3.3AL 1 2 F22 UVDD33_01
F19 R186
UVDD33_02
100ohm@100MHz,3A C444 C437 F17 UVDD33_03
10K
R0402 ns
连接到HDD LED上。
FB0805 0.1uF/10V,X7R 0.01uF/16V,X7R
HDACT AA3 IDE_LED# 29
AC1 ISW1
ISWITCHOPEN1 ISW0 这个是什么意思？
ISWITCHOPEN0 AD1
SATA Port0 Interlock Switch Input
C Layout note: C
Avoid noise possible,Gnd and signal to other distance larger than 8H +V3.3S +V3.3S
SATA
REXT R168 R169
1K 1K
C158 AVDD_SATARX AF14 R0402 R0402
R176 AVSS_SATARX AVDD_SATARX ns ns
AF15 AVSS_SATARX
12.1K,1% 22pF/50V,NPO D22 T69 ICTP ns ISW0 ISW1
R0603 12.1Kohm R0402 C0402 AVDD_SATAPLL33 IPB_OUT0 T70 ICTP ns
AC9 AVDD_SATAPLL33_01 IPB_OUT1 C22
P/N:120106061212 AD9 +VLAN
AVDD_SATAPLL33_02 HW_STRAP0 R184 R185
TRAP0 E22
AVSS_SATAPLL33 AC8 1K 1K
AVSS_SATAPLL33_01 R425
AD8 AVSS_SATAPLL33_02 R0402 R0402
10K
REXT AF7 D10 ATRAP R0402
REXT ATRAP ns
AE15 E9
Vih>2.0V !!
6 CLK_ICH_SATA CLK100P PCIEWAKE EC_PCIE_WAKE# 30
6 CLK_ICH_SATA# AD15 CLK100N
968 B0
BGA570
+V1.8S
6mA@+V1.8S/SO
FB191 2 FB0603 AVDD_SATARX
120ohm/100MHz,500mA
C160 C157
0.1uF/10V,X7R 0.01uF/16V,X7R
S42C/ NS Q40 and R481.LJ080922
AVSS_SATARX
B
C state Control +V1.05S
R480
H_DPSLP# 7 B
+V3.3AL 1K
3
+V3.3S 41mA@+V3.3S/SO R0402 Q40 R481
1 MMBT2222A 20K
SOT23 R0402
R482
5
FB181 2 FB0603 AVDD_SATAPLL33 ns ns
2
33 delay1 1 VCC
120ohm/100MHz,500mA R0402 4 DPSLP#
DPSLP#
该信号由以前的AL电改为S电.lj080201 21
C156 C159 STOP_CPU_DPSLP# R483 499,1% delay2 2
21 STOP_CPU_DPSLP# R0402 GND SOT23_5 +V3.3S
0.1uF/10V,X7R 0.01uF/16V,X7R 该信号由以前的S电改为AL电.lj080201 SN74AHC1G08DBV
510-->499 C478 C477
3
U20 +V3.3AL
AVSS_SATAPLL33 100pF/50V,NPO 100pF/50V,NPO R485
C0402 C0402 1K
ns R484 R0402
1K CPUSTP# 6
3
R0402
PQ55
2N7002
1 SOT23
+V3.3AL MuTIOL operation frequency select
3
3
R486
2
1. 133Mhz: Internal Pull-down PQ56 PQ57 20K
2N7002 2N7002
R427 2. 66Mhz: External Pull-up delay1 1 SOT23 delay2 1 SOT23
R0402
1K Note: MuTIOL operation frequency must accord
R0402
2
2
ns with the default ZCLK frequency of clock
HW_STRAP0
generator. R487 1K R0402 ns +V1.05S
1
Q41
MMBT2222A ns EVT
A
+VLAN
21 SB_DPRSTP#
SB_DPRSTP# SOT23 2 3
调试 A
H_DPRSTP# 7,42
3
R434
1K PQ58
R0402
ns 672:set "0"
STRAP PIN R488 R0402 1
2N7002
SOT23
TOPSTAR TECHNOLOGY
ATRAP
21,42 SB_DPRSLPVR
33 ns R489 Delay1 to Delay2 is 1PCI clock/33ns <OrgAddr1>
20K Page Name <Title>
2
R433
1K
C479
100pF/50V,NPO
R0402
ns Delay time require test to adjust the timing Size
C
Project Name Rev
S42C A
R0402 C0402
ns Date: Saturday, September 27, 2008 Sheet 22 of 51
S42C/ NS PQ58 and R489.LJ080922 TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
5 4 3 2 1
5 4 3 2 1
+V1.8S 9,10,11,12,17,20,21,22,38,39,44
+V1.8AL 12,21,22,39,40
+V3.3AL 6,18,20,21,22,26,27,28,29,30,32,33,34,35,36,37,38,39,40,42,44
+V1.05S 6,7,8,9,12,22,32,39,40,41,42
+VLAN 21,22,39
+V1.05S +V3.3S 6,7,11,14,15,17,18,19,20,21,22,24,26,27,28,29,31,32,37,38,40,41,42,44
22mA@SO
CPU VTT power
C358 C359 C360

1uF/10V,X7R
C0603 0.1uF/10V,X7R 0.1uF/10V,X7R
AB22
AA21
W23
M10
M11
M12
M13
M14
M15
U23
R22
R15
R16
U16
U17
N10
V21
Y21
P15
K10
K11
K12
T21
T15
T17
T16
L10
L11
L12
L14
L15
L16
D D
U5D
+V1.8S
N11
VTT01
VTT02
VSSZ01
VSSZ02
VSSZ03
VSSZ04
VSSZ05
VSSZ06
VSSZ07
VSSZ08
VSSZ09
VSSZ10
VSSZ11
VSSZ12
VSSZ13
VSSZ14
VSS01
VSS02
VSS03
VSS04
VSS05
VSS06
VSS07
VSS08
VSS09
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
U26 VDDZ01 VSS18 N12
C393 C403 W26 N13
10uF/6.3V,X5R 10uF/6.3V,X5R C378 C391 C400 C394 VDDZ02 VSS19
AA25 VDDZ03 VSS20 N14
C0805 C0805 1uF/10V,X7R 1uF/10V,X7R R24 P10
C0603 C0603 0.1uF/10V,X7R 0.1uF/10V,X7R VDDZ04 VSS21
T24 VDDZ05 VSS22 P11
V24 VDDZ06 VSS23 P12
Y24 VDDZ07 VSS24 P13
P18 VDDZ08 VSS25 P14
W18 VDDZ09 VSS26 R10
SB Core power U18 VDDZ10 VSS27 R11
V18 VDDZ11 VSS28 R12
+V1.8S
590mA@SO Put under 968 solder side V19 VDDZ12 VSS29 R13
W19 VDDZ13 VSS30 R14
N18 VDDZ14 VSS31 T10
VSS32 T11
R18 IVDD01 VSS33 T12
C380 R17 T13
C388 C376 C398 C387 C397 C409 IVDD02 VSS34
V17 IVDD03 VSS35 T14
0.1uF/10V,X7R V13 U10
0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R IVDD04 VSS36
V12 IVDD05 VSS37 U11
K9 IVDD08 VSS40 U14
M9 IVDD09 VSS41 U15
N9 IVDD10 VSS42 D13
P9 IVDD11 VSS43 D11
R9 IVDD12 VSS44 B12
T9 IVDD13 VSS45 B10
+V3.3S U9 AC25
IVDD14 VSS46
J14 IVDD15 VSS47 AD26
29mA@SO T18 IVDD16
C401 C385 D14
10uF/6.3V,X5R 10uF/6.3V,X5R C373 C390 C392 C396 USBVSS01
V16 PVDD01 USBVSS02 E15
C0805 C0805 1uF/10V,X7R 1uF/10V,X7R V15 A15
C0603 C0603 0.1uF/10V,X7R 0.1uF/10V,X7R PVDD02 USBVSS03
C V14 B15 C
4mA@SO
T8
N8
L9
PVDD03
PVDD04
PVDD05
PVDD06
Power/Ground USBVSS04
USBVSS05
USBVSS06
USBVSS07
C16
D16
A17
W17 OVDD01 USBVSS08 B17
C371 C369 C370 W16 E17
C407 C386 C414 C372 OVDD02 USBVSS09
W15 OVDD03 USBVSS10 C18
0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R W14 D18
0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R OVDD04 USBVSS11
W13 OVDD05 USBVSS12 A19
W12 OVDD06 USBVSS13 B19
K8 OVDD07 USBVSS14 E19
L8 OVDD08 USBVSS15 C20
Put under 968 solder side M8 OVDD09 USBVSS16 D20
P8 OVDD10 USBVSS17 A21
R8 OVDD11 USBVSS18 B21
+V1.8AL 19mA@+1.8VAL/SO U8 D23
OVDD12 USBVSS19
V8 D24
14mA@+1.8VAL/S3 OVDD13 USBVSS20
C25
USBVSS21
J18 IVDD_AUX01 USBVSS22 C26
J17 IVDD_AUX02 USBVSS23 K13
C410 C417 C416 C413 J16 K14
1uF/10V,X7R IVDD_AUX03 USBVSS24
J10 IVDD_AUX04 USBVSS25 K15
+V3.3AL C0603 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R J8 K16
IVDD_AUX05 USBVSS26
4mA@+3.3VAL/SO J9 IVDD_AUX06 USBVSS27 K17
L13
3mA@+3.3VAL/S3 H19
USBVSS28
L17
OVDD_AUX01 USBVSS29
H9 OVDD_AUX02
+VLAN C421 C424 C427 C415 H8 AB6
1uF/10V,X7R OVDD_AUX03 AVSS_SATA01
F7 OVDD_AUX04 AVSS_SATA02 AB7
Glan controller AUX power C0603 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R J11 AB12
OVDD_AUX05 AVSS_SATA03
8mA@+2.5V/SO J12 OVDD_AUX06 AVSS_SATA04 AB13
AB14
1mA@+2.5V/S3 H10
AVSS_SATA05
AB15
GMIIVDD_AUX01 AVSS_SATA06
H11 GMIIVDD_AUX02 AVSS_SATA07 AC2
+V1.8S C431 C447 C435 C446 C433 C432 H12 AC3
1uF/10V,X7R 1uF/10V,X7R GMIIVDD_AUX03 AVSS_SATA08
H13 GMIIVDD_AUX04 AVSS_SATA09 AC4
C0603 C0603 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R J13 AC5
GMIIVDD_AUX05 AVSS_SATA10
B AVSS_SATA11 AC7 B
R415 K18 AVDDPEX01 AVSS_SATA12 AC12
153mA@SO L18 AVDDPEX02 AVSS_SATA13 AC14
V_PCIE_1.8V L19 AC15
AVDDPEX03 AVSS_SATA14
M18 AVDDPEX04 AVSS_SATA15 AD2
SB PEX related 0 power C408 M19 AD3
10uF/6.3V,X5R C419 C418 AVDDPEX05 AVSS_SATA16
C412 C405 N19 AVDDPEX06 AVSS_SATA17 AD4
R0805 C0805 H21 AD5
0.1uF/10V,X7R 0.1uF/10V,X7R 0.01uF/16V,X7R 0.01uF/16V,X7R AVDDPEX07 AVSS_SATA18
J21 AVDDPEX08 AVSS_SATA19 AD7
K21 AVDDPEX09 AVSS_SATA20 AD12
L21 AVDDPEX10 AVSS_SATA21 AD14
+V1.8S M21 AE1
AVDDPEX11 AVSS_SATA22
N21 AVDDPEX12 AVSS_SATA23 AE2
Put under 968 solder side M22 AVDDPEX13 AVSS_SATA24 AE3
Sata controller power H22 AVDDPEX14 AVSS_SATA25 AE4
R398 AVSS_SATA26 AE6
190mA@SO AVSS_SATA27 AE7
+V_SATA_1.8V AB8 AE9
AVDD_SATA01 AVSS_SATA28
AB9 AVDD_SATA02 AVSS_SATA29 AE11
C362 AB10 AE13
0 10uF/6.3V,X5R C366 C357 AVDD_SATA03 AVSS_SATA30
C361 C363 AB11 AVDD_SATA04 AVSS_SATA31 AE14
R0805 C0805 AC10 AF2
0.1uF/10V,X7R 0.1uF/10V,X7R 0.01uF/16V,X7R 0.01uF/16V,X7R AVDD_SATA05 AVSS_SATA32
AC11 AVDD_SATA06 AVSS_SATA33 AF3
AD10 AVDD_SATA07 AVSS_SATA34 AF4
AD11 AVDD_SATA08
AE10 AVDD_SATA09 AVSS_SATA35 AF6
AF10 AVDD_SATA10 AVSS_SATA36 AF9
AVSSPEX01
AVSSPEX02
AVSSPEX03
AVSSPEX04
AVSSPEX05
AVSSPEX06
AVSSPEX07
AVSSPEX08
AVSSPEX09
AVSSPEX10
AVSSPEX11
AVSSPEX12
AVSSPEX13
AVSSPEX14
AVSSPEX15
AVSSPEX16
AVSSPEX17
AVSSPEX18
AVSSPEX19
AVSSPEX20
AVSSPEX21
AVSSPEX22
AVSSPEX23
AVSSPEX24
AVSSPEX25
AVSSPEX26
AVSSPEX27
AVSSPEX28
AVSSPEX29
AVSSPEX30
AVSSPEX31
AVSSPEX32
V9 AVDD_SATA11 AVSS_SATA37 AF11

W8 AVDD_SATA12 AVSS_SATA38 AF13
W9 AVDD_SATA13
W10 AVDD_SATA14
W11 AVDD_SATA15
P24
P23
N22
N26
N25
M24
M23
L22
K22
J22
G22
L26
L25
K24
K23
J26
J25
H24
H23
G26
G25
F24
F23
E26
E25
P16
M17
N17
P17
M16
N16
N15
968 B0
BGA570
A A
TOPSTAR TECHNOLOGY
<OrgAddr1>
Page Name <Title>
C S42C A
hexainf@hotmail.com expressed written consent of TOPSTAR

5 4 3 2 1
+V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,26,27,28,29,31,32,37,38,40,41,42,44
+V5S 17,18,19,25,29,30,31,32,37,38,39,41,42,44
+V3.3S
D D
FB33 0 R0805 V3.3_SATA
ns Close to connector as possible SATA_HDD1
the same distance to connector
ns ns ns 2
22 SATA_TXP1 TX
CT5 C246 C245 3 1
22 SATA_TXN1 TX# GND0
4.7uF/10V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V C248 C0402 3300pF/50V,X7R 5 4 SATAHDD_B1 SATAHDD_B2
V3.3_SATA 22 SATA_RXN1 RX# GND1
C0805 C0402 C0402 C247 C0402 3300pF/50V,X7R 6 7
22 SATA_RXP1 RX GND2
+V5S 8 11
VerB:Del R305 0 ohm for cost down VCC3_0 GND3
Average 1A,Peak 1.5A +V5S 071024
9
10
VCC3_1 GND4 12
13
VCC3_2 GND5
R304 0 14 17 Screw 2*8mm Screw 2*8mm
CT4 C244 C243 R0402 VCC5_0 GND6 ASSY ASSY
15 VCC5_1
4.7uF/10V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 16 VCC5_2 GND7 19
C0805 C0402 C0402 18 REEVE
GND23 23
20 VCC12_0 GND24 24
21 VCC12_1 GND25 25
22 VCC12_2 GND26 26
SATA_HDD CONN
SATA_S_50B
C C
+V5S
S42C,添加SATA DVD的Connector,LJ080911
FB24 0 R0805 Average 1A,Peak 1.5A V_DVD
SATA_CON1
CT3 C203 C204
B 4.7uF/10V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V S1 B
C0805 C0402 C0402 GND1 SATAODD_B1 SATAODD_B2
22 SATA_TXP0 S2 A+
22 SATA_TXN0 S3 A- GND6 14
S4 GND2
C636 0.01uF/25V,X7R S5
22 SATA_RXN0 B-
C637 0.01uF/25V,X7R S6
22 SATA_RXP0 B+
S7 GND3
V_DVD Screw 2*8mm Screw 2*8mm
P1 ASSY ASSY
DP
P2 +5V_1
P3 +5V_2
P4 MD GND7 15
P5 GND4
P6 GND5
SATA_ODD
SATA_S_50D
TOPSTAR TECHNOLOGY
A Echo liu A
Page Name IDE/SATA CONN(SATA&DVD)
B S42C
A
5 4 3 2 1
5 4 3 2 1
6 CLK_CR_12M
R0402
R442 0
ns
CR_XTALIN
SD/MMC/MS 3IN1 +V5AL
+V5S
18,27,29,32,35,36,38,39,40
17,18,19,24,29,30,31,32,37,38,39,41,42,44
C503
0.1uF/10V,X7R
CR_XTALIN VREF
CR_XTALO CR
D SD_D2 D
VerB:去掉一个270K增加振幅 SD_D3
071019 VCC33V
Y5 12MHz MS_D1 MS_INS
1 2 MS_CLK SD_D1
MS_BS SD_D0
xs2 CR
C460 C461
48
47
46
45
44
43
42
41
40
39
38
37
27pF/50V,NPO 27pF/50V,NPO U21
C0402 C0402 FB48
SMALE/MSBS
MSCLK
MSD1
SMREZ/MMCD4
SMD3/SDD3
SMD2/SDD2
GND_4
VCC33_3
SMD1/SDD1
SMD0/SDD0
VREF
MSINSZ
CR CR VCC33V 1 2 VCC33VA
CR
600ohm@100MHz,1.5A
Depend on Crystal CL and MS_D0 1 C504 C505FB0805 C506

SMD4/MSD0 MS_D2 CR 0.1uF/10V,X7R
2 36
PCB Cp capacitance./20pf SD_CLK 3
SMD5/MMCD6 SMD6/MSD2
35 MS_D3 0.1uF/10V,X7R 4.7UF/6.3V,X5R CR
SDCLK SMD7/MSD3 SD_CMD CR C0805
4 SMWEZ/MMCD5 SMCLE/SDCMD 34
GND 5 VCC33V
Confirm 12MHz volatge level 6
GND_1 VCC33_2 33
32 SD_CD#
VCC33V SMCDZ SDCDZ
7 VCC33_1 GND_3 31
CARD_3V3 8 30 SD_WP#
+VBUS VCC18 CRDVCC SDWPD
C 9 REG18_O SMWPZ 29 C
LEDZ/TESTEN/UATX
VCC33V 10 28 VCC18
+VBUS REG33_O VCC18
11 27
SMWPDZ/TEST0
+V5AL GND 12 VBUS SMBSYZ/MMCD7
GND_2 SDA/TEST3/UARX 26
CR 25
SCL/TESTINTR
VCC33A_1
VCC33A_2
R541 0 R0805 +VBUS C633 VCC18
GNDA_1
GNDA_2
+V5S 10uF/6.3V,X5R C507
SMCEZ
REXT
C0805 0.1uF/10V,X7R
DM
R542ns 0 R0805 +VBUS ns CR
XO
DP
XI
C508 C509
CR
13
14
15
16
17
18
19
20
21
22
23
24
UB6232 0.1uF/10V,X7R 4.7UF/6.3V,X5R
CR CR C0805
没有必要使用Always电。VerD:add 10uF capacitor.LJ080415 VerB:Card Reader采用UB6232新方案
6232_REXT
VCC33VA 071019
CR6232_USBP5 22
CR_XTALIN
CR6232_USBN5 22
CR_XTALO
R492
VCC33VA 12.1K,1%
R0402
CR
B B
3IN1 CONN.
J8A S42C/ Delete Co-layout connector.LJ080922
SD_D2 2
SD_D3 DAT2_SD CARD_3V3
3 DAT3_SD VDD_SD 6
SD_CMD 4 CMD_SD C476
SD_CLK 7 SD+MMC C440 1uF/10V,X7R
CLK_SD 0.1uF/10V,X7RC0603
SD_D0 9 8 CR CR
SD_D1 DAT0_SD VSS_SD2
10 DAT1_SD
SD_CD# 1 5
SD_WP# CD_SD# VSS_SD1
11 WP_SD#
3IN1 CR
TOPSTAR TECHNOLOGY
J8B
A MS_CLK CARD_3V3 Echo liu A
14 CLK_MS VCC_MS 13
Page Name Card Reader(UB6232 USB)
MS_D3 15
MS_INS 16
DAT3_MS MS C510 Size Project Name Rev
MS_D2 INS_MS 1uF/10V,X7R B S42C
17 DTA2_MS VSS_MS1 12 A
MS_D0 18 21 C454 C0603
MS_D1 DTA0_MS VSS_MS2 0.1uF/10V,X7R Date: Saturday, September 27, 2008 Sheet 25 of 51
19 DTA1_MS GND1 22
MS_BS 20 23 CR CR PROPERTY NOTE: this document contains information confidential and property to
BS_MS GND2
3IN1 CR to others or used for any purpose other than that for which it was obtained without
5 4 3 2 1
hexainf@hotmail.com
GRATIS - FOR FREE
5 4 3 2 1
+V3.3S +V1.5S QFNS20 package can support

Ti TPS2231 O2:OZ27C10LN +V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,27,28,29,31,32,37,38,40,41,42,44
Richo:R5538 QFN package. +V1.5S 8,11,28,32,39,40,41
+V3.3AL 6,18,20,21,22,23,27,28,29,30,32,33,34,35,36,37,38,39,40,42,44
C423 U15
C422 TPS2231
0.1uF/10V,X7R QFNS20_0D5_0D85G
0.1uF/10V,X7R 12 3 EXP_3.3V
1.5Vin1 3.3Vout1 NewCard_Shield1
14 1.5Vin2 3.3Vout2 5
D R5538: NEWCARD_SHIELD NCPVC1 D
2 15 EXP_AUX_3.3V PERST#: System RST# NEWCARD_B1 ASSY NewCard PVC
+V3.3AL 3.3Vin1 3.3Vauxout ASSY
4 3.3Vin2
11 EXP_1.5V AND/与RCLKEN
1.5Vout1 CPPE#:Internal pull
17 3.3Vauxin 1.5Vout2 13
C439 R435 0 1 8 EXP_RST#

to AUXIN(INPUT) PVC
21,30,40 PM_SLP_S3# STBY# PERST# 968 side for
0.1uF/10V,X7R PM_SLP_S4# 20 10 EXP_CPPE# PE_PRSNT#: Screw 2*5mm
21,30,41 PM_SLP_S4# SHDN# CPPE# ASSY
Vih>ZVREF+0.1V=0.55V
SYS_RST# 6 9 CP_USB# Vil<ZVREF-0.1V=0.35V
SYSRST# CPUSB#
16 NC GND2 G1
RCLKEN 18 G2 +V3.3AL +V3.3S
RCLKEN GND3
19 OC# GND1 7
611602231001
S42C/ change from Richon to ENE.LJ080923

R497 R417 R428
R418 0 SYS_RST# 100K 100K 100K
20,27,28,30 PCI_RST#
C C
EXP_CPPE#
S42C/ Delete Co-layout Newcard powerswitch circuit.LJ080922 CP_USB#

+V3.3S
NEWCARD_CLKREQ#
VerB:Add ESD protect
1
D26 R477 0 ns
NEWCARD1 BAT54SPT
NEW_CARD2 Q37
Sis require TX AC capcitors closing to SLOT 2N7002E-T1-E3
SOT23
3
C448 0.1UF/10V,X7R 25 16 NEW_CARD_CLKREQ# 2 3
21 SB_PCIE_TX_DP0 PETp0 CLKREQ# NEWCARD_CLKREQ# 6
C449 0.1UF/10V,X7R 24
21 SB_PCIE_TX_DN0 PETn0
RESV1 6
21 SB_PCIE_RX_DP0 22
1
PERp0 EXP_3.3V RCLKEN
B
RESV2 5 B
21 SB_PCIE_RX_DN0 21 PERn0
15 C420
+3.3VS_2 C430 10uF/6.3V,X5R
6 CLK_PCIE_NEWCARD 19 REFCLK+
14 0.1UF/10V,X7R C0805
+3.3VS_1
6 CLK_PCIE_NEWCARD# 18 REFCLK- ns
21 EXP_CPPE# 17 CPPE# GND0 26
EXP_AUX_3.3V
VerC:Add 0ohm for SMB and EXP_RST# 13
PCIE_WAKE# of New card PERST# C640
+3.3VAUX 12
R516 0 11 C425 10uF/6.3V,X5R
9,28,30 PCIE_WAKE# WAKE# 0.1UF/10V,X7R C0805
R494 0 8 ns
6,14,15,21,28 SMB_DATA_S SMB_DATA
GND1 23
R505 0 7 EXP_1.5V
6,14,15,21,28 SMB_CLK_S SMB_CLK
TOPSTAR TECHNOLOGY
R406 0 R0603 CP_USB# 4 10
CHK5 CPUSB# +1.5V_1 Echo liu
+1.5V_2 9
22 NEWCARD_USBP2 2 1 3 USB_D+ Page Name Express Card Socket
100uF/10V,TAN
A 3 4 20 C404 C136 A
22 NEWCARD_USBN2 GND2
2 0.1UF/10V,X7R + Size Project Name Rev
USB_D-
1
90ohm@100MHz,0.5A D20 D21 1 C402 A4 S42C

L4_0805 GND3 10uF/6.3V,X5RCT7343_28 A
27 GND4
R402 0 ns ns G1 C0805 ns Date: Saturday, September 27, 2008 Sheet 26 of 51
R0603 G1
ns 28 PROPERTY NOTE: this document contains information confidential and property to
2
EGA1-0603-V05 EGA1-0603-V05 GND5

G2 G2 TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
ESDPAD_R0603 ESDPAD_R0603 to others or used for any purpose other than that for which it was obtained without
PCI-EXP the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
+V3.3S
+V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,28,29,31,32,37,38,40,41,42,44
+V3.3AL
+V3.3AL 6,18,20,21,22,23,26,28,29,30,32,33,34,35,36,37,38,39,40,42,44
+V5AL
+V5AL 18,25,29,32,35,36,38,39,40
21 TX_CLK Impedence of RGMII is 50ohm
21 RXDV
DVDD33 DVDD33
D D
MDI0+
R294 SPEED R285 4.7K R0402
MDI0-
1.5K,1%
R0402 DUPLEX R286 4.7K R0402
U8
AVDD33 FB29 DVDD33 R15 R17 ANE R287 4.7K R0402
21 MDC MDC 25 32 PWFBOUT 100ohm@100MHz,3A 49.9,1% 49.9,1%
MDIO MDC PWFBOUT AVDD33 R0402 R0402 LDPS R283 4.7K
21 MDIO 26 MDIO AVDD33 36 1 2 R0402
21 TXD0 TXD0 6
TXD1 TXD0 C239 FB0805 SNIB R281 4.7K
21 TXD1 5 TXD1 R0402
21 TXD2 TXD2 4 29 0.1uF/10V,X7R
TXD3 TXD2 AGND_1 C0402 C18
21 TXD3 3 TXD3 AGND_2 35
21 TXEN TXEN 2 0.1uF/25V,Y5V
TX_CLK R18 22 R0402 TX_CLK_82017 TXEN C0402 ISOLATE R282 4.7K
TXC R0402
RXDV 22
RXD0 R301 22 R0402 RXD0_8201 21 RXDV
21 RXD[0:3] RXD0 NC 27
RXD1 R300 22 R0402 RXD1_8201 20 RPTR R284 4.7K
RXD2 R299 22 R0402 RXD2_8202 19 RXD1
RXD2
RTL8201CL R0402
RXD3 R298 22 R0402 RXD3_8201 18 GND

RXCLK R297 22 R0402 RX_CLK_8201 16 RXD3 MDI1-
21 RXCLK
COL 1
RXC TPRX- 30
31 MDI1+
Only be used when
21 COL COL TPRX+
21 CRS
CRS 23 CRS 8201CL is stuffed
RXER 24
21 RXER RXER/FXEN
Y3 XTAL1 46 33 MDI0- Hardwire Configuration network:
25MHz,25ppm,20pF XTAL2 X1 TPTX- MDI0+
47 X2 TPTX+ 34
XS2
2 1 LED0/PHYAD0 9 1. This configuration shows
LED1/PHYAD1 10 LED0/PHYAD0 RSET R0402 2K,1% R293
LED1/PHYAD1 RTSET 28 Enable: Auto negotiation, Full duplex, 100Mbps,
C LED2/PHYAD2 12 43 ISOLATE Link Down Power Saving, MII interface C
LED3/PHYAD3 13 LED2/PHYAD2 ISOLATE RPTR RTL8201CL:2K ,1% RTL8211BL:2.49K,1%
C235 C232 LED3/PHYAD3 RPTR 40 Disable: Isolate, Repeater mode
LED4/PHYAD4 15 39 SPEED
22pF/50V,NPO 22pF/50V,NPO LED4/PHYAD4 SPEED DUPLEX 2. These seven configuration pins could be connected
DUPLEX 38
C0402 C0402 PWFBIN 8 37 ANE to VDD or GND directly.
DVDD33 PWFBIN ANE LDPS
14 DVDD33_1 LDPS 41
DVDD33 48 44 SNIB
DVDD33_2 MII/SNIB/RTT3 PHYRSTB R13 0 R0402 ns +V5AL
RESETB 42 PCI_RST# 20,26,28,30
VerB:25M晶振振幅太小将 GND 11
电容由27pF改为22pF GND DGND_1 R12 4.7K R0402
17 DGND_2 DVDD33
071012 GND 45 DGND_3
2
C8
FB2
RTL8201CL-VD-LF 0.1uF/10V,X7R
QFPS48_0D5_1D6 C0402 100ohm@100MHz,3A
FB0805
1
Support LAN wake up +V5AL_IOUSB 1
1
2 2
+V3.3AL DVDD33 3
FB4 3
4 4
100ohm@100MHz,3A 1. You could simply connect RESETB to PCI 22 USB_PP6 5
+V3.3S FB0805 5
1 2 22 USB_PN6 6 6
Close to P14,P48 Reset. And just discard R30, R28, C20. 7 7
2. If Wake on Lan feature is needed, you have 8 8
1 2 DVDD33 9 9
FB7 to supply power from auxiliary power for all 22 USB_OC67#
C11 10 10
100ohm@100MHz,3A 1000pF/50V,X7R 11
FB0805 C6 C233 C242 C234 LAN-related circuit including RTL8201BL/CL/CP C0402 22 USB_PP7 12
11
25
ns 10uF/6.3V,X5R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 12 25
B C0805 C0402 C0402 C0402
and MAC. In this kind of application, discard 22 USB_PN7 13 13 26 26
B
14 14
R29 and retain other components for one MDI0+ 15 15
MDI0- 16
resetting upon power up. 17
16
MDI1+ 17
18 18
MDI1- 19 19
MP:change voltage from 10V to 6.3V.LJ0308 两份DEMO 不一样，千兆与百兆co-lay的线路使用4.7K DVDD33 20 20
百兆线路使用5.1K,FAE推荐使用4.7K 33,43 Isense_SYSP 21
22
21
21,29,30 POWERLED 22
LED0/PHYAD0 R20 4.7K R0402 23
28,30,35 PWR_SW_VCC2 23
R0402 4.7K R22 LED1/PHYAD1 R21 4.7K R0402 ns PWFBOUT FB111 2 PWFBOUT_L 24
4.7K R23 LED2/PHYAD2 FB0603 24
R0402
R0402 4.7K R295 LED3/PHYAD3 120ohm/100MHz,500mA
R0402 4.7K R296 LED4/PHYAD4
24pin 0.5mm bot FFC
COL R16 4.7K R0402 COL:
R302 4.7K R0402 CRS CL=0 for CL mode(Internal pull down-defalt) IOPOWERBRD1
R303 4.7K R0402 RXER BL=1 for BL mode
CRS:
1 for output if not in idle
输出到transformer 的TCT上拉上 0 for normal operation(Internal down--Default)
This schematic sets PHY address to 00001b.

close to PWFBOUT place C16 close You could set PHY address from 00001b to 11111b.
to PWFBIN.
120ohm/100MHz,500mA
PWFBOUT FB31 1 2 FB0603 PWFBIN R900 is reserved for ensuring 8201CL
A
C481 C240 A
10uF/6.3V,X5R10uF/6.3V,X5R C241 C15 latch to normal operation Mode.RTL8211BL:NS TOPSTAR TECHNOLOGY
C0805 C0805 0.1uF/10V,X7R 0.1uF/10V,X7R <OrgAddr1>
ns C0402 C0402 R908 is reserved for ensuring 8201CL Page Name RGMII LAN
GND GND GND latch to UTP Mode.RTL8211BL: NS
A3
R902(config9) is reserved for 8201CL/CP LED S42C A
Place C905, C1006, FB84 close to PWFBOUT and Mode Change to compatible with BL Date: Saturday, September 27, 2008 Sheet 27 of 51
place C1005 close to PWFBIN. PROPERTY NOTE: this document contains information confidential and property to
RTL8211BL:C83~C85(NC) L6(NC) TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
GRATIS - FOR FREE
5 4 3 2 1
H12 +V5S 17,18,19,24,25,29,30,31,32,37,38,39,41,42,44

+V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,29,31,32,37,38,40,41,42,44
+DATA1
+V1.5S 8,11,26,32,39,40,41
+V3.3AL 6,18,20,21,22,23,26,27,29,30,32,33,34,35,36,37,38,39,40,42,44
-DATA1
+VDC 18,33,35,36,37,38,41,42,44
1
D17 D16
ESDPAD_R0603 ESDPAD_R0603 +V3.3S +V3.3AL +V3.3AL +V1.5S
1
EGA1-0603-V05 EGA1-0603-V05
D Hole+Dowel 2*3mm D
2
ns ns MinipciE
R774 R775 VerD:Change footprint from TH_200_132_112 to TH_200_132_118 llh0418
VerB:ns D34 D36 0 0 TH_200_132_118
ns R0603
R0603 MinipciE
MPCIE1
MINIPCIE_DEBUG
与mini PCI不同，此处为低有效 +V3.3S
Keep USB2.0 Signal stub short
52
24
48
28
注意修改LED等处的电路
6
+3.3V0
+3.3V1
+3.3VAUX
+1.5V0
+1.5V1
+1.5V2
R348 0 R0603
MinipciE R109
+V3.3AL 10K
R349 0 R0603 MinipciE
MinipciE
PCIE_MINICARD_CLKREQ#
CHK4 ns R356
3 4 -DATA1 36 46 ns 10K
22 MINICARD_USBN1 USB_D- LED_WPAN# T107ICTP
2 1 +DATA1 38 44 ns
22 MINICARD_USBP1 USB_D+ LED_WLAN# Wireless_LED# 29
LED_WWAN# 42 T102ICTP
L4_0805 ns
C C
90ohm@100MHz,0.5A
PCIE mini Card

6 CLK_PCIE_MINICARD# 11 REFCLK- PERST# 22 PCI_RST# 20,26,27,30
13 1 R354 0 ns
6 CLK_PCIE_MINICARD REFCLK+ WAKE# PCIE_WAKE# 9,26,30
CLKREQ# 7 PCIE_MINICARD_CLKREQ# 6,21
Sis require TX AC capcitors closing to SLOT
21 SB_PCIE_TX_DN1 C182 0.1UF/10V,X7R MinipciE 31
C180 0.1UF/10V,X7R MinipciE PETN0
21 SB_PCIE_TX_DP1 33 PETP0 SMB_DATA 32 SMB_DATA_S 6,14,15,21,26
SMB_CLK 30 SMB_CLK_S 6,14,15,21,26
21 SB_PCIE_RX_DN1 23 PERN0
21 SB_PCIE_RX_DP1 25 PERP0
CHANNEL_CLK 5 CH_CLK 32
CHANNEL_DATA 3 CH_DATA 32
T115 ICTP ns 17 RESERVED0
19 RESERVED1
+V3.3AL T114 ICTP ns
RESERVED_DISABLE 20 HW_RATIO_OFF# 30
R776 MinipciE 0 37
R777 MinipciE 0 RESERVED_PCIE0 R351
39 RESERVED_PCIE1
41 16 ns 10K S42C/install R351.LJ080919
RESERVED_PCIE2 RESERVED_SIM0 T106ICTP
43 14 ns MinipciE
45 12 ns
47 10 ns
B 49 8 ns B
51 RESERVED_PCIE7 +V3.3AL
+V3.3AL A1 +V3.3AL REFRESH_EN# A15 Reflash_EN# 30

+V3.3S A2 +V3.3S
+VDC A17 +VDC PWR_SW_VCC A18 PWR_SW_VCC2 27,30,35
PWRSW# A19
20,26,27,30 PCI_RST# A3 PCIRST# DEBG_URXD A13 EC_DEBG_URXD 30

6 CLK_DEBUGPCI A9 PCICLK DEBG_UTXD A14 EC_DEBG_UTXD 30
21,30 LPC_FRAME# A12 LFRAME#
NC A20
21,30 LPC_AD0 A5 LAD0
21,30 LPC_AD1 A6 LAD1 GND14 A4
21,30 LPC_AD2 A8 LAD2 GND15 A7
A10 A11
GND10
GND11
GND12
GND13
21,30 LPC_AD3 LAD3 GND16

GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND17 A16
MinipciE PCIE ROBSON

9
15
21
27
29
35
4
18
26
34
40
50
53
54
+V1.5S
TOPSTAR TECHNOLOGY
+V3.3S +V3.3AL
A Echo liu A
Page Name MINI-PCI SLOT
C314 C313 C319 C318 C312S42C/ Change minipcie according to minipcie 1.2 spec.LJ080922
C0805 C315 C320 C316 C317 Size Project Name Rev
10UF/6.3V,X5R 0.1UF/25V,Y5V 10UF/6.3V,X5R 0.1UF/25V,Y5V B S42C
10UF/6.3V,X5R 0.1UF/25V,Y5V 0.1UF/25V,Y5V C0805 C0805 A
0.1UF/25V,Y5V 0.1UF/25V,Y5V MinipciE MinipciE MinipciE MinipciE Date: Saturday, September 27, 2008 Sheet 28 of 51
MinipciE MinipciE MinipciE MinipciE MinipciE PROPERTY NOTE: this document contains information confidential and property to
5 4 3 2 1
5 4 3 2 1
+V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,31,32,37,38,40,41,42,44
Singal USB PORT S1

+V5S
+V3.3AL
+V5AL
17,18,19,24,25,30,31,32,37,38,39,41,42,44
6,18,20,21,22,23,26,27,28,30,32,33,34,35,36,37,38,39,40,42,44
18,25,27,32,35,36,38,39,40
1 2 FUSE 1.1A +V5AL
FUSE1812
100uF/10V,TAN
330PF/50V,X7R
sis use 10K resistor
100uF/10V,TAN
C53 C44 CT1
D
+ + R65 300K R0402 D
USB_OC0# 22
C0402
CT7343_28 CT6032
ns R66
Cost down Vih_ttl>=2V
C52
560K Vil_ttl<=0.8V E1
1000pF/50V,X7R
1
R0402 EMI
Co-layout CT31-CT6032 ns ns
1
C0402 EMIPOINT
USB1
VCC1 1 GND_USB GND_USB
5 90ohm@100MHz,0.5A
HOLE0 -DATA7
6 HOLE1 -DATA1 2 4 3 USB_PN0 22
7 3 +DATA7 1 2 ns
HOLE2 +DATA1 USB_PP0 22
8 HOLE3
4 CHK3 L4_0805
GND
1
USB_8 D14 D15
USB1 ESDPAD_R0603 ESDPAD_R0603 R331 0 R0603 VerB:ns R329 R331 加上CHK3
EGA1-0603-V05 EGA1-0603-V05 071025
VerC: Add R331 and R329.LJ080327
2
C R329 0 R0603 C
GND_USB
GND_USB GND_USB
GND_USB
Keep USB2.0 Signal stub short
Quick button Conn

+V3.3AL
+V3.3AL +V5S QK_CON1

Touchpad Conn Conn 6Pin
CNS6_0D5_RA1
B B
C306 C307 6
6 LIDR#
8 8 5 5 LIDR# 18,30
0.1UF/25V,Y5V C0603 4 VOLUME+
4 VOLUME+ 30
1 C0402 1UF/10V,Y5V 7 3 VOLUME-
1 +V3.3S 7 3 VOLUME- 30
2 R346 0 R0603 ns R98 R336 C299 2
2 +V5S 2
3 R341 0 R0603 47K 47K 1
3 +V5AL 1
4 R0402 R0402 C0402
4 +V3.3AL
5 ns ns 0.1UF/25V,Y5V
5 Add pull res
21 21 6 6
7 7 NUMLED# 30
8 TPDAT
8 CAPLED# 30
9 +V3.3S
9 IDE_LED# 22
10 TPCLK
10
11 11 BT_ON_LED 32
12 12 WIRELESS_LED# 28
22 2213 13 S42C/ns R98 and R336.LJ080924 TOPSTAR TECHNOLOGY
14 14 POWERLED 21,27,30
15 C308 C305 Echo liu
15 CHG_LED 30
16 16 BTL_LED 30 Page Name
1UF/10V,Y5V C0402 TPM Module & USB PORT
A 17 17 A
18 C0603 0.1UF/25V,Y5V Size
18 TPDAT 30 Project Name Rev
19 19 TPCLK 30 A4 S42C
20 A
20
TOUCHPAD_CN1 PROPERTY NOTE: this document contains information confidential and property to
CNS20_0D5_RA1 TOPSTAR and shall not be reproduced or transferred to other documents or disclosed
20pin 0.5mm bot FFC Place close TP conn for EMI 0118
hexainf@hotmail.com
5 4 3 2 1
LPC_SIRQ T126ICTP ns
+V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
LPC_FRAME# T127ICTP ns
+V5S 17,18,19,24,25,29,31,32,37,38,39,41,42,44
LPC_AD0 T128ICTP ns
这几个测试点放到一起， +V3.3AL 6,18,20,21,22,23,26,27,28,29,32,33,34,35,36,37,38,39,40,42,44
EC_V3.3AL
+V3.3AL
R706
C641 10K FB61 FB0603EC_V3.3AL R707 R0805
4.7UF/10V,Y5V 0
C0805 EC_RESET# V18R 120ohm/100MHz,500mA
EC_V3.3AL
C642 C643 C644 C645
3
+V3.3AL Q59 C646 C647 C648 C649 C650 C651
1 MMBT3904-F 0.1UF/25V,Y5V 1uF/10V,X7R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 10UF/6.3V,X5R +V3.3AL
SOT23 C0603 C0805 0.1UF/25V,Y5V 1uF/10V,X7R 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
V18R
C0603
2
D R708 C652 D
10K
124
111
125
R709 0.01uF/16V,Y5V R710 R711 R712
67
96
33
22
9
10K U25 10K 10K 10K Fuction P.M2 P.M1 P.M0
ns ns ns
V18R
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
R713 0 A20GATE
21 H_A20GATE# EC Output Signal! PCB_Mark0 VerA 0 0 0
63 SYS_I_Sense PCB_Mark1 VerB
AD0/GPI38 SYS_I_Sense 43 0 0 1
ADC
64 R779 10K PCB_Mark2
R714 0 RCIN# A20GATE AD1/GPI39 R780 10K
21 H_RCIN# 1 GA20/GPIO00 AD2/GPI3A 65 Verc 0 1 0
RCIN# 2 66 R781 10K
MSIC
EC Output Signal! SCI南桥已经上拉 KBRST#/GPIO01 AD3/GPI3B R715 R716 R717
20
南桥已经10k上拉到+V3.3AL EC_RESET# 能够reset EC ALL21 EC_RUNTIME_SCI# EC_RESET# 37
SCI#/GPIO0E 10K 10K 10K
ECRST#
+V3.3AL 5V3.3VALW_PWROK D38 1 1N4148WS ns
6 CLK_591PCI 12 PCICLK PWM0/GPIO0F 21 BTL_BEEP 31
PWM
21 LPC_SIRQ 3 SERIRQ PWM1/GPIO10 23 POWERLED 21,27,29
R718 ns 4.7K EC_PLT_RST# 4 25 +V5S
21,28 LPC_FRAME# LFRAME# PWM2/GPIO11 SET_I 43
21,28 LPC_AD0 10 LAD0 PWM3/GPIO19 34 EC_LVDS_BKLTCTL 18
R719 4.7K CLKRUN# 8 Q60
21,28 LPC_AD1
LPC
LAD1 2N7002E-T1
21,28 LPC_AD2 7 LAD2
1
5 ns
21,28 LPC_AD3 LAD3
20,26,27,28 PCI_RST# R720 0 EC_PLT_RST# 13 28 SOT23
PCIRST#/GPIO05 FANFB0/GPIO14 FAN_BACK 32
FAN
CLKRUN# 38 29 ns
CLKRUN#/GPIO1D FANFB1/GPIO15 T139ICTP
KBCON1 26 EC_SB_PWRGD 3 2
FANPWM0/GPIO12 FAN1_V 32 SB_PWRGD 6,21,40
ACES 85201-2402 27 R721 1K
FANPWM1/GPIO13 IVT_I_ADJ 18
+V3.3AL
24 SCANOUT15 SCANIN7 62 R722 0
24 SCANOUT10 SCANIN6 KSI7/GPIO37
23 23 61 KSI6/GPIO36 C653
22 SCANOUT11 SCANIN5 60
22 SCANOUT14 RN22 4.7K SCANIN4 KSI5/GPIO35 1uF/10V,X7R
21 21 59 KSI4/GPIO34
20 SCANOUT13 1 2 SCANIN3 SCANIN3 58 C0603 +V5S
20 SCANOUT12 SCANIN2 SCANIN2 KSI3/GPIO33
19 19 3 4 57 KSI2/GPIO32 PSCLK1/GPIO4A/P80CLK 83 TPCLK 29
KB3310B
18 SCANOUT3 5 6 SCANIN1 SCANIN1 56 84 TPCLK/DATA NS了上拉。 Q61
18 KSI1/GPIO31 PSDAT1/GPIO4B/P80DAT TPDAT 29
17 SCANOUT6 7 8 SCANIN0 SCANIN0 55 85 EC_EXTSMI# 2N7002E-T1
17 KSI0/GPIO30/E51_TXD(ISP) PSCLK2/GPIO4C
1
16 SCANOUT8 ns 86 HW_RATIO_OFF#在connector处上拉到+V3.3AL ns
16 PSDAT2/GPIO4D HW_RATIO_OFF# 28
PS2
15 SCANOUT7 RA0402_8 82 87 EC_SB_PWRGD SOT23
15 SCANOUT4 内部已经默认上拉。 KSO17/GPIO49 PSCLK3/GPIO4E EC_NB_PWRGD
14 14 81 KSO16/GPIO48 PSDAT3/GPIO4F 88
13 SCANOUT2 RN23 4.7K SCANOUT15 54 EC_NB_PWRGD 3 2
13 KSO15/GPIO2F/E51_RXD(ISP) NB_PWRGD 11,40
12 SCANIN7 1 2 SCANIN4 SCANOUT14 53
12 KSO14/GPIO2E
KB
11 SCANOUT1 3 4 SCANIN5 SCANOUT13 52
11 SCANOUT5 SCANIN6 SCANOUT12 KSO13/GPIO2D R723 0
C 10 10 5 6 51 KSO12/GPIO2C C
9 SCANIN4 7 8 SCANIN7 SCANOUT11 50
9 SCANIN5 ns SCANOUT10 KSO11/GPIO2B +V3.3AL
8 8 49 KSO10/GPIO2A
7 SCANOUT0 RA0402_8 SCANOUT9 48
7 SCANIN2 SCANOUT8 KSO9/GPIO29
26 26 6 6 47 KSO8/GPIO28
SMBUS
25 5 SCANIN3 SCANOUT7 46 80 I2C_DATA
25 5 KSO7/GPIO27 SDA1/GPIO47 I2C_DATA 7
4 SCANOUT9 SCANOUT6 45 79 I2C_CLK I2C_CLK R724 4.7K
4 KSO6/GPIO26 SCL1//GPIO46 I2C_CLK 7
3 SCANIN1 SCANOUT5 44 78 I2C_DATA R725 4.7K
3 KSO5/GPIO25 SDA0/GPIO45 SM_BAT_SDA2 34
2 SCANIN0 SCANOUT4 43 77 SM_BAT_SDA2 R726 5.6K
2 KSO4/GPIO24 SCL0/GPIO44 SM_BAT_SCL2 34
1 SCANIN6 SCANOUT3 42 SM_BAT_SCL2 R727 5.6K
1 SCANOUT2 KSO3/GPIO23/TP_ISP PM_PWRBTN# R762 ns 5.6K
41 KSO2/GPIO22/TP_ANA_TEST
CNS24_1_R_UP SCANOUT1 40 AMP_SHDW R763 ns 5.6K
621102400002 SCANOUT0 KSO1/GPIO21/TP_PLL VOLUME- R764 ns 5.6K
39 KSO0/GPIO20/TP_TEST GPXIOA00/SDICS# 97 BTL_LED 29
98 VOLUME+ R765 ns 5.6K
GPXIOA01/SDICLK CHG_LED 29
GPXIOA02/SDIMOSI 99
GPXIOA
+V3.3AL R729 1K 6 100 R730 0
18,29 LIDR# GPIO04 GPXIOA03 PM_PWRBTN# 21
R731 ns 0 PCIE_WAKE#_EC
14 101
9,26,28 PCIE_WAKE# GPIO07/i_clk_8051 GPXIOA04 AMP_SHDW 31
R732 0 15 102 CHG_ON R728 ns 10K
22 EC_PCIE_WAKE# 33 AC_IN GPIO08/i_clk_peri GPXIOA05 AC_OFF 33
16 103 BAT_OV_REV R757 ns 10K
输出信号 34 BATT_IN# GPIO0A GPXIOA06 CHG_ON 43
R733 10K LIDR# 0 R734 17 104
11,21,40 ALW_PWROK GPIO0B/ESB_CLK GPXIOA07 BAT_OV_REV 34
PWRSW# R735 1K 18 105 PROCHOT#
R736 10K PCIE_WAKE#_EC GPIO0C/ESB_DAT_O/ESB_DAT_I GPXIOA08 HW_OFF_BKLT#
21,26,40 PM_SLP_S3# 19 GPIO0D GPXIOA09 106 HW_OFF_BKLT# 18
32 107 R737 0 5V3.3VALW_PWROK 35,40
21,26,41 PM_SLP_S4# GPIO18 GPXIOA10
R767 10K Reflash_EN# 36 108
29 NUMLED# GPIO1A/NUMLED# GPXIOA11
R773 0 ns 73 +V5S
GPIO
36,40 V1_8_PWROK GPIO40
T132 ns ALWAYS_ON R739 1K EC_IMVP_ON 74
42 IMVP_ON GPIO41
EC_IMVP_ON R738 ns 20K T133 ns MAIN_ON 32 ALT_ON 89
T134 ns V1_2S_ON GPIO50 ns +V3.3AL Q62
37 V1_2S_ON 127 GPIO59/TEST_CLKSPICLKI GPXIOD0/SDIMISO 109 T140ICTP
1
T135 ns V1_8_ON 110 ns 2N7002E-T1
GPXIOD1 T141ICTP
GPXIOD
T136 ns V0_9S_ON 68 112 PCB_Mark0 SOT23 EC Input Signal!
36 V0_9S_ON GPO3C GPXIOD2
T137 ns MAIN_PWROK 70 114 PCB_Mark1
35 ALWAYS_ON GPO3D GPXIOD3
T138 ns IMVP_PWRGD 71 115 PCB_Mark2 2 3 PROCHOT#
38 MAIN_ON GPO3E GPXIOD4 7 EC_PROCHOT#
72 116 R741
36 V1_8_ON GPO3F GPXIOD5 BT_PWRON 32
PM_SLP_S4# 117 0
GPXIOD6 CAM_PWRON 18
76 118 PCI_RST# 20,26,27,28 R0603 R740 0 ns
40 MAIN_PWROK GPI43 GPXIOD7
PM_SLP_S3# 75 CS# R778 4.7K ns
40,42 IMVP_PWRGD GPI42 U26
119 R742 0 SO 2 8 SVDD
MISO SO VDD
SPI
90 120 R743 0 SI 5
21 PM_BATLOW# E51CS#/GPIO52 MOSI SI
C654 C655 30 126 R744 0 SCK 6 3 SWP# R745 4.7K C656
28 EC_DEBG_UTXD E51TXD/GPIO16 SPICLK/GPIO58 SCK WP#
31 128 R746 0 CS# 1 1uF/10V,X7R +V5S
100pF/50V,NPO 100pF/50V,NPO 28 EC_DEBG_URXD E51RXD/GPIO17/E51CLK SPICS# CE#
29 VOLUME+ R782 1K 92 7 SHOLD# R748 4.7K C0603
R783 1K E51TMR0/GPIO54/WDT_LED# HOLD#
93 4
8051
29 VOLUME- E51INT0/GPIO55/SCROLED# VSS
B
29 CAPLED# 91 E51TMR1/GPIO53/CAPSLED#
B
1
95 121 W25X80A Q63
28 Reflash_EN# E51INT1/GPIO56 XCLK32K/GPIO57
CLK
122 32XCLKI SOIC8_50_208 LABEL1 2N7002E-T1
XCLKI 32XCLKO 南桥已经上拉。 SOT23
XCLKO 123 Topstar Soft
BIOS Ver: X.XX 2 3 EC_EXTSMI#
21 SB_EXTSMI#
AGND
ns
GND
GND
GND
GND
GND
EC Ver: X.XX
EC Output Signal!
+V3.3AL XXXX年XX月XX日
R747 ns 0
KB3310B EC/BIOS Label
69
113
94
35
24
11
740601900104
R769
10K
PWRSW# C657 15PF/50V,NPO

Q64
2N7002E-T1 32XCLKI
3
2
SOT23
C660 32.768KHz R749 32XCLKO
3
Y8 xd3_2X6 20M
1 R750 R0603 10 ppm R0603
27,28,35 PWR_SW_VCC2
1
0 Assy
1000pF/50V,X7R
2
R770 C659 15PF/50V,NPO R751 121K,1%

1M
A A
TOPSTAR TECHNOLOGY
Echo liu
Page Name KBC(KB3310B)
Custom S42C
A
5 4 3 2 1
5 4 3 2 1
600ohm/100MHZ changed to 300ohm/100MHZ +V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,32,37,38,40,41,42,44

+V5S 17,18,19,24,25,29,30,32,37,38,39,41,42,44
+V3.3S VCC5CDC +V5S
D27
FB17 1N4148WS
1 2300ohm@100MHz,1.5A MIC2_REF 1 2 VerC:change BAV99 to ESD diode 071226
FB0805 SOD323
D28
C155 C161 C354 C379 C381 C147 C139 1N4148WS
10UF/6.3V,X5R 10UF/6.3V,X5R 1 2
0.1UF/25V,Y5V 0.1UF/25V,Y5V C0805 0.1UF/25V,Y5V 0.1UF/25V,Y5V C0805 0.1UF/25V,Y5V SOD323 GND_AUD GND_AUD
C0402 C0402 C0402 C0402 C0402
INPUT:LINE-IN
Cross moat place OUTPUT:Surround L/R
1
GND_AUD U4 VerB: exchange with pin 39/41 to Headphone out R509 R508 D9 D10
25
38
1
9
4.7K 4.7K ESDPAD_R0603 ESDPAD_R0603
S42C/Delete CD_IN circuit. LJ080916 C512 4.7uF/10V,X5R R0402 R0402 EGA1-0603-V05 EGA1-0603-V05
Line in Jack
VDD1
VDD2
AVDD1
AVDD2
T56 C0805 MIC_IN1
2
D D
ICTP ns A_GPIO0 2 35 CT6 ns AMP_OUT_L ns ns
GPIO0 FRONT-OUT-L
+
T55 CT6032 100uF/10V,TAN MIC2_L R205 75 R0402 FB21
1 2300ohm@100MHz,1.5A 2 L
ICTP ns A_GPIO1 3 36 CT7 ns AMP_OUT_R FB0805
GPIO1 FRONT-OUT-R
+
CT6032 100uF/10V,TAN MIC2_R R193 75 R0402 FB20
1 2300ohm@100MHz,1.5A 3
37 C513 4.7uF/10V,X5R FB0805 4 R
LINE1-VREFO-R C0805
C148 C0402 MIC2_JD 5
0.1UF/25V,Y5V 0.1UF/25V,Y5V 1
27 C150 C0805 C0402
VREF GND_AUD
1
10UF/6.3V,X5R D8 R204 R192 C168 C154
11 28 VREFOUT R166 4.7K R0402 INT_MIC_L_R ESDPAD_R0603 C145 22k 22k AZALIAJACK
21 AZALIA_CODEC_RST# REST# MIC1-VREFO-L EGA1-0603-V05 R0402 R0402 100pF/50V,NPO 100pF/50V,NPO AUDIO5A
6 ns C0402 C0402
21 AZALIA_CODEC_BITCLK
2
BITCLK ns
LINE1-VREFO-L 29
21 AZALIA_CODEC_SYNC 10 SYNC
30 MIC2_REF VerB:Add C145 GND_AUDGND_AUD GND_AUD
GND_AUD GND_AUDGND_AUD GND_AUD
MIC2-VREFO 071025
21 AZALIA_CODEC_SDOUT 5 SDOUT
21 AZALIA_SDATAIN0
R175 22 R0402 8
LINE2-VREFO 31 used for enhancing VerC:change
Audio BAV99 to ESD diode 071227
SDIN R174 4.7K R0402 INT_MIC_L_R
MIC1-VREFO-R 32 quality and ESD ability.
R162 51K C146 1uF/10V,Y5V 12 33 R191 10K ns R0402 GND_AUD GND_AUD
30 BTL_BEEP
R0402 C0603 PC-BEEP DCVOL VCC5CDC Stereo Microphone Jack
JACK_DET_A JACK_DET_B
13 JD1 JD2 34 INPUT:STEREO MIC-IN
C151
1
21 AC_SPKR
R165 75K
R0402
C149 1uF/10V,Y5V
C0603 100pF/50V,NPO
14 LINE2-L CEN-OUT 43 OUTPUT:CENT/LFE D18
ESDPAD_R0603
D19
ESDPAD_R0603
C0402 15 44 EGA1-0603-V05 EGA1-0603-V05
LINE2-R LFE-OUT
VerB: exchange with pin 35/36 to internal Speaker
2
R163 R164 MIC2_L C141 4.7uF/10V,X5R C0805 16 ALC662 ns ns LINE_OUT1
MIC2-L SIDESURR-OUT-L 45
4.7K 4.7K
R0402 R0402 MIC2_R C140 4.7uF/10V,X5R C0805 17 46 AMP_OUT_L R153 75 R0402 FB15 1 2300ohm@100MHz,1.5A 2 L
MIC2-R SIDESURR-OUT-R FB0805
18 47 EAPD R493 0 R0402 SHUTDOWN# AMP_OUT_R R158 75 R0402 FB14 1 2300ohm@100MHz,1.5A 3
CD-L SPDIFI/EAPD ns FB0805 R
4
20 48 VerB:NC SPDIF HP_JD 5
ns R515 0 R0402 SHUTDOWN# CD-R SPDIFO 071024 1
VerB: change to 5.11K INT_MIC_L C346 1uF/10V,X7R C0603 21
MIC1-L
1
C 39 SURR_OUT_L D5 0.1UF/25V,Y5V C
JACK_DET_B R383 20K,1% R0402 MIC2_JD update internal MIC circuit C347 1uF/10V,X7R C0603 22 SURR-OUT-L ESDPAD_R0603 C135 R0402 R149 C138 AZALIAJACK
MIC1-R C131
40 R387 20K,1% R0402 EGA1-0603-V05 C0402 22k 22k AUDIO5A
JDREF GND_AUD 100pF/50V,NPO
JACK_DET_A R161 5.11K,1% R0402 HP_JD 23 ns R152 R0402 100pF/50V,NPO
2
LINE1-L SURR_OUT_R C0402 C0402
SURR-OUT-R 41
CD-GND
24
AGND1
AGND2
LINE1-R
GND1
GND2
GND_AUD VerB: Del Spdif
USE 4.7UF 0805 QFPS48_0D5_1D6 ALC662
4
7
19
26
42
VerB:Add C135
All of JD resistors should be 071025
VerB: ALC883 changed to ALC662
placed as close as possible to
the sense pin of codec.
VerB:add R593,and change C594 from 1UF to AMP_OUT_R AMP_OUT_L
GND_AUD GND_AUD
0.1UF,and change C613 from 0.47UF to 0.33UF
to mute high frequence speaker's popo GND_AUD
U14 Q14 Q15
3
TPA6017A2 2N7002DW 2N7002DW
sop20_0d65_4d4g SC70_6 SC70_6
SURR_OUT_R C0603 R405 0 17 18 +INTSPR AMP_SHDW 2 5 AMP_SHDW 2 5
C383 0.22uF/10V,X7R RIN- ROUT+
4
7 14 -INTSPR
C365 RIN+ ROUT-
0.22uF/10V,X7R R396 0 9 4 +INTSPL
GND_AUD LIN+ LOUT+
C0603 VCC5CDC
C364 C0603 10 8 -INTSPL VCC5CDC
GND_AUD BYPASS LOUT-
0.22uF/10V,X7R
SURR_OUT_L C0603 R404 0 5 16
C384 0.22uF/10V,X7R LIN- VDD R408
12 NC PVDD1 6
15 C352 10K Tied at three points under the
SHUTDOWN# PVDD2 0.1UF/10V,X7R R0402
19 SHDWN# GND1 1
GND2 11 C0402 C137 4.7uF/10V,Y5V codec and near the codec
GAIN0 C353 C0805 SHUTDOWN#
2 GAIN0 GND3 13
20 0.1UF/10V,X7R
De-pop Solution
GND4
3
GAIN1 3 21 C0402
GAIN1 GND5 Q35
B 2N7002 B
R0402
VerB: change connection GND_AUD R385 1K 1
30 AMP_SHDW
to pin 39/41 from pin 35/36 R411
2
R384 100K
10K R0402
GAIN0 GAIN1 Av(inv) R0402
0 0 6dB
VCC5CDC VCC5CDC 0 1 10dB R472 0 R0603
1 0 15.6dB GND_AUD
R471 0 R0603
R410 R414 1 1 21.6dB
10K 10K
R0402 R0402 R469 0 R0603
ns ns
GAIN0
GAIN1 FB41 1 2FB0805
300ohm@100MHz,1.5A
R407 R413
10K 10K
R0402 R0402 GND_AUD C351 C0402 ns
0.1UF/25V,Y5V
GND_AUD GND_AUD
GND_AUD
onboard stereo
INTSPK1 INTSPK2 INT_MIC_L_R
microphone
W-B-2P-R W-B-2P-R
A CNS2_R CNS2_R A
300ohm@100MHz,1.5A
FB16
4
+INTSPL +INTSPR INT_MIC_L R479

FB0805 +
2 2 1 2 1
4
2 -INTSPL 2 -INTSPR
1 1 1 1 2
3
1K TOPSTAR TECHNOLOGY
1
R0402 D6 C144
3
ESDPAD_R0603 MIC1 Echo liu

EGA1-0603-V05 100pF/50V,NPO
Microphone Page Name
C0402 Azalia audio codec(ALC880)
ns BZ_D6027
2
GND_AUD GND_AUD ASSY Size Project Name Rev

C S42C A
GND_AUD TOPSTAR and shall not be reproduced or transferred to other documents or disclosed

5 4 3 2 1
+V1.05S 6,7,8,9,12,22,23,39,40,41,42
+V1.05S 6,7,8,9,12,22,23,39,40,41,42
FAN Controller Circuit +V3.3S
+V5S
+V3.3AL
6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,37,38,40,41,42,44
17,18,19,24,25,29,30,31,37,38,39,41,42,44
6,18,20,21,22,23,26,27,28,29,30,33,34,35,36,37,38,39,40,42,44
H15 +V1.5S 8,11,26,28,39,40,41
For Heatsink +V5AL 18,25,27,29,35,36,38,39,40
H14 H13
+V5S +V3.3S
Q17
BT Reserved for 0 ohm R besides FB
AO3415
FB27 0 R0603
1
R264 0 R0805 BT 2 3 Hole+Dowel 2*5
BT
D +V5AL D
R258 0 R0805 ns/BT TH_200_132_118 +V5S +V3.3S
1
C225 C221 Hole+Dowel 2*5 Hole+Dowel 2*5
R238 0 R0603 BT
1
1000pF/50V,X7R 0.1UF/10V,X7R R237 0 R0603 BT TH_200_132_118 TH_200_132_118 GND
R254 BT BT R502 R503
100K
BT 0 0 R273
1 1 GND GND R0603 ns R0603
2 CHK2 90ohm@100MHz,0.5A 10K
2 R0402
3 3 2 1 BT_USBN4 22
9 9 4 4 3 4 BT_USBP4 22
VerB:BT_PWRON信号改为低电平有效 BT_ON# R244 1K 10 5 L4_0805 ns/BT
071024 10 5 BT_ON_LED 29
BT 6 R240 0 ns/BT
6 CH_CLK 28 VerB:NUT 2*3改为2*5
R498 1K 7 R241 0 ns/BT/CCOM S42C／Fan直接反馈给EC做处理， R276
7 CH_DATA 28 071105 FAN_BACK 30
ns/BT 8 R242 0 ns/BT/CCOM 10K
8 CH_CLK 28 需要在S42QT上面验证，LJ080918 R0402
3
3
SOT23 ns
Q16 VerB：BT_PWRON改为低有效 BT_CN1 R243 0 BT_ON# R275 1K FAN_TACH_ON 1 Q21
2N7002E-T1-E3 071024 87213-0800 BT R0402 2N2222 R274
30 BT_PWRON
R245 1K 1 BT C220 此处为高有效注意修改LED等处的电路 C227 ns SOT23
2
BT CNS8_1_R_W2B for graphic enhance ns 0
BT 1uF/10V,Y5V 1000pF/50V,X7R R0402
2
ns/BT C0402
R771 VerB:change BT_ON_LED# control to 5pin, VerB:Footprint改为0402的 ns
100K Q6 071024
and exchange USB D+/- depend on billition
BCP69-16 Vfan
BT BT.and reserve C631 for BT_ON# timing. CPUFAN1
SOT223 4
+V3.3S 3 2 1 4
1 4
2 2
2
C226 C13 3 5
R19 D3 3 5
1
R236 ns/BT 10K CH_CLK 1K 39 VCC_358 R271 0.1UF/25V,Y5V 10uF/6.3V,X5R CONN3_V
1N4148WS
1
R0402 10 C0402 C0805 CNS3_V
R235 ns/BT 10K CH_DATA R0402 R266 SOD323 FAN_FB
1
+V1.5S +V3.3AL +V3.3S VCC_358 5.11K,1%
1
C230 R0402
2
R272 U7A
C 1K 0.1UF/25V,Y5V LM358 C
8
R688 R689 R0402 C0402 so8_50_150 +V3.3S Shut-Down
R687 0 0 3
2
+
0 MDC ns/MDC 1
1
MDC1 2 Throttling/
-
MDC_AC/AZ_MODEM ns/MDC R267 Un-throttling
CNS12_MDC1 R772
4
C632 C229 10K,1% 4.7K
1 2 0.1UF/25V,Y5V R0402
2
GND1 RSVD1 ns T124 C0402 0.1UF/25V,Y5V
21 AZALIA_MDC_SDOUT 3 Azalia_SDATA_O RSVD2 4
5 6 MDC C0402 R270 R268
GND2 3_3VDUAL High-5V
7 8 1 100K 2
21 AZALIA_MDC_SYNC Azalia_SYNC GND3 FAN1_V 30
R690 22 MDC 9 10
21 AZALIA_SDATAIN1 Azalia_SDATA_I GND4
11 12 R0402 200K Middle-4V
21 AZALIA_MDC_RST# Azalia_RST Azalia_BCLK AZALIA_MDC_BITCLK 21
C661 C662 R0402
GND10
GND5
GND6
GND7
GND8
GND9
HOLE
4.7uF/10V,Y5V 0.1uF/25V,Y5V Low-3V

VerD: Add Modem connector LJ080415
MDC HOLD1
FAN1_V=3.30V,Vfan=5V
13
14
15
16
17
18
19
Cu Boss for MDC 2*5mm

FAN1_V=2.65V,Vfan=4V 50 55 60 65 70 75 80 85 90 95 100
MDC FAN1_V=1.98V,Vfan=3V S42C/ add Fan PWM RC 滤波，LJ080922
VerD:Add boss for MDC llh0418
+V3.3S
R353
B B
10K
R0402 +V1.05S
SHDN_LOCK#
VerC:change R343 to 470 ohm from 10K R352
4.7K
3
R343 R0402
5 2 ns
7 OVT_SHUTDOWN#
Q28
C304 MMDT3904 SHDN_LOCK#
SHDN_LOCK#40
4
470 R345 1000pF/50V,X7R SC70_6

R0402 100K C0402
R0402
6
R342
7,21 PM_THRMTRIP# 5 2
3
Q27
Q29 ns MMDT3904
Here removed GPU OTP circuit/ns
4
1
470 R344 C300 ns SC70_6
2N7002E-T1 R0402 100K ns
1
30 ALT_ON R0402 0.1UF/25V,Y5V
Use for temperature alarm driver. ns C0402
2
R347
100K
OVP CIRCUIT Don't use thermtrip shuntdown funciton.LJ080408
A A
Shut Down
VIN
CPU
Throttling on TOPSTAR TECHNOLOGY

THRMTRIP# SHDN#
AND Echo liu
THERM_ALERT# CPU Temperature Page Name
Throttling Off MDC/FAN/OTP/OVP
VDC 0 85 90 95 100 Size Project Name Rev
Thermal (Degree) C S42C
sensor A
5 4 3 2 1
BATT+ 34,38,43
+VDC 18,28,35,36,37,38,41,42,44
AD+ 19,38
+V3.3AL 6,18,20,21,22,23,26,27,28,29,30,32,34,35,36,37,38,39,40,42,44
PR27 PR25
3.3K 15K
R0402 R0402
PR101 10
R0402
ALW_EN 35 080430VD:Co-lay.
PC29 PQ24
PD5
0.1uF/25V,X7R SBM54PT
AD+ C0603 SMB AO4419
4
1
SO8_50_150
G
PR102
6.6A 6.6A
D
PD13 SSM34PT SMA 5
4A 1 8 ns 1 4A 3
S
6 BATT+
2 7 2 7
3 6 0.025,1% 1 8
S 5 ns 1 R2512
PR13 D 1
PC19 100K G PD12 SSM34PT SMA PD14
0.01uF/25V,X7R R0402 PQ25 PC115 SSM34PT
4
C0402 AO4419 1 0.1uF/25V,Y5V SMA
PR23
51K
SO8_50_150
PD8
SBM54PT
6.6A C0402
R0402 SMB
PR12
51K 6.6A 1
2
8
7
6.6A
+VDC
PR24 R0402 3 6
51K S 5
R0402 D
1
G PC138
PQ26 + 100UF/25V
1
4
AO4419 CAP6D3X11A
27,43 Isense_SYSP
PR105 SO8_50_150 ns
2
510K
R0402
40,43 Isense_SYSN
PR104 PR28
510K 100K
R0402 R0402
PQ1
3
PQ2 2N7002
3
2N7002 3 SOT23 PQ4

SOT23 2N7002
1 SOT23
40 SHDN#
30 AC_OFF 1 1 BAT_OV# 34
2
2
PR26 PC30
51K 1000pF/50V,X7R
R0402 PC28 PR29 C0402
C0402 510K
1000pF/50V,X7R R0402
AD+ +V3.3AL
PR33
3
100K
R0402 PQ5
2N7002
1 SOT23
AC_IN 30
2
PR34
51K PR31
R0402 1K
PR30 R0402
PC31 20K
1000pF/50V,X7R R0402
C0402
TOPSTAR TECHNOLOGY
Echo liu
Page Name ADAPTER IN
A3 S42C
A
hexainf@hotmail.com
GRATIS - FOR FREE
BATT+ 33,38,43
AD+ 19,33,38
+V3.3AL 6,18,20,21,22,23,26,27,28,29,30,32,33,35,36,37,38,39,40,42,44
PFB2
100ohm@100MHz,3A
1 2 PF2
8A ns
FB0805 FUSE1206
PFB3 100ohm@100MHz,3A 1 2
1 2
PF1 BATCON1
FB0805 8A
6.6A PFB4
1 2
FUSE1206
1 2
6.6A 7 BATT+ BAT_B1 BAT_B2
BATT+
PC12 1000pF/50V,X7R 100ohm@100MHz,3A KEY
FB0805
SM_BAT_SDA2 PR10 100 SM_BAT_SDA 6 SDAT
30 SM_BAT_SDA2
R0402
SM_BAT_SCL2 100 SM_BAT_SCL 5 SCLK
30 SM_BAT_SCL2
PR9 R0402 Screw 2*11mm Screw 2*11mm
4 TEMP ASSY ASSY
VA：由EC读电池SMBUS数据， BAT_IN#
3
得到电池温度信息。
2 GND
S42C/删掉BAT_TEM circuit.LJ080919 1 GND
BATT_CONN
9
BATJ7_MC
+V3.3AL +V3.3AL
+V3.3AL
GND_BAT PZD1 PZD2

PR5 2 2
SM_BAT_SDA2 300K
R0402 3 SM_BAT_SDA 3 SM_BAT_SCL
SM_BAT_SCL2 PC8 PC9
0.1uF/25V,Y5V 1 0.1uF/25V,Y5V 1
C0402 C0402
PR6
PC1 PC7 BAT54SPT BAT54SPT
BATT_IN# 30
5.6pF/50V,NPO 5.6pF/50V,NPO SOT23 SOT23
C0402 C0402 R0402 1K
061225:change to 5.6pF for SI
30 BAT_OV_REV
33 BAT_OV#
PD15
1
1N4148WS
SOD323
PQ31
MMBT2907
SOT23 PR111
2
1K
1 R0402
3
PQ30 1
2N2222
SOT23
2
PR112 PC122
2K 0.1UF/25V,X7R
R0402 C0603
TOPSTAR TECHNOLOGY
Echo liu
Page Name BATTERY IN/OVP
A3 S42C
A
5 4 3 2 1
+V3.3AL 6,18,20,21,22,23,26,27,28,29,30,32,33,34,36,37,38,39,40,42,44
+VDC 18,28,33,36,37,38,41,42,44
AD+ 19,33,38
+V5AL
+V5AL 18,25,27,29,32,36,38,39,40
+V3.3AL
GND_51120
PR197 PC175
20K,1%
220pF/50V,X7R
1.输入电容要靠近MOSFET漏极 PR200 PC174
R0402 PC173 11.5K,1% 220pF/50V,X7R
D C0402 1000pF/50V,X7R 2.MOS管尽量靠近IC芯片 R0402 C0402 D
VFB1 C0402
3.芯片的Thermal GND用至少5个过孔连到信号地,用来散热 VFB2
V5FILT
V5FILT
PR194 0
V2_REF
GND_51120
R0402 +V5AL
GND_51120
+V3.3AL 4.信号地和电源地在输出电容的负极连到一起
PR196 PR199
VFB1
VFB2
4.99K,1% 4.99K,1%
R0402 R0402
+VDC
8
VO1
COMP1
VFB1
VREF2
VFB2
COMP2
VO2
GND
+VDC GND_51120 PR191 GND_51120
VDC1
TestP 2A 10K
R0402 32 9
PR192 100K R0402
1.5A
TPC60 ns SKIPSEL EN5
ns PR190 10
V2_REF 31 10 5V_LDO
TONSEL EN3 R0402
PC106 PC101 PC103 PC102 PC172 PC171 PC176 PC177
10uF/ 25V 4.7uF/25V,X7R 0.1uF/25V,X7R 1000pF/50V,X7R 5V3.3VALW_PWROK 30 11 5V3.3VALW_PWROK 1000pF/50V,X7R 0.1uF/25V,X7R 4.7uF/25V,X7R 10uF/ 25V
C1210 C1206 C0603 C0402 PGOOD1 PGOOD2 C0402 C0603 C1206 C1210
ns ns
EN_V5AL 29 PU9 12 EN_V3AL
EN1 EN2
C C
Co-lay Co-lay.
TPS51120RHB
8
7
6
5
PC170 28 13 PC169
VBST1 VBST2
1
V5AL1 QFNS32_0D5_1G 0.1uF/25V,X7R PQ51
D
TestP PQ23 0.1uF/25V,X7R C0603 D1 D1
ns AO4468 4 C0603 500mA 27 DRVH1 DRVH2 14 500mA 8 V3R3AL1
TPC60 PL9 SO8_50_150 TestP
G
G1
5.2uH/5.5A PR96 LL2 TPC60
S
S1
LS2_1040 10K 500mA 26 15 500mA PL10
4A ns
1
2
3
R0402 LL1 LL2 PR193 LL2 +V3.3AL

5 7 1 +V3.3AL
+V5AL +V5AL 1
10K 5.2uH/5.5A
5A PC180
500mA 25 DRVL1 DRVL2 16 R0402 6 LS2_1040 4A
PGND1
PGND2
VREG5
VREG3
V5FILT
2
2
1uF/10V,Y5V 500mA D2 PC181
CS1
CS2
VIN
C0603 1uF/10V,Y5V
G1
G2
G5
G4
G3
+ 3 +
1
1
8
7
6
5
ns C0603 PZ14
PZ15 共lay G2 S2 ns BZT52C3V6S-F/3.6
D
2
G1
G2
24
23
22
21
20
19
18
17
G5
G4
G3
2
BZT52C5V6S-F/5.6 PD26 SOD323
1
1
SOD323 PD27 SSM34PT 4
1N5819 SMA
1
SOD123 ns
4A AO4932
S
PC168 PQ22 SO8_50_150 PC167

1
2
3
220UF/6.3V,OSCON AO4468 GND_51120 GND_51120 220UF/6.3V,OSCON

CAP6_6x7_3 SO8_50_150 PC108 CAP6_6x7_3
B 5A 1uF/25V,Y5V
C0805
+VDC
+V3.3AL
B
5V_LDO
V5FILT
V5FILT PR186 15K PR187 V5FILT
R0402 15K PR189
过流保护 R0402 100K
PD10 R0402
1N4148WS 100mA
SOD323 100mA
EC_RTC 21
100mA 30,40 5V3.3VALW_PWROK
5V3.3VALW_PWROK
27,28,30 PWR_SW_VCC2 1 100mA
PR183 10 100mA
PD11 R0402 PC110
2 4.7UF/6.3V,X5R
30 ALWAYS_ON PR100 C0805
3 EN_V5AL EN_V3AL PC109 PC114
4.7uF/10V,X5R 4.7uF/10V,X5R
1 10 C0805 C0805
33 ALW_EN
R0402
PR99 PC111 TOPSTAR TECHNOLOGY
BAT54C 100K 1000pF/50V,X7R
A SOT23 R0402 C0402 Echo liu A
GND_51120
Page Name +V3.3AL/+V5AL
PR195 0
R0402 Size Project Name Rev
B S42C
A
GND_51120 GND_51120
GND_51120 PROPERTY NOTE: this document contains information confidential and property to
5 4 3 2 1
hexainf@hotmail.com
GRATIS - FOR FREE
+V5AL 18,25,27,29,32,35,38,39,40
+V3.3AL 6,18,20,21,22,23,26,27,28,29,30,32,33,34,35,37,38,39,40,42,44
+VDC 18,28,33,35,37,38,41,42,44
DDR2用电源 +V1.8 6,10,12,14,15,16,38,40,41,44
+V0.9S 16,41
+V1.8 2.5A 2A
+VDC
PC99
5
6
7
8
4.7uF/25V,X7R Co-lay.
D
PU7 C1206 PC146
PC154 PC157 TPS51116 PQ21 PC148 PC98 PC100 1000pF/50V,X7R
0.1UF/10V,X7R 4.7UF/6.3V,X5R SOP20_0D65_4D4G PC150 4 AO4468 0.1uF/25V,X7R 4.7uF/25V,X7R 10uF/ 25V C0402
G
C0402 C0805 0.1uF/25V,X7R SO8_50_150 C0603 C1206 C1210
S
C0603 PR405 ns
1 0
VBST 20
3
2
1
VLDOIN R0402
V1_8
9 19
500mA PR93 PL8 TestP
For debug purpose 10,14 SM_VREF VDDQSNS DRVH 10K PD7 2.2UH/14A PC145 PC164 TPC60
R0402 LS2_6530 220UF/6.3V,OSCON 220UF/6.3V,OSCON
SSM34PT ns
PJ4 RESISTOR_1 PC152 6 18
500mA SMA +V1.8 CAP6_6x7_3 CAP6_6x7_3
MODE LL 1 +V1.8
2 1 0.1uF/10V,X7R PQ54 ns
+V3.3AL
5
6
7
8
5
6
7
8
C0402 AO4468
8A
2
D
D
JOPEN ns DDR_GND 7 17 PR406 0 DRVL1 SO8_50_150
VTTREF DRVL R0402 PZ6
+ +
1
PR143 10K 4 DRVL14 BZT52C2V0S-F/2.0V
30 V0_9S_ON
D-CAP
G
R0402 PR142 10K R0402 SOD323
1
11 8
2
S3 COMP
S
PQ20
30 V1_8_ON
1
PR145 AO4468
3
2
1
3
2
1
200K For debug purpose 12 10 SO8_50_150
R0402 PR144 S5 VDDQSET PC149 1000pF/50V,X7R PC182 080426VD: PC155
+V3.3AL 2 1
PJ5 200K C0402 1uF/10V,Y5V 预留电容位置。C0402
DDR_GND RESISTOR_1 R0402 4 15 PR390 20K R0402 F_5VAL PR391 10 R0402 C0603 0.1uF/10V,X7R
JOPEN VTTSNS CS ns
2.5A ns
DDR_GND 2 14
+V0.9S VTT V5IN +V5AL
2.5A V0_9S1
TestP 3 13 R390 100K
VTTGND PGOOD +V3.3AL
ns + PC160 PC158 R0402 PC147
TPC60 CT3216 10uF/6.3V,X5R ns 4.7UF/6.3V,X5R F_5VAL
22uF/6.3V,TAN C0805 TGND C0805
5 GND PGND 16
ns
21
400KHz PC156
V1_8_PWROK 1uF/10V,X7R
V1_8_PWROK 30,40
C0603
PR148
DDR_GND
0
R0402
DDR_GND
1.输入电容要靠近MOSFET漏极
TOPSTAR TECHNOLOGY
2.MOS管尽量靠近IC芯片
Echo liu
3.芯片的Thermal GND用至少5个过孔连到信号地,用来散热 Page Name +V1.8/+V0.9S POWER
4.信号地和电源地在输出电容的负极连到一起 Size Project Name Rev
A4 S42C
A
+V1.2S 9,12,39,40,41,44
+VDC 18,28,33,35,36,38,41,42,44
+V5AL 18,25,27,29,32,35,36,38,39,40
+V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,38,40,41,42,44
+V3.3AL 6,18,20,21,22,23,26,27,28,29,30,32,33,34,35,36,38,39,40,42,44
+V5S 17,18,19,24,25,29,30,31,32,38,39,41,42,44
PC191
+V3.3AL C0603
+VDC
0.1uF/16V,X7R
1
PR394 PR395
PJ6 200K PU12 2.2
JOPEN R0402 TPS51117RGY R0603 PC184 PC185
RESISTOR_1 PC183 10UF/25V,X5R 4.7uF/25V PC186 PC187
PR201 10K R0402 0.1UF/25V,X7R C1210 C1206 1000pF/50V,X7R 1000pF/50V,X7R
2
ns C0603 ns C0402 C0402
30 V1_2S_ON 1 EN_PSY VBST 14
5
6
7
8
PR396 Co-lay
D
80130:Add a res. R0603 PQ63 +V1.2S1
PR404 PC188 0 AO4468 TestP
200K +V5S 0.1uF/10V,X7R 2 13
500mA 4 SO8_50_150 TPC80
TON DRVH
G
R0402 C0402 PL12 ns
S
PR398 5.2uH/5.5A
GND_TPS51117 10K LS2_1040
3
2
1
GND_TPS51117 PR397
301,1% +V1.2S 3 12
500mA +V1.2S
4.5A
VOUT LL 1 +V1.2S
R0402
80130:increase OCP. PQ64
PR399
5
6
7
8
AO4468
4.5A
2
D
4 11 GND_TPS51117 SO8_50_150 ns
V5FILT TRIP
1
PC189 PD17 PC192 PZ8
1uF/10V,Y5V PC190 15K 4 1N5819 1uF/10V,X7R + PC194 BZT52C2V0S-F/2.0V
1
G
+V3.3S C0603 47pF/50V,NPO R0402 PD30 SOD123 C0603 10uF/6.3V,X5R SOD323
1
1
S
PR400 C0402 SSM34PT ns PC193 C0805
1
6.2k,1% 5 10 +V5S SMA 220UF/6.3V,OSCON
3
2
1
R0402 VFB V5DRV ns Co-lay CAP6_6x7_3
PR401
100K Vref=0.75V. 4.5A
R0402 GND_TPS51117
6 9
500mA
40 V1R2S_PWROK PGOOD DRVL
PR402 PC195
10K,1% 47pF/50V,NPO 7 8
R0402 C0402 GND PGND PC196
ns 1uF/10V,Y5V
GND2
GND1
GND3
GND4
C0603
PR403
0
G1
G2
G3
G4
GND_TPS51117 GND_TPS51117 R0402
GND_TPS51117
GND_TPS51117
TOPSTAR TECHNOLOGY
Echo liu
Page Name +V1.2S
A3 S42C
A
hexainf@hotmail.com
GRATIS - FOR FREE
+VDC 18,28,33,35,36,37,41,42,44
+V5S 17,18,19,24,25,29,30,31,32,37,39,41,42,44
+V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,40,41,42,44
+V5AL 18,25,27,29,32,35,36,39,40
+V3.3AL 6,18,20,21,22,23,26,27,28,29,30,32,33,34,35,36,37,39,40,42,44
+V1.5S 8,11,26,28,32,39,40,41
+V1.8S 9,10,11,12,17,20,21,22,23,39,44
+V1.8 6,10,12,14,15,16,36,40,41,44
AD+ 19,33
BATT+ 33,34,43
PR181 0
R0402
+VDC
PD25 +V3.3AL
2 PR178
BATT+
1K
PR182 3 2 3 R0402
4.7K ns
R0402 1 PQ49 PD24
AD+
DTB114EK 1N4148WS PQ50
PR172 SOT23 +V5AL SOD323 AO4468
5
6
7
8
BAT54C 100K PC162 1 SO8_50_150
D
SOT23 R0402 0.01uF/25V,X7R V3_3S1
ns C0402 PR198 TestP
51K 4 TPC60
G
R0402 ns
5
6
7
8
S
PR179 PR171 PR180
D
PR173 33K PQ53 33K 51K
3
2
1
1K R0402 AO4468 R0402 R0402 +V3.3S
R0402 4 SO8_50_150
G
V5S1 PC165
S
MAIN_PWR_DN# TestP 0.1uF/25V,Y5V
41 MAIN_PWR_DN#
TPC60 C0402 PC166
3
2
1
3
ns +V5S 1uF/10V,X7R
PQ48 C0603
2N7002
30 MAIN_ON 1
PC178 PC179
PR167 SOT23 0.1uF/25V,Y5V 1uF/10V,X7R
2
1K PR168 C0402 C0603

R0402 510K PR212
R0402 0
+V1.8
R0402
PD23
1N4148WS
SOD323 PQ34
AO4468
5
6
7
8
1 SO8_50_150
D
PR205 0
+V5S R0402 4 V1_8S1
G
PR141 TestP
S
ns TPC80 ns
100K
3
2
1
R0402
+V1.8S
PC142
0.1UF/25V,X7R
C0603
PC141
1uF/10V,X7R
C0603
TOPSTAR TECHNOLOGY
Echo liu
Page Name V5S/ V3.3S/ V1.8S Power
A3 S42C
A
+V1.05S 6,7,8,9,12,22,23,32,40,41,42
+V1.5S 8,11,26,28,32,40,41
+V5S 17,18,19,24,25,29,30,31,32,37,38,41,42,44
+V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
+V3.3AL PR94 0 R0603 +VLAN +V5AL 18,25,27,29,32,35,36,38,40
+V3.3AL 6,18,20,21,22,23,26,27,28,29,30,32,33,34,35,36,37,38,40,42,44
+VLAN 21,22,23
+V1.8 6,10,12,14,15,16,36,38,40,41,44
+V1.2S 9,12,37,40,41,44
+V1.2AL 12,40
PD9 1N4148WS +V1.8AL 12,21,22,23,40
SOD323 +V1.8S 9,10,11,12,17,20,21,22,23,38,44 V1R05S1
V1R8AL1 TestP
1 ns
TestP PQ6 TPC60
TPC60 AO4468 ns
600111308001 ns 1A SO8_50_150 1A
ADJ/GND 0.5A +V1.2S 8 1 +V1.05S
+V3.3AL 3 VIN VOUT 2 +V1.8AL 7 2
Vo 4 6 3
PC117 PC32 5 S
10uF/6.3V,X5R 0.1uF/10V,X7R D
PU5 PR95 C0805 C0402 G
1
APE1117 220
4
SOT223 R0402 PC38 PC43
PC107 PC112 PC104 10uF/6.3V,X5R 10uF/6.3V,X5R
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R C0805 C0805 PR106
C0805 C0805 C0805 PR98 PR206 5.6K
1K PC72 1.5K,1% R0402
PR392
PR97 R0402 220 C0402 R0402 ns
100,1% ns +V5S
R0402
R0402 1000pF/50V,X7R
2
K
ref 1
Vref=1.24V(1.25V).
S42C/ change from KIA to APEC.LJ080923 A PU10
AP432N PR207
3
SOT23 2K,1%
预留+V1.2AL的大电流产生电路。 R0402
V1R2AL2
PQ12 TestP
AO4468 TPC60 +V1.5S
PR185
0.5A SO8_50_150 ns 0.5A 0 ns
+V1.8AL 8 1 +V1.2AL
7 2
6 3 PC130 R0402 ns MP:change voltage from +V5S to +V1.5S,PR207 change to 2K.LJ0308
PC53 PC55 5 S PR132 1000pF/50V,X7R PC47
10uF/6.3V,X5R 0.1uF/10V,X7R D 2K C0402 10uF/6.3V,X5R
C0805 C0402 G R0402 ns C0805
ns ns ns ns
4
V1_2AL_FB
+V1.8AL
+V5AL V1R5S1
TestP
PR137 PQ16 TPC60
4.99K,1% AO4468 ns
R0402 PU6B 1A SO8_50_150 1A
8
ns LM358 +V5AL +V1.8S 8 1 +V1.5S

1.20V_ref 5 +
SO8_50_150 500mA 7 2
7 6 3
V1_2AL_FB 6 PC140 PC139 5 S
-
PC134 PR136 ns 10uF/6.3V,X5R 0.1uF/10V,X7R D
0.01uF/16V,X7R 10K,1% PU6A C0805 C0402 G
4
R0402 LM358 PR56
4
C0402 ns 3 SO8_50_150 2K,1% PC62 PC80
+
ns 1 PC46 R0402 10uF/6.3V,X5R 10uF/6.3V,X5R
PR393
2 220 C0402 C0805 C0805
-
ns +V5S
PR135 510K ns
4
R0402 R0402 1000pF/50V,X7R
2
K
ref 1 Vref=1.24V.
PC135 1000pF/50V,X7R
C0402 ns A PU11
AP432N PR204
3
SOT23 10K,1%
R0402
32 VCC_358
+V3.3AL
VCC_358
PR213
6.98K,1%
R0402
U7B
LM358
8
so8_50_150
PR184
5 +
7 +V1.2AL
PR188
6 - LM358电压跟随器，
4.02K,1% 0
允许输出电流在30mA以内。
4
R0402 R0402 PC50 TOPSTAR TECHNOLOGY

10uF/6.3V,X5R SIS资料表明最大需要69mA， Echo liu
C0805
但S42P实测电流小于10mA. Page Name 2.5AL/1.8AL/1.5S/1.05S LDO

A3 S42C
A
hexainf@hotmail.com
GRATIS - FOR FREE
+V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,41,42,44
+V5AL 18,25,27,29,32,35,36,38,39
+V3.3AL 6,18,20,21,22,23,26,27,28,29,30,32,33,34,35,36,37,38,39,42,44
Power Good Logic CIRCUIT +V3.3S
30,42 IMVP_PWRGD
+V1.05S
+V1.5S
6,7,8,9,12,22,23,32,39,41,42
8,11,26,28,32,39,41
+VCC_CORE 8,42,44
+V1.8 6,10,12,14,15,16,36,38,41,44
AD+ 19,33,38
PR124
+V1.2AL 12,39
10K
+V1.2S 9,12,37,39,41,44
R0402
+V1.8AL 12,21,22,23,39
R334 1K +V3.3S
+VLAN 21,22,23,39
PD18 1 1N4148WS
21,26,30 PM_SLP_S3# MAIN_PWROK 30
R0402
SOD323 PD29
C291 PR119 1N5819
10K
1
0.1uF/10V,X7R SOD123
C0402 R0402 ns PR118 0
ns ns
NB_PWRGD 11,30
+V3.3AL PR123 10K ns R0402 ns
PD16 1 1N4148WS R0402
37 V1R2S_PWROK
SB/NB_PWRGD
SOD323 SB/NB_PWRGD# PC121
1000pF/50V,X7R
C0402
6
ns
PD20 1 1N4148WS MAIN_PWROK PR114 5 2 SB/NB_PWRGD#
30,36 V1_8_PWROK
20K
SOD323 R0402 PR117 0
1
PQ8 ns PR120 PQ33
SB_PWRGD 6,21,30
2N7002 100K MMDT3904 R0402 ns
3
SOT23 R0402 SC70_6
ns ns
PC120
+V5AL PR122 10K 1 1000pF/50V,X7R
R0402 C0402
ns
2
注：由EC实现
080103VA:PQ8改用MOS管， OVP CIRCUIT
3
+V1.5S PQ35
PR116 1 PR122上拉电压改为+V5AL。 PR150 DTB114EK
20K 20K R0402 SOT23
R0402 2 3 SHDN# 33
33,43 Isense_SYSN
2
PR115 PQ32
100K MMBT2222A
From +V1.8S R0402 SOT23 PC153
0.1uF/25V,Y5V PR149
1
C0402 100K
R0402
PR147
3
20K
PR108 1 PQ28 R0402
2
+V1.05S 20K MMBT2222A
R0402 SOT23 PR154 0 PR152 PQ37
2
3
R0402 20K DTB114EK
From +V1.2S PC124 32 SHDN_LOCK#
R0402
1
SOT23 PC151 PQ36
1uF/10V,Y5V 0.01uF/25V,X7R 2N7002
3
ns C0603 PQ38 C0402 1 SOT23
MMDT3904
6
PZ13 SOD323 SC70_6
2
2 1 5 2
+V5AL
BZT52C5V6S-F/5.6
1
PR146
30,35 5V3.3VALW_PWROK PZ7 SOD323 20K
2 1 PR153 PR151 R0402
+V3.3AL +V3.3AL PC161 100 PC159 20K
BZT52C3V6S-F/3.6 1uF/10V,X7R R0402 1000pF/50V,X7R R0402
C0603 C0402
PZ12 SOD323
2 1
+V1.8
PD19 BZT52C2V0S-F/2.0V
1N5819 PZ10
1
SOD123 +VCC_CORE 2 1
ns
PR110 BZT52C2V0S-F/2.0V
10K SOD323
R0402 PZ3
PR109 2 1
8.2K ns +V1.2S
R0402 ALW_PWROK 11,21,30 BZT52C2V0S-F/2.0V
3
ns PZ2 SOD323
PQ29 2 1
2N7002 注：V3.3AL高电平维持10 +V1.8AL
1 SOT23 mS以上，再发出ALW_PWROK高电 BZT52C2V0S-F/2.0V ns
平给北桥、南桥。
SOD323
ns PC118
2
3
+V1.2AL 1uF/10V,X7R
PR107 1 PQ27 C0603
10K MMBT2222A ns
ns R0402 SOT23
2
PC116 ns
4.7uF/10V,Y5V 070906VA：预留LDO产生的1.8VAL保护电路。
ns C0805
TOPSTAR TECHNOLOGY
Echo liu
Page Name Power Good Logic / OVP
A3 S42C
A
+V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,42,44
+V1.05S 6,7,8,9,12,22,23,32,39,40,42
+V1.5S 8,11,26,28,32,39,40
+V1.8 6,10,12,14,15,16,36,38,40,44
+V0.9S 16,36
+V1.2S 9,12,37,39,40,44
+VDC 18,28,33,35,36,37,38,42,44
+V5S 17,18,19,24,25,29,30,31,32,37,38,39,42,44
+V1.5S +V5S +V3.3S +V1.05S +V0.9S +V1.2S

PR169
100
30mA 100mA 70mA R0402
2
PR175
100 PR174 PR164 PR157 PR165 PR166 PR160 PR155 PR161 PR156 PR170
R0402 100 100 100 100 100 100 100 100 100 100
R0402 R0402 R0402 R0402 R0402 R0402 R0402 R0402 R0402 R0402 +VDC
ns ns
1
1
PR158
PQ46 PQ41 PQ45 PQ42 PQ44 510K
3
3
2N7002 2N7002 2N7002 2N7002 2N7002 R0402
SOT23 SOT23 SOT23 PQ40 SOT23 SOT23
2N7002 S42C/删掉DISCHG offpage connector.LJ080920
1 1 1 1 SOT23 1 1 DISCHG
PQ39
3
2N7002
2
2
PR32 SOT23
200K
R0402 1 MAIN_PWR_DN# 38
2
+V1.8 +VDC
PR177
100
2
2
R0402
PR176
100
R0402 PR159
V1_8DISCHG 510K
1
1
R0402
PQ43 PQ47
3
2N7002 2N7002
SOT23 SOT23
PR162 10K 1 1V1_8DISCHG

21,26,30 PM_SLP_S4#
R0402
2
PR163
200K
R0402
TOPSTAR TECHNOLOGY
Echo liu
Page Name Discharge Circuit
A3 S42C
A
hexainf@hotmail.com
GRATIS - FOR FREE
5 4 3 2 1
Note: +V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,44

Pin45/DPRSLPVR: 3.3V level +V5S 17,18,19,24,25,29,30,31,32,37,38,39,41,44
+VDC 18,28,33,35,36,37,38,41,44
Vih=2.3V;Vil=1.0V +VCC_CORE 8,40,44
Pin46/DPRSTP#:1.0V Level +V3.3AL 6,18,20,21,22,23,26,27,28,29,30,32,33,34,35,36,37,38,39,40,44
+V1.05S 6,7,8,9,12,22,23,32,39,40,41
Vih=0.3V;Vil=0.7V
S42C/ NS PR45,add PR408.LJ080922 +VDC
SB_DPRSLPVR_R PR408 1K Co-lay. 3A PC85

H_VID6 8 Co-lay. PC33 1000pF/50V,X7R
1
D 0.1uF/25V,X7R C0402 D
H_VID5 8
CPU_GND C0603 +
1
PC94
80130:Add a res. PC37 PC35 PC39
30 IMVP_ON H_VID4 8 4.7uF/25V,X7R 10uF/ 25V
4.7uF/25V,X7R 10uF/ 25V
2
PR45 ns 470 R0402 SB_DPRSLPVR_R C1206 C1210 C1206 C1210 VA:ns 22uF MLCC.
21,22 SB_DPRSLPVR H_VID3 8
5
6
7
8
9
PR70 ns ns
D
0
7,22 H_DPRSTP# H_VID2 8
R0603 PQ7 PC119
AOL1426 22uF/25V VCC_IMVP1
6 SIS_CLK_EN# H_VID1 8 4
TestP
G
SO8_50_150_PPAK 0.68uH/28A CAP8_3X9_0
S
PC125 1uF/10V,X7R PR40 PL3 LS2_1335 ns TPC60
CPU_GND H_VID0 8 Co-lay.
C0603 10K ns
3
2
1
1
PR46 R0402 PC57
+V3.3S
2K R0402 PL2 220UF/2.5V,POSCAP
22A
48
47
46
45
44
43
42
41
40
39
38
37
PU3 CT7343_19
1
PR49 100K G9
3V3
CLK_EN#
DPRSTP#
IVD6
VID5
VID4
VID3
VID2
VID1
VIO0
DPRSLPVR
VR_ON
+V1.05S G9 CPU_GND 0.36uH/30A +VCC_CORE
3
R0402 ns G8 PR73 LS2_1040 ns
G8
1
1
G7 G7
36
PC56 0.22uF/16V,X7R
C0603 500mA
0
R0603 PQ61
PD4 PR121
0
PR126
PR127 PR128 + +
44A
1
30,40 IMVP_PWRGD PGOOD BOOT1 AOD472A
PMON1 TestP 1 R0805 10K 10 PC34 PC48
TPC60 ns PR47 0 500mA TO252 R0402 R0402 R0402 C0603 220UF/2.5V,POSCAP
1
7 PM_PSI# 2 35
2
R0402 PR50 PSI# UGATE1 SBM54PT 5.11K,1% 1uF/10V,X7R CT7343_19
2
PC126
CPU_GND
PC59 0 3 PMON PHASE1 34 500mA SMB PC123
C0402 1000pF/50V,X7R R0402 0.1uF/25V,Y5V
PR51 500mA C0402
ISEN1
CPU_GND 4 RBIAS PGND1 33
PR283放到最热的地方 147K,1% 0.22uF/16V,X7R MP:Install PC34 and
变化范围为2.56K PR52 R0402 5 32 500mA LAGTE1 C0603 PC41,改用0603的物料。LJ0308
4.02K,1% 7,21 VR_PROCHOT# VR_TT# LAGTE1
R0402 PR48 NTC 6 ISL6262A 31 VSUM VCC_OUT
CPU_GND NTC PVCC +V5S
C 470K,1% PC61 C
C0402 PC60 R0603 C0402 QFNS48_0D5_1G 500mA LAGTE2 PC137
ISEN2
7 SOFT LGATE2 30
1000pF/50V,X7R 0.1uF/25V,Y5V
CPU_GND
0.022uF/16V,X7R 8 OCSET PGND2 29 500mA C0402 PC127
PR74 C0603
PC71 1000pF/50V,X7R 9 VW PHASE2 28 500mA 0
2
C0402 R0603 PD6 PR131 0.22uF/16V,X7R
500mA
1
PR53 10 27 1 5.11K,1%
COMP UGATE2
2
PC63 10K PR55 R0402 PQ62 PR138 PR130 PR129
1000pF/50V,X7R R0402 6.98K,1% 11 FB BOOT2 26 500mA AOD472A SMB 0 10K 10 PC41 PC49
1
+ +
C0402 TO252 SBM54PT R0805 R0402 R0402 1uF/10V,X7R 220UF/2.5V,POSCAP
12 25 PC64 R0402 C0603 CT7343_19
1
FB2 DROOP NC 0.22uF/16V,X7R
PL5
VDIFF
VSUM
ISEN2
ISEN1
VSEN
PC69 C0603
GND
VCC_OUT
VDD
RTN
DFB
1
VIN
3300pF/50V,X7R PC58
22A
VO
G1
G2
G3
G4
G5
G6
PC70 C0402 PR57 0.36uH/30A ns 220UF/2.5V,POSCAP
3
2
1
100pF/50V,NPO PR59 10K LS2_1040 CT7343_19
G1
G2
G3
13
14
15
16
17
18
19
20
21
22
23
24
G4
G5
G6
C0402 R0603 R0402
S
1
PR54 6.04K,1% SO8_50_150_PPAK Co-lay.
G
CPU_GND 4
ns PR77 AOL1426 PL6 0.68uH/28A
VSUM
ISEN2
ISEN1
75K
VCC_OUT
CPU_GND 0 PQ15 LS2_1335

R0402
R0603
D
5
6
7
8
9
PR66 10 PC81 1000pF/50V,X7R PR76
+V5S
R0402 C0402 10
PR71 2K PC76 R0402
R0402 1uF/10V,X7R
PR67 C0603 CPU_GND PC88 PC40 PC97 PC36 PC96 PC44
8 VCCSENSE
10 PC129 0.1uF/25V,X7R 10uF/ 25V 4.7uF/25V,X7R 10uF/ 25V 4.7uF/25V,X7R 1000pF/50V,X7R
B R0402 1000pF/50V,X7R PC77 C1210 C1206 C1210 C1206 B
C0603 C0402
PC83 C0402 0.1uF/25V,X7R ns ns
1uF/10V,X7R PC74 C0603 Co-lay. Co-lay.
C0603
ns
0.1UF/10V,X7R
C0402
PR75
R0402
10
+VDC 3A +VDC
CPU_GND S42C/ Mosfet parnumber.LJ080923
PR68 PR60 1.21K,1% PC136 1000pF/50V,X7R PR134
8 VSSSENSE
0 R0402 C0402 R0402 IMVP_PWRGD# IMVP_PWRGD
+V3.3AL
R0402 3.57K,1%
PR69 PC131 PC75 PR72 PR139 10K,1%
30 IMVP_ON
100
R0402
1000pF/50V,X7R
C0402
C0402
330pF/50V,X7R
1K,1%
R0402
R0402
IMVP_VI Test Debug +V1.05S
ns PR140 1K,1% PR92 PR84
CPU_GND R0402 1K 10K
CPU_GND R0402 ns
3
PR133 ns R0402
PR125 CPU_GND
PC133 4.53K,1% PR79 56 R0402 ns
0.1UF/10V,X7R R0402 8 H_VID0 PR81 56 R0402 ns IMVP_PWRGD#
8 H_VID1 2 5
C0402 PC128 PR80 56 R0402 ns
4
0 0.22uF/10V,X7R 8 H_VID2 PR83 56 R0402 ns
R0402 C0603 8 H_VID3 PR86 56 R0402 ns PR90 PQ18 PR82
PC132 8 H_VID4 PR89 56 R0402 ns 100K SC70_6 510K
CPU_GND 0.027uF/50V,Y5V 8 H_VID5 R0402 2N7002DW ns
8 H_VID6
1
C0603 J1 ns ns R0402
J6 J5 J2 JOPEN
JOPEN JOPEN JOPEN RESISTOR_1
RESISTOR_1 RESISTOR_1 RESISTOR_1 ns
ns ns ns ns ns
A A
2
2
J4 J3 TOPSTAR TECHNOLOGY
JOPEN JOPEN
RESISTOR_1 RESISTOR_1
Page Name
+VCC_CORE CIRCUIT
A3 S42C
A
5 4 3 2 1
5 4 3 2 1
BATT+ 33,34,38
+V5AL 18,25,27,29,32,35,36,38,39,40
+V3.3AL 6,18,20,21,22,23,26,27,28,29,30,32,33,34,35,36,37,38,39,40,42,44
+V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42,44
PU1
PC10 PR21 0
1.5A
1uF/10V,X7R VDDP 15 2 Isense_SYSN 33,40
D VDDP ACSET CHG_GND D
C0603
PR22 R0402
4.7 5V_internal_LDO Co-lay。
R0402 1 PC11 PC23 PC21 PC17 PC18
PC24 VDD 0.1uF/50V,Y5V PD2 SOD323 1000pF/50V,X7R 0.1uF/25V,X7R 10uF/ 25V 4.7uF/25V,X7R
CHG_GND
1uF/10V,X7R 24 C0603 1N4148WS/75V/150mA C0402 C0603 C1210 C1206
C0603 DCIN 1
ns ns
27,33 Isense_SYSP 19 CSIP
PC6 PR14 0
PR3 0.1uF/50V,Y5V R0402
C0603 20 17 PR203
33,40 Isense_SYSN CSIN UGATE R0402 4.7
10 R0402
PD1
1
PC20
1000pF/25V,X7R
PC27
5600pF/50V,Y5V VDDP D1 D1
PQ3 12.63V
5 ICOMP BOOT 16 1
C0402 C0603 ISL6251HAZ
1N4148WS/75V/150mA
PR202 8
10K PR103
2A
PC4 G1
SSOP24_25_150 SOD323 R0402 S1 0.05,1% PC13 BATT+
PC25 PC22 0.01uF/25V,X7R 6 0.1uF/50V,Y5V PL1 R2512 0.1uF/25V,X7R
C0402 VCOMP C0603 phase C0603
5 7 1
R0402 10K 18 phase 15uH/3.6A
PHASE AO4932 PR214 LS2_1040
6 PC16
CHG_GND 3.3V 11 VADJ
2.2 PC15
SO8_50_150 D2 R0805 4.7uF/25V,X7R 10uF/ 25V PC14
C C
14 PR215 3 ns C1206 C1210 1uF/25V,Y5V
LGATE 0 ns C0805
30 CHG_ON 3 EN R0402 G2 S2 PC163
13 0.01uF/25V,X7R
PR19
4
6.98K,1% PGND C0402
PR407 1K 9 ns
30 SET_I CHLIM
21 PR2
R0402 CSOP
PR18 PC5 2.2 R0402
PC197 15.4K,1% 2.39V_Vref 8
1uF/10V,X7R R0402 VREF 1uF/10V,X7R
CSON 22
C0603 C0603
PR16 10
10.5K,1% ACLIM
R0402 4 CHG_GND
CELLS
S42C／添加RC滤波，需要在 0.643Vref
23 ACPRN PR15
S42QT上面验证，LJ080918 7
ICM SYS_I_Sense 30
PR17 100 R0402 PC26
设置适配器限流值为 20K,1%
82mV/25m ohm=3.28A. R0402 GND 12
3300pF/50V,X7R Layout note:
C0402
B
Far away from critical signal trace B
SET_I 充电电流 PR20 0
CHG_GND R0402
0V 0A
0.33V 200mA CHG_GND
CHG_GND
2V 1.2A
3.3V 2A
SYS_CURRENT SYS_I_Sense
SYS_I_Sense SYS_CURRENT
>3.6A >1.8V
1A
500mV <3A <1.5V
3A
1.5V
3.33A
1.67V
TOPSTAR TECHNOLOGY
A Echo liu A
Page Name CHARGER(ISL6251)
B S42C A
5 4 3 2 1
hexainf@hotmail.com
GRATIS - FOR FREE
5 4 3 2 1
+V1.2S 9,12,37,39,40,41
+V3.3S 6,7,11,14,15,17,18,19,20,21,22,23,24,26,27,28,29,31,32,37,38,40,41,42
H5 H11 H8 H1 H2 H6 H9 H7 H4 H3 H10
+V3.3Al 6,18,20,21,22,23,26,27,28,29,30,32,33,34,35,36,37,38,39,40,42
+V5S 17,18,19,24,25,29,30,31,32,37,38,39,41,42
+V1.8 6,10,12,14,15,16,36,38,40,41
+V1.8S 9,10,11,12,17,20,21,22,23,38,39
+VCC_CORE 8,40,42
HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE
1
1
TH_276_315_118 TH_240_92 TH_276_315_118 TH_276_315_118 TH_276_315_118 TH_276_315_118 TH_315_118 TH_315_118 TH_315_216 TH_315_118 TH_240_92
ns ns ns +VDC 18,28,33,35,36,37,38,41,42
ns ns ns ns ns ns ns ns +V3.3S +V3.3S
D C497 C519 D
GND GND GND GND_AUD GND_BAT GND GND GND GND GND GND
0.1uF/10V,X7R 0.1uF/10V,X7R
VerD:Change footprint from TH_315_112 to TH_315_118 llh0418 C0402 C0402
VerB：更改螺丝孔footprint
071024
VerD:Change footprint from TH_276_315_112 to TH276__315_118 llh0418 E5 E6 E9 E8 E7 E12 E10 E11 GND GND
V13 V52 V51 V44 V27 V1
1
V3 V28 V25 V37 V53
EMI EMI EMI EMI EMI EMI EMI EMI VerB:Add stitching Cap for MII
1
1
1
ns ns ns ns ns ns ns ns
VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA
1
1
ns ns ns ns ns ns ns ns ns ns ns
GND
GND GND +V1.8
V38 V29 V56 V55 V54 V49 V50 V45 V47 V46 V11 V10 V31 V32 V12 V9 V21 V20 V19 V18
1
1
VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA C520 C521 C522 C523
1
1
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V 0.1UF/25V,Y5V
C0402 C0402 C0402 C0402
ns ns ns ns
GND GND
FMK4 FMK3 FMK2 FMK1 FMK12 FMK11 FMK7 FMK6 FMK5 FMK8 FMK9 FMK10
V41 V42 V43 V48 V39 V40 V34 V36 V30 V33 V24 V23
1 VerB:add four stitching Caps for Memory
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
C 071026 C
FMARKC FMARKC FMARKC FMARKC FMARKC FMARKC FMARKC FMARKC FMARKC FMARKC FMARKC FMARKC VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA
1
ns ns ns ns ns ns ns ns ns ns ns ns
VIA_D10 VIA_D10 VIA_D10 VIA_D10 VIA_D10 VIA_D10 VIA_D10 VIA_D10 VIA_D10 VIA_D10 VIA_D10 VIA_D10
ns ns ns ns ns ns ns ns ns ns ns ns
FD7 FD8 FD2 FD1 FD4 FD3 FD6 FD5 GND GND
E2 E3
1
1
1 1 1 1 1 EMI EMI
1 1 1 1 1 1 1 ns ns
For MutIOL
1
1
FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS FMARKS V22 V26 V8 V17 V16 V15 V14 V7 V5 V4 V6 V2 V35
ns ns ns ns ns ns ns ns
1
VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA VIA
1
VIA_D10 VIA_D10 VIA_D10 ns ns ns ns ns ns ns ns ns ns VerB:加一个0.22uF for EMI
GND_AUD ns ns ns 071025
+VDC
GND GND
+V1.8S +V1.8S +V1.8S
+V5S +V1.8 +V1.8 +V1.8 +V1.8 +V1.8 +V1.8 +V1.8
ns C612 ns C613 ns C614 ns C615 ns C616
0.1uF/25V,Y5V 0.1uF/25V,Y5V 0.1uF/25V,Y5V C494 C495
1uF/25V,Y5V 1uF/25V,Y5V C0402 C0402 C0402 C0402 C489 C490 C491 C492 C493 C498 C499 C517
C0805 C0805 0.1uF/10V,X7R For DIMM 0.1uF/10V,X7R 0.1uF/10V,X7R
0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R C0402 C0402 C0603
C496 C0402 C0402 C0402 C0402 C0402 C0402 C0402 +V1.8
GND GND GND 0.22uF/16V,X7R
GND
+V3.3S GND GND GND GND GND GND GND
B B
+VDC VerB:for EMI
071029
For IDE
+V3.3S +V3.3S +V3.3AL +V5S +V5S +V5S +V5S +V5S +V5S
C617 C618 C619
0.01uF/25V,X7R 0.01uF/25V,X7R 0.01uF/25V,X7R
C0603 C0603 C0603 C468 C469 C470 C0402 C0402 C0402 C0402 C0402 C0402
ns ns ns 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R 0.1uF/10V,X7R
0.1uF/10V,X7R0.1uF/10V,X7R 0.1uF/10V,X7R
C0402 C0402 C0402 C483 C484 C485 C486 C487 C488
+V3.3S +V3.3S
GND
GND GND GND +V3.3S +V3.3S +V3.3S +V3.3S GND GND
C525 C524
+V3.3AL
0.1uF/10V,X7R0.1uF/10V,X7R
C0402 C0402
C663
GND GND 0.1uF/10V,X7R

C0402
VerC:Add power stitching Cap

GND
A +V3.3S GC194 0.1uF/10V,X7R +V1.8S A

C0402 TOPSTAR TECHNOLOGY
GC195 0.1uF/10V,X7R Echo liu

+V3.3S +V1.8S
C0402 Page Name
HOLE & EMI
GC192 0.1uF/10V,X7R GC196 0.1uF/10V,X7R Size Project Name Rev
+V3.3S +V1.2S +V3.3S +VCC_CORE
C0402 C0402 A3 S42C
A
GC193 0.1uF/10V,X7R GC197 0.1uF/10V,X7R Date: Saturday, September 27, 2008 Sheet 44 of 51
+V3.3S +V1.2S +V3.3S +VCC_CORE
C0402 C0402 PROPERTY NOTE: this document contains information confidential and property to
+V1.8S GC198 0.1uF/10V,X7R +V1.2S +V1.8S GC199 0.1uF/10V,X7R +V1.2S to others or used for any purpose other than that for which it was obtained without
C0402 C0402 the expressed written consent of TOPSTAR
5 4 3 2 1
5 4 3 2 1
CLOCK Distribution CLK_FBIN

CHA DUAL DIMM
CLK_FBOUT
SODIMM0
SODIMM1
Merom
166/200/266MHz MEM_CHA_CLK0
D
CPU_L0# CLK_CPU_BCLK# MEM_CHA_CLK#0 D
CLK Buffer ICS9P935

CPU_L0 166/200/266MHz CLK_CPU_BCLK
MEM_CHA_CLK2
MEM_CHA_CLK#2
166/200/266MHz
CPU_L1# CLK_NB_BCLK# DDR_FWD_CLK
CPU_L1 166/200/266MHz CLK_NB_BCLK DDR_FWD_CLK#
MEM_CHA_CLK1
ADAPTER MODE
SiS672 MEM_CHA_CLK#1
100MHz
PCIE_L0# NB_PCIE_CLK#
PCIE_L0 100MHz NB_PCIE_CLK MEM_CHA_CLK3
MEM_CHA_CLK#3 no Check RTC
SUSCLK
133MHz Xtal&Battery
ZCLK0 ZCLK
14.318MHz yes
REF0_2X VOSCI
EC_RTC,+V5_STB, no
100MHz +V3.3AL,+V5AL
PCIE_L1# 307_PCIE_CLK Check ISL6232
PCIE_L1 100MHz
307_PCIE_CLK#
SIS307ELV
14.318MHz yes
REF0_2X CLK14_307
Check BIOS FLASH ROM no

no EC XTAL Check EC Xtal
C
EC&BIOS ADDRESS:A16-A18 32.768K C
100MHz ROM yes
PCIE_L2# CLK_PCIE_ICH#
PCIE_L2 100MHz CLK_PCIE_ICH yes
100MHz Press
SATA# CLK_ICH_SATA# 32.768KHz
SATA 100MHz CLK_ICH_SATA no LPC PWRSW
Check SIS968 Frame#
14.318MHz yes
14.318MHz
REF1 CLK_ICH14 SiS968
ZCLK0
133MHz
ZCLK133MHZ 24MHz Audio Codec yes SLP_S4# no
12MHz CLK_USB12 ALC882H SLP_S3# Check EC output PWRBTN#
12M no SLP_S1#
Check SIS968 PCI
33MHz
PCI0 CLK_ICHPCI
Frame# yes
Azalia MDC
no
Sytem Main
100MHz yes Check PWM & MOS Switch
PCIE_L4#
100MHz
PCIE Power Plane
PCIE_L4
NEWCARD
no yes
CPUBUS
100MHz Check CPU no
PCIE_L5# MPCIE ADS#
PCIE_L5 100MHz
MAIN_PWROK Check Power Good logic
ROBSON
yes
DEBUG
33MHz yes
PCI1
B no no B
33MHz Check SIS672 H_CPURST# All Clock Check Clock chip

PCI2
PC87541L-VPC 32.768KHz
yes yes
no yes no
Card Reader 12MHz Check SIS968 H_CPUPWRGD Check IMVP6 for Meron
PM_ICH_PWROK
(USB6236) PLT_RST# CPU
ICS9LPR600_TSSOP-56P
A A
TOPSTAR TECHNOLOGY
Echo liu
Page Name
Clock Distribution
C S42C
A
hexainf@hotmail.com
5 4 3 2 1
POWER Distribution
D D
CPU(Socket-M) R0.92
0V-1.4625V VCC 0V-1.4625V VCC
1.05V FSB VCCP
CPU Core Regulator
INVP-6 Compliant 1.5V VCCA
USB
DDR2 SO-DIMM V5A&V3.3A
Battery 0.9V SM VTT
VCCP,GMCH_CORE,
ICH_CORE 1.8V VDD/VDDQ
1.05V SATA
V3.3S&V5S
AC Calistoga GMCH
1.8V DDR I/O
C DDR VCC Regulator 3.3V TVDAC C
V1.8 PATA
1.05V FSB VTT
V5S
3.3V DAC Regulator 1.05V Core(Int)
System V5 V3.3S
VREG 1.5V PCI Express(X16)
3.3V LDO
9-19V 1.5V PCI Express(X1)
DDR VTT Regulator FWH
V0.9S 1.5V SDVO
V3.3S
1.5V LVDS
1.5V DMI
1.5V HSIO
VGA_CORE LVDS
1.15V System VREG(9-12.6V)
NB8M
CK410-M
ICH7-M V3.3S
1.05V VCC_CPU
1.5V Interface Regulator 1.05V Core
V1.5S 1.5V PCI Express SMC/KBC
1.5V RING V3.3A
B
V5S 1.5V SATA B
1.5V LAN
5.0V Interface Regulator 1.5V USB AC97/Azalia
V5A V5 V5,V3.3,V3.3A
1.5V AZALIA
5VRef
RTC 5VrefSus
V3.3S 3.3VBG
3.3V Interface Regulator RTC
V3.3A Mini-PCI Express
3.3V IDE/PCI V1.5S +1.5V
3.3V VccSus V3.3A +3.3Vaux
1.5VSUS(IntVR) V3.3S +3.3V-3.0A
1.05VSUS(Int/ExtVR)
A A
TOPSTAR TECHNOLOGY
Echo liu
Page Name
Power Distribution
C S42C
A
5 4 3 2 1
5 4 3 2 1
Power Off Sequence(Adapter Mode)

With AC adapter
S0 S0 S5 S5 G3
With Main Battery

Power On Sequence(Battery mode) Power On Sequence(Adapter mode) STPCLK#
Without AC With AC adapter

adapter G3 G3 S5 S3/S4/S5 S0 S0 G3 G3 S5 S3/S4/S5 S0 S0 STP_PCI# T24
PCIRST#
M_CKE_A[3:0] M_CKE_A[3:0]
T10 T10 CPURST#

T18a T18a
D
CPURST# CPURST# D
SLP_S3#(Input to EC)
(CPU PWRGD) (CPU PWRGD)
H_PWRGD T13 T14 T16 H_PWRGD T13 T14 T16
T23
PCIRST# PCIRST#
T15 T15
IMVP_ON(EC Output)
T9 T9
IMVP_PWRGD(Input to EC)
T9a T9a T22
NB_PWRGD(Input to NB) NB_PWRGD(Input to NB)
SB_PWRGD(Input to SB) SB_PWRGD(Input to SB) MAIN_PWROK T21a
PCI CLK CLK

NB_PWRGD(Input to NB)
SB_PWRGD(Input to SB)
V1_2S_ON(EC Output)
IMVP_PWRGD(Input to EC) IMVP_PWRGD(Input to EC)
T10a T22d
SIS_CLK_EN#
V0_9S_ON(EC Output)
SIS_CLK_EN#
Vboot Vboot
+VCC_CORE +VCC_CORE V1_8_ON(EC Output)
T43 T10a T43
MAIN_ON(EC Output)
T42 T42
H_VID* H_VID* +V3.3S,+V5S,+1.8S,+V1.8,+V1.5S

+V1.2S,+V0.9S,+V1.05S,+VGA_CORE
T22a
IMVP_ON(EC Output) IMVP_ON(EC Output) ALWAYS_ON(EC Output)

T25(a)
IacN
MAIN_PWROK(Input to EC) T8 MAIN_PWROK(Input to EC) T8
C C
+V3.3AL,+V5AL
+V1.05S +V1.05S
T22c
5V3.3VALW_PWROK(Input to EC)
T44 T44
+V1.5S +V1.5S
+V3.3S,+V5S,+1.8S,+V1.8 T41 +V3.3S,+V5S,+1.8S,+V1.8 T41

+V1.2S,+V0.9S,+VGA_CORE +V1.2S,+V0.9S,+VGA_CORE
V1_8_ON,V0_9S_ON,V1_2S_ON V1_8_ON,V0_9S_ON,V1_2S_ON
MAIN_ON,(EC Output) MAIN_ON,(EC Output) T07 Pull out AC_Battery
T6(a)
SLP_S4#(Input to EC) SLP_S3#(Input to EC)

T6(a) With Main Battery
Without AC
Power Off Sequence(Battery Mode)
adapter
PWRBTN#(EC Output)
T6 S0 S0 S5 S5 G3
T4b T4 STPCLK#
T5 PWRBTN#(EC Output)
ALWAYS_ON(EC Output) T3 T24
T4 T5 STP_PCI#
T4a
ALW_PWROK(EC Output) PWRSW#(Input to EC) PCIRST#
5V3.3VALW_PWROK(Input to EC) T6 CPURST#

PWR_SW_VCC2
+V3.3AL,+V5AL (PRESS POWER BUTTON) SLP_S3#(Input to EC)
T3
PWR_SW_VCC2 T4b SLP_S4#(Input to EC)
ALWAYS_ON(EC Output) T23
PWRSW#(Input to EC) T4a

B ALW_PWROK(EC Output) IMVP_ON(EC Output) B
(PRESS POWER BUTTON)

5V3.3VALW_PWROK(Input to EC) IMVP_PWRGD(Input to EC)
T22
EC_RTC
+V3.3AL,+V5AL MAIN_PWROK
T1 EC_RTC T21a
+VDC
ALW_EN NB_PWRGD(Input to NB)
SB_PWRGD(Input to SB)
BAT_PWRGD V1_2S_ON(EC Output)
+VDC T22d
VCCRTC T2 T1 V0_9S_ON(EC Output)

AD+
V1_8_ON(EC Output)
BAT_PWRGD
MAIN_ON(EC Output)
VCCRTC T2
Plug out main battery
+V3.3S,+V5S,+1.8S,+V1.8,+V1.5S
+V1.2S,+V0.9S,+V1.05S,+VGA_CORE
T22a
Plug AC_Adapter
ALWAYS_ON(EC Output)
T25(a)
+V3.3AL,+V5AL
5V3.3VALW_PWROK(Input to EC)
T22c
IacN
A A
Pull out main battery
TOPSTAR TECHNOLOGY
Page Name
Power ON/OFF Timing
Custom S42C A
5 4 3 2 1
hexainf@hotmail.com
GRATIS - FOR FREE
5 4 3 2 1
C0 to C3 to C0 Timings S0 to S3 to S0 Timing
CPU I/F
Signals Unlatched Latched Unlatched S0 S0 S3 S3 S3 S0 S0
T28
STPCLK#
(ICH Output) STPCLK# T37
T26
T33
D T18a D
Bus Master Active Idle
CPUSLP# T29 CKEA[3:0],CKEB[3:0]
(ICH Output)
DPSLP# T30a T32b DMI Message
(ICH Output)
T32a T21
STP_CPU# T31
T30b T15
(ICH Output)
STP_PCI# T24
CPU Clocks Running Stopped Running

T19
PCIRST#
T34a T14+T16
T36b
Break Event CPURST# T13
C0 to C4 to C0 Timings T23
C T49 C
IMVP_ON(EC Output)
CPU I/F Unlatched Latched Unlatched
Signals
T28 IMVP_PWRGD(Input to EC)
STPCLK# T22
(ICH
Output) T26 T33 MAIN_PWROK
T33 T21a
Active
Bus Master
T29 NB_PWRGD(Input to NB)
CPUSLP# SB_PWRGD(Input to SB)
(ICH
Output) T32b V1_2S_ON(EC Output)
T30a
DPSLP# T22d
(ICH
Output) T32a V0_9S_ON(EC Output)
T30b
STP_CPU#
(ICH
Output) MAIN_ON(EC Output)
T34a
T10a
CPU Clocks Running Stopped Running
+V3.3S,+V5S,+V1.5S,+V1.2S T22a
DPRSTP# T35 +V0.9S,+V1.05S,+VGA_CORE
T36b
(ICH T25(a)
B T36a B
Output) T34b Break Event
DPRSLPVR
(ICH Output)
CPU Vcc
Break
Event
C0 to C2 to C0 Timings
CPU I/F Unlatched Latched Unlatched
Signals TOPSTAR TECHNOLOGY
T28
A STPCLK# A
(ICH Page Name ACPI mode switch timings
Output) T26
T27 Size Project Name Rev
Break Custom S42C
Event A
5 4 3 2 1
5 4 3 2 1
Isense_SYSP 1B 3A 2B
BATT+
5V3.3VALW_PWROK EC_RTC LDO
PQ2
D D
5A 5B +V1.8AL
1A 1 +VDC
AD+
Always_On 4B +V3.3AL
+V2.5AL
PQ1 PD22/23 PQ3 +V3.3AL,+V5AL
Power +V1.2AL_PWRGD
OR 4A +V1.2AL
BAT_OV# SHDN# TPS51120
PWRSWVCC2
V1_8_PWROK 12+
ALWAYS_ON 6B Note:+VGA_CORE/+1.8S PWR SEQ.By GPU
AD+ ALW_EN 2A System Power 15 +V3.3S
3B 8A +V_S +V5S +V1.8S
Isense_SYSP
PWRSWVCC2 PWRSW# DDR Power 13 +V1.8 +V1.8S
ALW_PWRGD Logic 8B 9A TPS51116 +V0.9S
AC/DC ON
13 LDO +V1.5S
5V3.3VALW_PWROK 12 MAIN_ON +V3.3AL
ALW_PWRGD 12
7A 5V3.3VALW_PWROK 5B
V1_8_ON
V0_9S_ON
+V1.2AL_PWRGD 7B PM_SLP_S4# 11 5A +V3.3S
MAIN_ON 13 15 13
C
PM_SLP_S3# 11 +V1.05S C
V1_8_PWROK 12+ NVVDD_ON V1_2S_ON
19 Power Good +V1.05S/+V1.5S PWRGD 18 18

MAIN_PWROK
EC_KBC And Logic
SET_I PM_SLP_S3# 11 VGA_CORE
SIS968 10 PM_PWRBTN# PC87541L +VGA_CORE +V1.2S
CHG_ON TPS51124
V1.2S / VGACORE_PWROK 17 16
6A ALWAYS_ON
IMVP_ON
V1.2S / VGACORE_PWROK
SYS_I_Sense
6B
SB_PWRGD 23 NB_PWRGD
SYS_I_Sense AC_IN
23 GPIO5_VID0
20
IMVP_PWRGD
BAT_PWRGD SB_PWRGD
Graphic
GPIO6_VID1
0 RTC BAT Charge BATT+
NB8M
MAIN_PWROK
+VDC 17
ISL6251
NB_RST#
to IMVP_ON
24 Delay 100mS
22
PCI_RESET# SET_I
CHG_ON
B B
NB_PWRGD
23 SET_I 充电电流
0V 0A
0.33V 200mA
22 IMVP_PWRGD 21 3.3V 2A
SIS671DX VCC_CORE SIS_CLK_EN# Clock GEN.
ISL6262A ICS9LPR600 Note:
21 SYS_I_Sense SYS_CURRENT
*A:For adapter in
+VCC_CORE 500mV 1A
*B:For battery only
H_PWRGD
25 H_CPURST# 26 1.5V 3A * :For all

1.67V 3.33A
H_PWRGD
Merom
CPU
A A
TOPSTAR TECHNOLOGY
Page Name PowerOnSequence & Reset Map

A3 S42C A
GRATIS - FOR FREE
5 4 3 2 1
RESET Mapping
NB_RST# H_CPURST#
D
SiS671DX Memron(Socket-P) D
33ohm
SMI#/NMI# Toplogy
GPU_PE_RST#
PCI_RESET# SB_PCI_RST# +V1.05S
+V1.05S +V3.3S
PCIEx16(GPU NB8M-SE)
33ohm
EC(KBC/TP/GPIO)
Memron(Socket-P) SiS968 B stepping
PCI_RST# H_SMI# SB_SMI#
33ohm NEWCARD A3 AD23
H_NMI# W4 P22
B4 AE25
SiS968
PCI_RST#
MINI PCIE
C
Thermal/FAN/OVP/OTP Control Logic Mapping C
LRESET2# P165 EC(KBC/TP/GPIO)

P19
+3VAL
Core domain reset
LRESET1# Host domain reset +V1.05S
Memron(Socket-P) PM_THRMTRIP#
Level shift C7 +V1.05S
AD25 SiS968 IMVP6
IDE_RST#
PCI_RST# IDE(ODD)
RGMII_RESET# +3VAL
D21 AC24 5
VR_PROCHOT#
NS 0ohm
PHYRSTB PHY (RTL8201CL) +V5AL/5.6V
SHDN_LOCK#
Bidirection +V3.3AL/3.6V
CPU External
Level shift Over Voltage +V1.8/2.0V
Thermal sensor +V3.3S
B Alert# Protect +V1.5S/2.0V B
OVT_SHDWN#
OD (OVP/OTP) +V1.05S/2.0V
33ohm
HDA_RST# +VCC_CORE/2.0V
ALC662 EC(KBC/TP/GPIO)
EC_PROCHOT# +VGA_CORE/2.0V
+V3.3S
33ohm ALT_ON
Reset function
CLK GEN. AND Gate and
MDC
SB_PWRGD
SYS_RST#
Sys_rst# FAN1_V Cntrol Logic
GPIO18/KBRST# FAN1_V=2.65V,Vfan=4V
RST# Button OD GPU_OVT#
GPIO8
FAN/DC Voltage SHDN#
Control Circuit BATTERY
GPU Internal AC/DC Switch +VDC
Vfan Fan_back
Thermal sensor
FAN ADAPTER
(DC Mode)
A
EC(KBC/TP/GPIO) TOPSTAR TECHNOLOGY
A
Page Name RESET/NMI/SMI/THERMAL/OV(T)P

A3 S42C A
5 4 3 2 1
5 4 3 2 1
SIS968 GPIO Routing

Pin Name Type Power Net Name Description Default Used
GPIO0 I/O +V3.3S CPUSTP# For CPU C State Control,Output toCLK IC stop CPU clk CPUSTP#
GPIO1 I/O +V3.3S N/A BIOS Configuration for output NC/output
GPIO2 I/O +V3.3S PM_THRM# Thermal information from EC PM_THRM#/Input
GPIO3 I/O +V3.3S SB_EXTSMI# SMI From EC not used NC/output
GPIO4 I/O +V3.3S PM_CLKRUN# CLKRUN# From EC PM_CLKRUN#/Input
CPU C State CONTROL TOPLOGY
GPIO5 I/O +V3.3S PANEL_ID1 Not used NC/output
GPIO6 I/O +V3.3S PANEL_ID0 Not used NC/output
D +V1.05S D
GPIO7 I +V3.3AL PM_BATLOW# EC Ouput Low When Detected BAT Voltage too lower?? PM_BATLOW#
GPIO8 I/O +V3.3AL SB_RING Ring up wakeup function(Pulse >4ms) NC/output Merom-CPU PCI-Express Card
SIS671DX
GPIO9 I/O +V3.3AL EC_RUNTIME_SCI#Embedded controller SCI Interrupt to SIS968 EC_RUNTIME_SCI#/Input Socket-P (NEW CARD)
GPIO10 O/PU +V3.3AL SLP_S4# SIS968 Only as SLP_S5# function SLP_S4#
NEWCARD_CLKREQ#
GPIO11 I/O/OD +V3.3AL PCI_STOP# For STOP PCI CLKS with S/W setup by I2C PCI_STOP#/Output PIN/E5
GPIO12 I/O/OD +V3.3AL DPSLP# For CPU C State Control H_DPSLP#

DPSLP#
AGP_STOP#
AGP_BUSY#
+V1.05S +V3.3AL
+V1.05S +V1.05S
GPIO13 I/O +V3.3AL SB_DPRSLPVR CPU Deep Sleep control for VR SB_DPRSLPVR/Output
+V3.3AL
GPIO14 I/O/OD +V3.3AL AGP_STOP# STOP AGP CLKs For 671DX Not used AGP_STOP#/Output
GPIO15 O/PU +V3.3AL SLP_S3# SIS968 Only as SLP_S3# function SLP_S3# SLP_S4#
GPIO16 I/O/OD +V3.3AL SB_DPRSTP# For CPU C State Control /Ouput SB_DPRSTP#/Output
SB_DPRSTP# PIN/B7
GPIO17 I/O +V3.3AL H_A20GATE# A20GATE# from KBC,when active, H_A20GATE#
CPUSTP#
use to force A20M# signal active/
GPIO18 I/O +V3.3AL H_RCIN# H_RCIN#/Input
Keyboard Reset input from KBC H_CPUSLP# CLK Generator
GPIO19 O/PU +V3.3S SMBCLK SMBCLK SIS968
SIS968 SMBUS Master Controller CLK
GPIO20 I/O/PU +V3.3S SMBDATA SMBDATA H_STPCLK#
SIS968 SMBUS Master Controller DATA PCI_STOP#
GPIO21 O +V3.3AL EESK GMAC EEPROM CLK EESK
SIS_CLK_EN
GPIO22 O +V3.3AL EEDI GMAC EEPROM DATA OUTPUT FROM SIS968 EEDI
H_DPRSTP#
GPIO23 I +V3.3AL EEDO GMAC EEPROM DATA INPUT TO SIS968 EEDO
PM_PSI#
SB_DPRSLPVR
GPIO24 O +V3.3AL EECS GMAC EEPROM CHIP SELECT EECS
PCIE_CLKREQ#
C C
Pin/46
CPU Core Voltage Regulator

(ISL6262A) SIS_CLK_EN# PCI-E Mini-Card
(Wireless LAN)
Embeded Controller GPIO Routing After updating from R18P VC

Pin165 I Digital EC_LPC_RST# Host domain reset(LPC/Host controlled/Shared memory host)
Pin5 O Digital A20GATE HIGH LEVEL AFTER PCI RESET# SO DOUBLE CHECK AGAIN??
Pin110 I Digital ALW_PWROK Used for EC detected AlW_PWRGD
Pin63 O Digital V1_2S_ON
Pin156 I Digital 5V3.3VALW_PWROK
Pin90 I Analog AD7
Pin102 O Digital NB_PWRGD
Pin32 O Digital SB_PWRGD
Pin43 I Digital Media HW pull high/NOT USED
Pin176 I Digital FAN_BACK HW pull high/NOT USED
B B
Pin44 I Digital CPPE#_GPU_OVT# HW pull high/NOT USED
Pin24 I Digital EC_PMSUSStat# Platform don't have PM_SUS_SATA#
Pin30 I Digital PCIE_WAKE# HW pull high/NOT USED
Pin23 O Digital PWUREQ# HW pull high/NOT USED
Pin43 I Digital RY/BY# Bios Flsah Ready or Busy,default NC
A A
TOPSTAR TECHNOLOGY
Page Name RESET/NMI/SMI/THERMAL/OV(T)P

C S42C A

Topstar S42C - Rev A

Uploaded by

Copyright:

Available Formats

You might also like

Topstar S42C - Rev A

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Topstar S42C - Rev A

Uploaded by

Copyright:

Available Formats

5 4 3 2 1

Topstar Digital technologies Co.,LTD

7. Power On Sequence Map;

Power drawing by: Power check by:

Manager Sign by:

S42C POWER BLOCK Ver:A

Charger Battery Platform

SIS968 CPU_PWRGD CPU-M

LDO LDO CLK

BATT+ +V5AL +V3.3AL +V1.8 +V1.5S +V1.05S +VCC_CORE +VGA_CORE

GND Power States/AC mode

B S0(Full On) HIGH HIGH HIGH ON ON ON ON B

1 Mini PCIE Card(WLAN & ROBSON)

6 USB Port(on I/O Board)

Schematic modify Item and history:

D 4.PG11 : Change C573 and C574 net from DACAVDD2 to DACAVDD1 D

5.PG15 Add DIMM2 and surrounding Capacitor

6.PG21 : Add clear_cmos point.

7.PG22 : Change R421 value from 127 to 130 Ohm

8.PG26 Power Switch: Add Power Switch and surrounding circuit.

9.PG29 USB: Delete CHK3, and R331 and R329

10.PG30: PCB version from A to B

2007-03-09 Ver C Change List

2.PG30: PCB version from B to C

2007-04-29 Ver D Change List

2. PG30: PCB version from C to D,Reserved R691

3. PG44:Change H3,H7 and H9 footprint from TH_315_112 to TH_315_118

4. PG33:Co-lay PD5 and PD8

2007-05-28 Ver E Change List

2008-09-11 Ver F Change List

2008-09-22 S42C Ver A Change List,主要换了realtek clock和新EC（KB3310B）

3. R24,R26 footprint from 0603 to 0402

5. Reserved SPI BIOS ROM for SIS968, add R170

8. Add reserved SPI ROM

9. Add SATA ODD,NS Q40 and R481,NS PQ58 and R489

10. 添加SATA DVD的Connector

B 11. Delete Co-layout card reader connector. B

12. Delete Co-layout Newcard powerswitch circuit

13.Change minipcie according to minipcie 1.2 spec

14. change EC form 87541 to KB3310B

15. Delete CD_IN circuit.

14 VDDPCI_1 CPUC_L0 54 3 4 CLK_CPU_BCLK# 7

R369 R673 0 R142 ns 2.7K

2N7002 U3 33pF/50V,NPO 33pF/50V,NPO

2. RTM683-910 CLKGEN_MODE R126 10K

C0805 PECLK2/3/5_REQ# R691 10K

DDR_FBIO R457 0 DDR_FBIN Mobile mode default used as CPUSTOPIN#

A 18 FB_IN DDRC3 15 MEM_CHA_CLK#3 15 A

C212 8 23 =HIGH for Mobile mode

CPU TO SB Interface +V1.05S

A5 C7 R0402 H_GTLREF AD26 R26 COMP_CPU0 R320 27.4,1% R0603 +V1.05S

VerC:CPU Socket改为Foxconn的 SIS671DX: 10 pull down,E21 is NC pin

CPU Thermal Sensor

+V1.05S R355 +V1.05S EC SMBUS ADD:1001 100X

Q30 SOT23 LM86CIM

SOT23 R196 SOIC-8 THERM#

R0402 U9 R324 R323