USN : 1 D S 1 E C

Dayananda Sagar College of Engineering

Shavige Malleshwara Hills, Kumaraswamy Layout, Banashankari, Bangalore-560078, Karnataka
Tel : +91 80 26662226 26661104 Extn : 2731 Fax : +90 80 2666 0789
Web - http://www.dayanandasagar.edu Email : hod-ece@dayanandasagar.edu
( An Autonomous Institute Affiliated to VTU, Approved by AICTE & ISO 9001:2008 Certified )
( Accredited by National Assessment & Accreditation Council (NAAC) with 'A' grade )

Department of Electronics & Communication Engineering

Continuous Internal Evaluation – II
Course Name : Digital Electronic Circuits Date : 10/11/2020
Course Code : 19EC3DCDEC Day : Tuesday
Semester : III Timings : 9:30-11:00 AM
Max Marks : 50 M Duration : 1½ Hrs.
M CO &
No. Question Description
ks Levels
Q1 (a) Which logic gate is a basic comparator? 1 CO2
i) NOR ii) NAND iii) XOR iv) XNOR CO3
CO4
(b) A demultiplexer is used to 1
i) perform arithmetic division ii) perform parity checking
iii) steer the data from a single i/p to one of many outputs
iv) select data from several inputs and route it to single output.
(c) Let A and B are the inputs of a subtractor then the output will be ___________. 1
i) A NAND B ii) A OR B iii) A XNOR B iv) A XOR B
(d) How many NOT gates are required for the construction of a 4-to-1 multiplexer? 1
i) 2 ii) 4 iii) 5 iv) 8
(e) How many inputs are required for a priority encoder which can give maximum 1
output value as binary equivalent of 15?
i) 4 ii) 15 iii) 16 iv) 8
10
(f) Number of 2 input multiplexers need to construct a 2 inputs multiplexer is___? 1
i) 32 ii) 9 iii) 129 iv) 1023
(g) The transparent latch is 1
i) SR flip-flop ii) D flip-flop iii) T flip-flop iv) JK flip-flop
(h) The output Qn of a SR-flip flop is 0. Its output does not change when a clock 1
pulse is applied, then the inputs S and R respectively are
i) 0 and X ii) X and 1 iii) 1 and 0 iv) X and 0
(i) For positive level triggered SR Flip Flop if S = 1 0 1 1 0 1 and R = 0 1 1 0 0 0, 1
then the output is
i) 1 0 1 1 1 1 ii) 1 0 0 1 1 1 iii) 1 0 0 1 0 1 iv) 1 0 1 1 0 1
(j) For a flip flop with preset and clear inputs 1
i) preset & clear operations are performed simultaneously
ii) while presetting, clear is disabled iii) while clearing, preset is disabled
iv) both (ii) and (iii) are true
Q2 (a) Suggest a suitable circuit to reduce the propagation delay of the Ripple carry 7 CO2& L3
adder. Also explain its working with the help of logic diagram and expressions.
(b) Implement f(x,y,z) = ΠM (3,4,5,6,7) using 3:8 decoder & NAND gate. 3 CO4& L3
Q3 (a) With neat circuit diagram, explain the working of negative edge triggered D Flip 7 CO3& L3
flop.
(b) Derive the characteristic equation of T Flip flop. 3 CO3& L3
Q4 Implement the Boolean function f(a,b,c,d) = ∑m(0,2,4,5,6,9,10,12,14) using 10 CO2& L3
multiplexers with two 4:1 multiplexer with variables b,d connected to their select
lines in the first level and one 2:1 multiplexer with variable ‘a’ connected to its
select line in the second level.
 OR
Q5 (a) Design a priority encoder for a system with a 3 inputs, the MSB with highest 5 CO4& L4
priority encoding to 10, the middle bit with next priority encoding to 11, while
the LSB with least priority encoding to 01.
(b) Implement Binary Full Subtractor using 2:4 Decoder & OR gate. 5 CO4&L3
Q6 What is Race around condition? Explain how it is eliminated by using Master 10 CO3& L4
Slave JK Flip flop. Analyze your solution with appropriate logic diagrams. Also
draw the waveforms.
OR
Q7 (a) Explain with timing diagram, the working of SR latch as a switch debouncer 5 CO3&L2
(b) Draw the Block diagram, logic diagram (using NAND gates) and truth table of T- 5 CO3&L2
Flip flop