Interrupts in 8085

Interrupts are the signals generated by the external devices to request the microprocessor to perform a task. There
are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
Interrupt are classified into following groups based on their parameter −
 Vector interrupt − In this type of interrupt, the interrupt address is known to the processor. For
example: RST7.5, RST6.5, RST5.5, TRAP.
 Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the processor so,
the interrupt address needs to be sent externally by the device to perform interrupts. For example: INTR.
 Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some instructions
into the program. For example: RST7.5, RST6.5, RST5.5.
 Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by writing some
instructions into the program. For example: TRAP.
 Software interrupt − In this type of interrupt, the programmer has to add the instructions into the
program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0, RST1, RST2, RST3,
RST4, RST5, RST6, and RST7.
 Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP, RST7.5,
RST6.5, RST5.5, INTA.
Note − NTA is not an interrupt, it is used by the microprocessor for sending acknowledgement. TRAP has the
highest priority, then RST7.5 and so on.

Interrupt Service Routine (ISR)

A small program or a routine that when executed, services the corresponding interrupting source is called an ISR.

TRAP

It is a non-maskable interrupt, having the highest priority among all interrupts. Bydefault, it is enabled until it gets
acknowledged. In case of failure, it executes as ISR and sends the data to backup memory. This interrupt transfers
the control to the location 0024H.

RST7.5

It is a maskable interrupt, having the second highest priority among all interrupts. When this interrupt is executed,
the processor saves the content of the PC register into the stack and branches to 003CH address.

RST 6.5

It is a maskable interrupt, having the third highest priority among all interrupts. When this interrupt is executed,
the processor saves the content of the PC register into the stack and branches to 0034H address.

RST 5.5

It is a maskable interrupt. When this interrupt is executed, the processor saves the content of the PC register into
the stack and branches to 002CH address.

INTR

It is a maskable interrupt, having the lowest priority among all interrupts. It can be disabled by resetting the
microprocessor.
When INTR signal goes high, the following events can occur −
 The microprocessor checks the status of INTR signal during the execution of each instruction.
 When the INTR signal is high, then the microprocessor completes its current instruction and sends active
low interrupt acknowledge signal.
 When instructions are received, then the microprocessor saves the address of the next instruction on stack
and executes the received instruction.
8 – BIT ADDITION USING 8085
4100 3A 00 42 LDA 4200H Get first data in A
4103 47 MOV B,A Move A to B
4104 3A 01 42 LDA 4201H Get second data in A
4107 0E 00 MVI C00H Clear C register to account for carry
4109 80 ADD B Get Sum in A reg
410A D2 0E 41 JNC AHEAD If CY=0 go to AHEAD
410D 0C INR C If CY=1 increment C reg
410E 32 02 42 AHEAD STA 4202H Store the sum in memory
4111 79 MOV A,C Move C to A
4112 32 03 42 STA 4203H Store the carry in memory
4115 76 HLT Terminate the program

8 – BIT SUBTRACTION USING 8085

4100 3A 01 42 LDA 4201H Get the subtrahend in B reg
4103 47 MOV B,A Move A to B
4104 3A 00 42 LDA 4200H Get the minuend in A reg
4107 0E 00 MVI C,00H Clear C register to account for sign
4109 90 SUB B Get Difference in A reg
410A D2 11 41 JNC AHEAD If CY=0 go to AHEAD
410D 0C INR C If CY=1 increment C reg
410E 2F CMA Get 2’s complement of difference
410F C6 01 ADI 10H Result in A reg
4111 32 02 42 AHEAD STA 4202H Store the sum in memory
4114 79 MOV A,C Move C to A
4115 32 03 42 STA 4203H Store the sign bit in memory
4118 76 HLT Terminate the program

8 – BIT MULTIPLICATION USING 8085

4100 21 00 42 LXI 4200H Set pointer for data
4103 0E 00 MVI C00H Clear C to account for
overflow
4105 AF XRA A Clear accumulator
4106 46 MOV B,M Get first data in B reg
4107 23 INX H
4108 56 MOV D,M Get second data in D reg
4109 82 REPT ADD D Add D reg to accumulator
410A D2 0E 41 JNC AHEAD
410D 0C INR C If CY=1 increment C reg

410E 05 AHEAD DCR B

410F C2 09 41 JNC REPT Repeat addition until ZF=1
4112 23 INX H
4113 77 MOV M,A Store lower byte of product
in memory
4114 23 INX H
4115 71 MOV M,C Store higher byte of product
in memory
4116 76 HLT Terminate the program
8 – BIT DIVISION USING 8085

4100 3A 01 42 LDA 4201H

4103 47 MOV B,A Get the divisor in B reg
4104 3A 00 42 LDA 4200H Get the dividend in A reg
4107 0E 00 MVI C00H Clear C reg for Quotient
4109 B8 AGAIN CMP B
410A DA 12 41 JC STORE If divisor is less than dividend go to STORE
410D 90 SUB B Subtract divisor from dividend
410E 0C INR C Increment quotient by 1 for each subtraction
410F C3 09 41 JMP AGAIN
4112 32 03 42 STORE STA 4202H Store the remainder in memory
4115 79 MOV A,C
4116 32 02 42 STA 4203H Store the quotient in memory
4119 76 HLT

8086 ARCHITECTURE
8086 Microprocessor is an enhanced version of 8085Microprocessor that was designed by Intel in
1976. It is a 16-bit Microprocessor having 20 address lines and16 data lines that provides up to 1MB
storage. It consists of powerful instruction set, which provides operations like multiplication and
division easily.
It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is
suitable for system having multiple processors and Minimum mode is suitable for system having a
single processor.

Features of 8086
The most prominent features of a 8086 microprocessor are as follows −
 It has an instruction queue, which is capable of storing six instruction bytes from the memory
resulting in faster processing.
 It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and
16-bit external data bus resulting in faster processing.
 It is available in 3 versions based on the frequency of operation −
o 8086 → 5MHz

o 8086-2 → 8MHz

o (c)8086-1 → 10 MHz

 It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves
performance.
 Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue.
 Execute stage executes these instructions.
  It has 256 vectored interrupts.
 It consists of 29,000 transistors.

Comparison between 8085 & 8086 Microprocessor

 Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.
 Address Bus − 8085 has 16-bit address bus while 8086 has 20-bit address bus.
 Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.
 Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an instruction
queue.
 Pipelining − 8085 doesn’t support a pipelined architecture while 8086 supports a pipelined
architecture.
 I/O − 8085 can address 2^8 = 256 I/O's, whereas 8086 can access 2^16 = 65,536 I/O's.
 Cost − The cost of 8085 is low whereas that of 8086 is high.

Architecture of 8086
The following diagram depicts the architecture of a 8086 Microprocessor −