CMOS RF Power Rectifier Design

Author: Law Carlos

Student I.D.: 03614511

Supervisor: Professor K.K.Cheng

Associate Examiner: Professor H.P.Ho

A project report presented to the

Chinese University of Hong Kong
In partial fulfilment of the
Degree of Bachelor of Engineering

Department of Electronic Engineering

The Chinese University of Hong Kong

April, 2006
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Abstract

A set of design criteria for the radio frequency section of a passive RF

identification (RFID) transponders operating at 900MHz industrial, scientific

and medical (ISM) range is derived in this thesis report. Particular focus is put

on the analysis, verification and IC implementation of the voltage multiplier

and the power matching sections. A reader-to-tag read range of around 4m is

achieved with a 4W Effective Isotropic Radiated Power (EIRP) from the base

station. A voltage multiplier sensitivity of –14dBm is achieved with proper

power matching to give at the output of the voltage multiplier an approximate

1.5V and 1.5A to drive the digital section of the RFID passive transponder with

a 10% conversion efficiency. Two IC designs are submitted to

Austriamicrosystems for manufacturing. The first design includes the

complete set of the voltage multiplier circuit. The second has the input

capacitors omitted to see the effect of such an omission to conversion

efficiency and size reduction.

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Acknowledgements

The author would like to thank his supervisor, K.K. Cheng, for his patience

and kind suggestions during the course of the project undertaking, and his

insights in assigning an experienced tutor to assist in the guidance and

troubleshooting of the CADENCE design tool. He would also like to thank F.L.

Wong, W.F. Chung, and C.F. Au Yeung for their invaluable technical support

in the project. H.Y. Yim, C.P. Kong and K.K. Tse have also been very helpful in

the microwave laboratory.

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Contents
Abstract i

Acknowledgements ii

Contents iii

1. Introduction 1

A. Radio Frequency Identification (RFID) 1

i. Brief History 1

ii. Key Features 2

B. Types of RFID Tag 3

i. Passive 3

ii. Semi-passive 5

iii. Active 5

C. Radio Frequency Identification Application 6

D. Overview 7

2. Theory 9

A. Rectifiers 9

B. Voltage Multiplier (VM) 12

i. Traditional Voltage Multipliers 12

ii. CMOS Voltage Multipliers 15

iii. Parameter Analysis 16

C. Matching 28

D. Antenna 32

E. Limiter and Regulator 34

3. Simulation Results 40

A. Rectifiers 40
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i. Comparison 40

ii. Conclusion 45

B. Voltage Multiplier 46

i. Schematic 46

ii. Layout 51

C. Matching 57

D. Proposed Layout 60

4. Discussions 61

A. Comparison of performance 61

B. Design Limitations 62

C. Further Improvement Work 63

5. Conclusions 64

6. References 65
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1. Introduction

A. Radio Frequency Identification (RFID)

Radio Frequency Identification (RFID) is an automatic identification method,

relying on storing and remotely retrieving data using devices called RFID

tags or transponders. An RFID tag is a small object that can be attached to or

incorporated into a product, animal, or person. RFID tags contain silicon

chips and antennas to enable them to receive and respond to radio-frequency

queries from an RFID transceiver. Passive tags require no internal power

source, whereas active tags require a power source. [1]

i. Brief History

In 1945 Léon Theremin invented an espionage tool for the Soviet

government which retransmitted incident radio waves with audio

information. Even though this device was a passive covert listening device,

not an identification tag, it has been attributed as the first known device and

a predecessor to RFID technology. The technology used in RFID has been

around since the early 1920s according to one source. [1]

CMOS RF Power Rectifier Design

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ii. Key Features [2]

• Not line of sight

WID tags do need to be visible to be read / Written.

• Robust

Because they don't need to be visible, they can be encased within rugged

materials protecting them from the environment they are being used in.

This means they can be used in harsh fluid and chemical environments

and rough handling situations.

• Read speed

Tags can be read from significant distances (especially the active variety)

and can also be read very quickly. This is especially useful when the

items needing to be identified are moving quickly for example on a

conveyor.

• Reading multiple items

A number of tagged items can be read at the same time within a RF field.

This cannot be done as easily with "visual" identifiers.

• Security

Because tags cm be enclosed, they are much more difficult to tarnper

CMOS RF Power Rectifier Design

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with, A number of tag types now also come programmed with a unique

identifier (Serial Identification) which is guaranteed to be unique

throughout the world.

• Programmability

Many tags are read / write capable, rather than read only. This means

that information can be written to the tag, perhaps to show that the item

being tagged has gone through a particular process, or that it's condition

or status has changed somehow. Or in some instances to store

information about the tagged items e.g. the results of a test that it has

undergone.

B. Types of RFID Tag

RFID tags can be classified as passive, semi-passive, or active.

i. Passive tag

Passive RFID tags have no internal power supply. The minute

electrical current induced in the antenna by the incoming radio

frequency signal provides just enough power for the CMOS

integrated circuit (IC) in the tag to power up and transmit a

CMOS RF Power Rectifier Design

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response. Most passive tags signal by backscattering the carrier

signal from the reader. This means that the aerial (antenna) has to

be designed to both collect power from the incoming signal and also

to transmit the outbound backscatter signal. The response of a

passive RFID tag is not just an ID number (GUID); the tag chip can

contain nonvolatile EEPROM for storing data. Lack of an onboard

power supply means that the device can be quite small:

commercially available products exist that can be embedded under

the skin. Passive tags have practical read distances ranging from

about 2 mm (ISO 14443) up to a few meters (EPC and ISO 18000-6)

depending on the chosen radio frequency and antenna design/size.

Due to their simplicity in design they are also suitable for

manufacture with a printing process for the antennae. Passive RFID

tags do not require batteries, and can be much smaller and have an

unlimited life span. Because passive tags are cheaper to

manufacture and have no battery, the majority of RFID tags in

existence are of the passive variety. [1]

CMOS RF Power Rectifier Design

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ii. Semi-passive Tag

Semi-passive RFID tags are very similar to passive tags except for

the addition of a small battery. This battery allows the tag IC to be

constantly powered, which removes the need for the aerial to be

designed to collect power from the incoming signal. Aerials can

therefore be optimized for the backscattering signal. Semi-passive

RFID tags are faster in response and therefore stronger in reading

ratio compared to passive tags.

iii. Active Tag

Unlike passive and semi-passive RFID tags, active RFID tags have

their own internal power source which is used to power any ICs and

generate the outgoing signal. They may have longer range and

larger memories than passive tags, as well as the ability to store

additional information sent by the transceiver. At present, the

smallest active tags are about the size of a coin. Many active tags

have practical ranges of tens of meters, and a battery life of up to 5

years.

CMOS RF Power Rectifier Design

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C. Radio Frequency Identification Application

• RFID are used as replacement of barcode tags

• High-frequency RFID tags are used in library book or bookstore

tracking, pallet tracking, building access control, airline baggage

tracking, and apparel and pharmaceutical item tracking. High-frequency

tags are widely used in identification badges, replacing earlier magnetic

stripe cards. These badges need only be held within a certain distance of

the reader to authenticate the holder.

• Systems for prepaying for unlimited public transport have been devised,

making use of RFID technology. The design is embedded in a

credit-card-like pass, that when scanned reveals details of whether the

pass is valid, and for how long the pass will remain valid.

• UHF RFID tags are commonly used commercially in case, pallet, and

shipping container tracking, and truck and trailer tracking in shipping

yards.

• Microwave RFID tags are used in long-range access control for vehicles.

• RFID tags are used for electronic toll collection at toll booths. The tags

are read remotely as vehicles pass through the booths, and tag

CMOS RF Power Rectifier Design

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information is used to debit the toll from a prepaid account. The system

helps to speed traffic through toll plazas as it records the date, time, and

billing data for the RFID vehicle tag.

• During the 2006 NASCAR racing season, the Goodyear Tire and Rubber

Company began testing RFID tags provided by Advanced ID

Corporation embedded in racing tires. It is expected that these tags will

be commercially available by the end of 2006.

• A number of ski resorts, particularly in the French Alps, have adopted

RFID tags to provide skiers hands-free access to the lift system.

E. Overview

The architecture of a passive microwave RFID transponder is shown in Fig. 0.

The coupling element is an antenna, which typically is a dipole or a patch

antenna. A voltage multiplier converts the input alternating voltage into a dc

voltage, which is used by a series voltage regulator to provide the regulated

voltage required for the correct operation of the transponder. The voltage

multiplier is matched with the antenna in order to ensure the maximum

power transfer from the transponder’s antenna to the input of the voltage

CMOS RF Power Rectifier Design

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multiplier. A backscatter modulator is used to modulate the impedance seen

by the transponder’s antenna, when transmitting. The RF section is then

connected to the digital section, which typically is a very simple

microprocessor or a finite-state machine able to manage the communication

protocol.

Fig. 0 A Passive transponder architecture [7]

The objective of this thesis is to design a RF power-rectifying unit that suits

in the application of a RFID passive transponder and to maximize the

operating read range. Special attention is given to the voltage multiplier

design and the matching network. The rectifier is expected to give 1.5V and

1.5uA to the digital section with reasonable efficiency as shown in Fig. 0.

CMOS RF Power Rectifier Design

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2. Theory
A. Rectifier

Rectification is a process whereby alternating current (AC) is converted

into direct current (DC). Rectifiers are devices that perform this duty.

Almost all rectifiers comprise a number of diodes in a specific

arrangement for more efficiently converting AC to DC than is possible

with just a single diode. Rectification is commonly performed by

semiconductor diodes. Rectifiers can have various configurations and

are chosen depending on applications.

Half-wave Rectifiers

In a half-wave rectifier (Fig. 9), either the positive or negative half of the

AC wave is passed easily while the other half is blocked, depending on

the polarity of the rectifier. This configuration is adopted because of

simplicity of circuits.

Full-wave Rectifiers

Full-wave rectification converts both polarities of the input waveform to

CMOS RF Power Rectifier Design

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DC, and is more efficient. However, more diodes are needed in this

configuration. A full wave rectifier (Fig.11) converts the whole of the

input waveform to one of constant polarity (positive or negative) at its

output by reversing the negative (or positive) portions of the alternating

current waveform. The positive (negative) portions thus combine with

the reversed negative (positive) portions to produce an entirely positive

(negative) voltage/current waveform.

Schottky Rectifiers

Schottky rectifiers have been used for over 25 years in the power supply

industry. The primary advantages are very low forward voltage drop and

switching speeds that approach zero time making them ideal for output

stages of switching power supplies. This latter feature has also

stimulated their additional use in very high frequency applications

including very low power involving signal and switching diode

requirements of less than 100 picoseconds. These require small Schottky

devices with low capacitance.

CMOS RF Power Rectifier Design

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What little reverse recovery time they may exhibit is primarily dictated

by their capacitance rather than minority carrier recombination as in

conventional pn junction rectifiers. This characteristic provides very

little reverse current overshoot when switching the Schottky from the

forward conducting mode to the reverse blocking state. These make

schottky rectifiers a very attractive choice for low parasitic switching

losses.

Design considerations with Schottky devices are limited in some

applications compared to pn junction rectifiers because their reverse

leakage currents are many times higher. Also Schottky rectifiers have

maximum rated junction temperatures typically in the range of 125°C to

175°C, compared to the typical 200°C for conventional pn junctions

which further influences leakage current behavior. For some

applications, Schottky devices are limited in available reverse blocking

voltage ratings compared to conventional pn junction rectifiers.

The Schottky rectifier properties described above are primarily

CMOS RF Power Rectifier Design

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determined by the metal energy barrier height of material deposited on

the silicon by the manufacturer. A metal with a low energy barrier height

will minimize forward voltage, but will also be restricted in its high

temperature operating capability and have very high reverse leakage

currents. A high barrier metal height selection will minimize

temperature and leakage current sensitivity but will increase the

forward voltage. [3]

B. Voltage Multiplier

i. Traditional Voltage Multipliers

Traditional voltage multipliers make use of schottky diodes that

have low series resistance and allow for a high conversion efficiency

of the received RF input signal energy to dc supply voltage.

CMOS RF Power Rectifier Design

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Fig. 1 Schematic of the voltage multiplier converting RF input

signal to dc supply voltage

Schottky diodes have advantages of fast switching speed and low

forward voltage drop. Due to these excellent high frequency

performances, they have been widely used in power detection and

microwave network circuit. Schottky diodes are often fabricated by

depositing metals on n-type or p-type semiconductor materials such

as GaAs and SiC. The properties of forward-biased Schottky diodes

are determined by majority carrier phenomena, while minority

carriers primarily determine those properties for p-n diodes. In

order to increase high frequency performance and decrease the

CMOS RF Power Rectifier Design

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supply voltage of IC, integrating the Schottky diode into modern IC

is very important. But the processes can integrate Schottky diode

are often not commercially available and don’t have the capability

of integrating CMOS circuits monolithically with them.

In [5], a voltage multiplier using a self-designed schottky diode

model with a multiplier stage of 5 obtains a conversion efficiency of

9.6% in the operating frequency of 915MHz. This is not a fair nor

complete comparison to the design listed in this thesis but provides,

to some extend, a reference. A simulation of the schottky diode

voltage multiplier is not available in this thesis because there is no

dedicated industry standard compact Model to be used for circuit

simulation.

The design parameters of the voltage multiplier are a tradeoff

between power efficiency, useful impedance, and operating point

(load). Optimization parameters include the number of stages, the

size of Schottky diodes, and the size of coupling capacitors.

CMOS RF Power Rectifier Design

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To get a good efficiency, it is very important to have Schottky diodes

with large saturation current (resulting in low forward voltage drop)

and a low junction capacitance, as well as a small series resistance

and small parasitic capacitance to substrate. Larger Schottky diodes

have a larger saturation current and a smaller series resistance, but

also larger junction and substrate capacitances, which then may

dominate the power losses, so that an optimum size of the Schottky

diode has to be found. Similarly, for the coupling capacitors, it is

also important to have small series resistance and parasitic

capacitance to substrate.

ii. CMOS Voltage Multipliers

Schottky diodes are generally used for its low conduction resistance

and low junction capacitance. However, the particularity of

manufacturing processes for Schottky diodes and the inconsistency

in quality between different product batches often make the

integration of Schottky voltage multiplier incompatible with

CMOS RF Power Rectifier Design

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standard CMOS circuits and thus limit its applications. [6]

Therefore, instead of using expensive Schottky diodes, voltage

multipliers are replaced by MOS-connected diodes with standard

CMOS technologies as shown in Fig. 2 below.

Fig. 2 Schematic of the simplified voltage multiplier

iii. Parameter Analysis

In a voltage multiplier, there are several parameters that can be

optimized and designed for a tradeoff of high conversion efficiency

and output voltage:

• Number of multiplier stage

CMOS RF Power Rectifier Design

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By analyzing a single unit voltage multiplying cell, as shown in Fig.

3 below, multiplying capacitor Cn-1 and Cn can look like a pair of DC

voltage sources; Cc is a coupling capacitor that combines input

voltage Vi and Vn-1, voltage drop on Cn-1, to provide voltage for the

next multiplier. Suppose Cdn-1 is the voltage drop on NMOS FET

Mn-1, Vdn for Mn and Vc is the DC voltage at point C, under

steady-state condition,

Vc = Vn-1 – Vdn-1, Vc = Vn + Vdn (1)

If W/L of 2 MOSFETs is identical, we have

Vdn = Vdn-1, ∴Vc = (Vn + Vn-1)/2 (2)

The actual input signal for Mn is Vc + Vi. Assume ΔV is the unit

voltage increment, then

ΔV = Vi – Vd, ∴(Vn + Vn-1)/2 +ΔV = Vn, Vn = Vn-1 + 2ΔV (3)

If redefining a pair of MOSFET and capacitor as new unit voltage

multiplying cell, the stage number becomes 2, such that

∴Vn = Vn-2 + 2ΔV (4)

where n = 2k+1, k is the ordinal number of initial unit voltage

multiplying cells and equal to 1,2,3… With the same aspect ratio for

CMOS RF Power Rectifier Design

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all the MOSFETs in the charge pump, everyΔV would be identical.

Further iterating the formula, we get

Vn = Vn-4 + 4ΔV = Vn-6 + 6ΔV (5)

Finally, V = nΔV = n(Vi - Vd) where n is the number of multiplying

stages. In RFID applications, due to the lack of input power, output

voltage and conversion efficiency of the voltage multiplier are hence

2 primary performance parameters. [6]

Fig. 3 Single unit voltage multiplying cell

• Coupling capacitor

In order ensure a small ripple in the output voltage Vout, the

coupling capacitors have to be dimensioned so that their time

constant is much larger than the period of the input signal,

CMOS RF Power Rectifier Design

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that is,

Iout/(2πCVout) << fo (6)

where Iout is the DC output current. In this way, the voltage

across C capacitors and the output voltage can be considered as

a DC voltage. As a consequence, in the high frequency analysis,

it is possible to consider C capacitors as short-circuits and

therefore all diodes appear to lie directly in parallel or

anti-parallel to the input. In this situation, the input RF voltage

entirely drops across the diodes. In the dc analysis, capacitors

can be considered as open circuits so that we have 2N identical

diodes in series with the output. Indeed, since the dc power

required by radio-frequency identification (RFID) passive

transponders is quite low (in the order of a few microwatts),

the dc output current of the voltage multiplier is very small,

leading to a negligible effect of the series resistance of the

diodes. [7]

• Aspect ratio of the transistor connected diodes

CMOS RF Power Rectifier Design

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The transistors employed in the voltage multiplier plays a

significant role in rectification like the traditional Schottky

diodes configuration. The aspect ratio of the transistor that

describes the ratio of the width to the length of the active

region determines the amount of current that can go through

the such-connected diode. In a typical voltage multiplier, the

current through is in the order of several microamperes. The

amount of current that goes through each transistor and in

turn the size or aspect ratio of the transistor tells how serious

the parasitic effects has to the whole voltage multiplier. For a

transistor-connected diode with a larger aspect ratio, it would

have two effects: one is it leads to a higher conversion

efficiency when the current is still small and the second is a

degradation in conversion efficiency due to the increase power

dissipated through the diode leakage in the transistors. This

leakage is related to the size of the active region. In conclusion,

an optimization in the transistor aspect ratio can be derived to

maximize the conversion efficiency by simulations.

CMOS RF Power Rectifier Design

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• Antenna impedance

The antenna impedance usually has a standard value of 50Ω

and sometimes a value of 75Ω optimized for performance.

However, in the case of a voltage multiplier, the input

impedance looking into the voltage multiplier has an

impedance of more than 300Ω and maybe up to 1000Ω

because of the coupling capacitors and gate of the transistors. A

matching network is therefore essential to match the antenna

impedance to that of the voltage multiplier. In this case, more

freedom is given to design the antenna and design the

matching circuit in order to achieve a given impedance level.

Finally, it is the application that defines the constraints for the

antenna and the matching circuit design.

• Threshold Voltage

As described in the previous part, the output voltage and the

number of stages are related by the equation:

CMOS RF Power Rectifier Design

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V = nΔV = n(Vi - Vd)

where n is the number of multiplying stages.

With a constant input signal power, the most obvious way to

increase output voltage is to increase the number of

multiplying stages and to minimize the voltage drop across the

diodes Vd. However, because the increase of stage number is

subject to degradation of power dissipation and conversion

efficiency, [6] the only feasible way is to lower the voltage drop

Vd on every transistor.

Due to the short connection between the gate and drain, all

transistors work in the saturation region:

Vd = Vds = 2Ids β + Vth (7)

where β = µnCox W L . In a fixed output current Ids, the bigger

W/L and the smaller Vth are, the lower Vd is. As a result, in

order to obtain a bigger output, lower Vth MOSFET and a larger

aspect ratio should be adopted. However, when the aspect ratio

increases, as mentioned in the above subsection, the parasitic

CMOS RF Power Rectifier Design

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lost also increases and an optimized value has to be located.

Vth is a process dependent parameter and is not controllable at

the design process.

Then, we define several performance parameters:

• Output voltage

The output voltage is a significant consideration for the choice

of the parameters to optimize, as mentioned above. A

minimum output voltage has to be satisfied at the digital

section of the passive transponder to carry out the basic

operations to identify and communicate between the

transponder and the reader. A typical transponder operates

with 1.5μA at 1.5V supply voltage in all nodes. In other words,

we can consider an output load of 1MΩ and a 1.5V output

voltage.

• Input sensitivity

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Given the output requirement and a fixed conversion efficiency,

the minimum input power required for the operation of the

passive transponder can be calculated. This is the sensitivity of

the voltage multiplier. With this value, we can obtain the

maximum read range from the reader to the tag in a RFID

system.

• Read Range

Read range is an important characteristic of the RFID tag. It is

the maximum distance from which the tag can be detected. One

limitation on the range is the maximum distance from which

the tag receives just enough power to turn on and scatter back.

Another limitation is the maximum distance from which the

reader can detect this scattered signal. The read range is the

smaller of the two distances (typically, the first one since RFID

reader sensitivity is usually high).

The theoretical read range depends on the power reflection

CMOS RF Power Rectifier Design

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coefficient and can be calculated using the Friis free-space

formula as

λ Pt Gt Gr (1− | s | 2 )
rmax = (8)
4π Pth

where λ is the wavelength, Pt is the power transmitted by the

RFID reader, Gt is the gain of the transmitting antenna (PtGt is

EIRP, equivalent isotropic radiated power), Gr is the gain of

the receiving tag antenna, and Pth is the minimum threshold

power necessary to power up the chip. Typically Pt, Gt, Gr and

Pth are slow varying, and |s|2 is the power reflection coefficient

that can be easily determined from the Smith Chart as a square

of distance (measured as a radius of the circle radius) between

the origin and the mapped impedance point. [9]

For a 4W RIRP and assuming a good power matching of the

antenna to the voltage multiplier and a 0dB gain at the tag

antenna, the read range can be simplified to:

53.05e − 3
rmax = (9)
Pth

CMOS RF Power Rectifier Design

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where Pth is the minimum threshold power necessary to power

up the chip.

Fig. 4 A plot of the relation between the read range and input

power based on equation (9)

• Conversion efficiency [8]

The conversion efficiency is defined as the ratio of the DC

output power to the difference of the incident and reflected RF

power as collected from the antenna:

DC Output Power
η0 = (10)
Incident RF Power - Reflected RF Power

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Conversion efficiency is an important parameter in a passive

transponder because power received at the antenna is limited.

A higher conversion efficiency means a smaller power

dissipated across the diodes and a higher output voltage at the

given operating power. If we consider a fixed output power at

the voltage multiplier output, a higher conversion efficiency

means a lower power required in the voltage multiplier input.

This in turn means a higher sensitivity of the passive

transponder.

• Global efficiency [8]

The global rectifier efficiency is defined as the ratio of the DC

output power to the incident radio frequency (RF) power:

DC Output Power
ηo = (11)
Incident RF Power

Global efficiency also provides a good measurement to the

performance of a rectifying unit in a passive transponder. It

CMOS RF Power Rectifier Design

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provides a more thorough knowledge of the circuit

performance by considering also the power-matching network

that lies between the tag antenna and the rectifying unit.

C. Matching

Since the power at the transponder antenna varies with the distance

between the reader and the transponder, power matching will be

pursued in the condition of minimum power available at the antenna

that still ensures correct operation of the transponder. Indeed, the

transponder continues to work correctly when the power at the antenna

increases even if power matching is lost. [7] It is, however, important to

ensure the power available at the voltage multiplier end is sufficient to

turn on the gate transistors. In other words, the antenna voltage level is

scaled for a constant received power and allows to reach the rectifier

sensitivity with less power.

Since in this thesis, the focus is on the design and optimization of the

voltage multiplier and matching network, most of the simulation and

CMOS RF Power Rectifier Design

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the design work assume an antenna characteristic impedance of 50Ω.

This is based on the fact that most antennas have a standard 50Ω

characteristic impedance determined by experiments. However, for a

general voltage multiplier that has at its inputs capacitors connected in

series, they usually carry large input impedance. Therefore, the

transponder input impedance is mainly influenced by the rectifier. [7]

The detector, demodulators and other digital sections have little

contribution here. The transponder input impedance is composed of an

imaginary part due to the parasitic capacitances and a real part that

depends on the output current consumption.

The matching network considered in this design is mainly lumped

discrete elements to tackle the process variation of the IC

manufacturing.

A very useful impedance matching tool for any microwave engineer is

the Smith chart. It was developed by Smith in the 1930s [9] and is the

most widely known graphical impedance chart. The Smith chart is

CMOS RF Power Rectifier Design

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typically normalized to a real impedance and can be used to find a

lossless transmission-line section for desired impedance matching

between two complex impedances.

In lumped circuit matching, inductors and capacitors can be arranged in

parallel and or in series to move the input impedance point as located in

a Smith Chart freely to the center point, which is the match point.

z1 = 2 + j z2 = 1.5 -j2 z3 = j4 z4 = 3

z5 = 8 z6 = 0 z7 = 1 z8 = 3.68 -j18S

CMOS RF Power Rectifier Design

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Fig.5 Sample of plot points in a Smith Chart (z7 is a match point)

Fig.6 Schematic of 8 possible matching network configurations

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According to the different designs, the input impedance varies with the

aspect ratio of the transistors, the capacitor values, the multiplying

stages and the output load. In each case, a new matching network has to

be included for power matching. Resistors are not included to avoid

power dissipation in the matching network. Inductors connected in

series are also avoided as much as possible to prevent the possible

power dissipation while considering a wider band of the input 900MHz

frequency range.

D. Antenna

Antenna is the most front-end part of a passive transponder. This is the

crucial part where RF power transmitted from the reader is collected at

the passive tag. The amount of power distributed into the voltage

multiplier section for power rectification is directly related to the

antenna characteristic impedance and that of the multiplier. Matching is

usually necessary because of the impedance mismatch. A good matching

network minimizes the power reflection to the antenna and thus

improves global efficiency.

CMOS RF Power Rectifier Design

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There are several types of antennas that can be used with a

high-frequency transponder. The choice is closely related to the target

application [8]. Patch antennas are well suited for metallic objects since

it is possible to make use of their bodies as a ground plane. Inverted-F

antennas are also mountable on such objects [8]. Other types of

materials, e.g., wood, cardboard, etc. also allow differential antennas.

These antennas offer the advantages of higher radiation resistance

compared to single ended versions, and of less capacitive losses.

A higher antenna radiation resistance is sometimes preferable for easier

match to the rectifier that possesses high input impedance. An antenna

impedance level of 300Ω is suggested in [8], however, this is out of

scope of the discussion in this thesis. Finally, the antenna design is given

a larger room for optimization with a proper consideration of a good

power-matching network.

CMOS RF Power Rectifier Design

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E. Limiter and Regulator

Due to the variance between Vi, RF input signals with different power

levels, modulation indexes and modes will generate quite different and

even unstable output voltages through the charge pump, which is not

desired for a steady DC supply in RFID transponder. For stabilizing

output voltage, Fig. 7 presents a low power regulator that includes a

diode regulator, a voltage reference and a series regulator. [6]

The diode regulator simply utilizes four series diodes to provide an

elementary regulating strategy, which only confines large output swing

to a comparatively low but still apparent and unfavorable degree. For

two following portions, such pre-regulation is necessary and makes

them properly work in an appropriate and acceptable supply swing

range to produce more precise and stable output.

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Fig.7 Schematic of the low-power regulator

To reduce power dissipation, the required high reference voltage, for

example 1.5V, is directly generated through a β self-biasing voltage

reference instead of the conventional way to accurately amplify a

pre-generated low reference voltage. As shown in Fig. 8, M5—M10 build

up triple cascode connection to increase output resistance and all

operate in the subthreshold region for reduced power consumption. In

subthreshold region, the drain-source current approximately is:

W q (Vgs −Vth ) nKT

I sds = I do e (12)
L

kT 2 1.8
where I do = µ n C ox ( )
q e

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If the W/L of M9 is made Q times larger than that of M10 and both have

the same L, Vgs of M9 and M10 can be rewritten in terms of the current

Isds as:

kT I L
V gs10 = n ln[ sds ] + Vth (13)
q IdoW

and

kT I L
V gs 9 = n ln[ sds ] + Vth (14)
q I do QW

In addition, we have

Vgs10 = Vgs9 + IRr (15)

Solving for the subthreshold current Isds using equation (12), (13), (14),

we have

nkT
I sds = ln Q (16)
qRr

which is independent of DC supply source and is much smaller, only in

the order of magnitude of several dozen nA, than the current operating

in typical saturation region. With such a constant and small current, the

voltage on the drain of M6 can be also stable and independent of power

supply. Moreover, for minimizing the RF input power, since such

reference is expected to work under a power supply as low as possible,

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the current mirror load M3—M4 utilize the low Vth PMOS FETs to

reduce requisite Vds voltage drops as well.

Series regulator simply utilizes a differential amplifier and a negative

feedback NMOS FET to make the output fixed on the given reference

voltage. In order to achieve low-dropout regulation and ensure that M16

operates in saturation region, the native transistor with nearly zero Vth

same as the one in basic charge pump and greatly large W/L are

employed. [6]

Another method is by adding a limiter at the output of the rectifier. Such

a voltage regulation has the advantage of simplicity. The disadvantages

are that for high-received power, i.e., for low communication distances,

the transistor pair will drive a quite high current that will dramatically

reduce the input impedance seen by the antenna and thus degrades the

matching performance.

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Fig.8 Schematic of a limiter

We can derive,

I ds R l + Vds = Vout (17)

and,

Vds + Vth = Vout (18)

so,

I ds Rl = Vth (19)

µ n C ox W
where I ds = (V gs − Vth ) is the drain-source current in saturation,
2 L

Vth is the threshold voltage of the MOSFETs, Vds is the drain-source

voltage, and Rl is the limiter resistor.

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From equation (19), Ids, which is dependent on the gate-source voltage,

is made a constant such that the output voltage after the limiter is

maintained a more steady voltage level. The limiter resistor value is

adjusted according to the expected voltage level at the output and in the

previous voltage multiplier stage, which is also dependent on the

number of stages implemented.

Since the thesis focuses only in the design and optimization of a voltage

multiplier and the matching network, the part of a regulator or a limiter

is not implemented or discussed in detail and hence, it is out of scope of

this thesis.

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3. Simulation Results
A. Rectifiers

i. A comparison

Different rectifier configurations as suggested in [4] are compared

from simulation under the following conditions:

• Operating frequency: 900MHz

• Characteristic impedance: 50Ω

• Input Voltage: 1V

• Output load: 50Ω

• Capacitor: 100pF

• Diode model: PRIMLIB welldiode

Fig.9 Schematic of a half-wave rectifier (configuration A)

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Fig. 10 Schematic of a full-wave rectifier (configuration B)

Fig. 11 Schematic of a full-wave rectifier (configuration C)

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Fig. 12 Schematic of a full-wave rectifier (configuration D)

Fig. 13 Schematic of a full-wave rectifier (configuration E)

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Fig. 14 Output voltage of a half-wave rectifier (configuration A)

Fig.15 Output voltage of a full-wave rectifier (configuration B)

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Fig.16 Output voltage of a full-wave rectifier (configuration C)

Fig.17 Output voltage of a full-wave rectifier (configuration D)

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Fig.18 Output voltage of a full-wave rectifier (configuration E)

ii. Conclusion

A half wave rectifier with the simplest configuration as shown in fig.

9 is adopted in the design to operate in the interested frequency. By

reducing the number of diodes employed in the design, the voltage

drop across them are reduced, which means a higher voltage at the

output. However, the desired output voltage minimum for the

operation of the digital section in the required passive transponder

cannot be achieved with this simple half-wave rectifier. Hence, a

voltage multiplier is considered.

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B. Voltage Multiplier

i. Schematic

The RF power rectifier under investigation in this thesis focuses on

the voltage multiplier design and the power-matching network that

is essential for effective rectification. Fig. 19 shows a schematic of

the circuit used for simulation. It consists of 2 stages.

The input port resembles the effect of an antenna in a passive

transponder. The characteristic impedance is set at 50Ω. Following

it is a LC matching network, as described in the theory section, to

match the antenna impedance to that of the voltage multiplier. Next

to it is the voltage multiplier that employs 2 stages and follows a

typical half-wave rectifier configuration (configuration A). The

output port is a 1MΩ load to resemble the influence of a typical

digital section in a RFID tag. The 1MΩ load is set to simulate the

effect of a 1.5uA current drive at a 1.5V output voltage. This load

also influences the input-matching network, and therefore, affects

the conversion efficiency.

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Fig. 19 Schematic of a 2-stage voltage multiplier with appropriate

matching network applied for simulation

The voltage multiplier employs a 2-stage unit voltage-multiplying

cell as a balance after the comparison of the conversion efficiency

and the output voltage for different number of multiplying stages,

as shown in Fig.20 and Fig.21.

The following simulations are based on some model parameters

provided from the technology provider and are directly available in

the simulator library.

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Fig. 20 Plot of conversion efficiency against input power with different number of stages

Fig.21 Plot of output voltage against input power with different number of stages

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The values of the transistor aspect ratio are verified in simulations

from a range of 10um to 100um. Since we employ a 0.35um

technology, the aspect ratio is simply a variation of the width. Again,

both conversion efficiency and output voltage are taken to compare

the performance. It agrees with the theory that says while balancing

the tradeoff between three fundamental factors: the reverse current,

the direct current and the capacitance behavior, [10] increasing the

transistor width increases the forward current. However, the

reverse current and the parasitic capacitances increase more rapidly.

Based on the simulation obtained in Fig.22 and Fig.23, a transistor

width of 20um to 90um is a reasonable range for further simulation

and design considerations.

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Fig. 22 Plot of conversion efficiency against the transistor aspect

ratio

Fig. 23 Plot of output voltage against the transistor aspect ratio

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ii. Layout

Based on the schematic simulation, the voltage multiplier schematic

is converted to layout, which is done in CADENCE. After proper

design rule check and extraction, post layout simulation is carried

out to verify the schematic design.

Fig.24 The conversion efficiency against various input power of a

layout extracted simulation

The 2 basic parameters are plotted again. The conversion efficiency

reaches a maximum of more than 30% at around 8dBm input

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power, as shown in Fig. 24. The efficiency begin to drop at higher

input power because the power matching network is designed for

the farthest read range and hence, to ensure the correct

functionality of the digital section in a passive transponder. In other

words, the power matching aims at maximizing the read range and

correct tag functionality with best sensitivity achievable at the

rectifier. When the transponder is closer to the reader, input power

available at the transponder antenna increases, and matching

deteriorates. This results in more reflection at the rectifier. The

conversion efficiency thus decreases. However, it is still in an

operable region. By comparing the output voltage, as shown in Fig.

25, considering a minimum digital section voltage requirement of

1.5V, the rectifier can reach a sensitivity of –16dBm.

The coupling capacitance is further compared in the layout level.

Fig. 26 and Fig. 27 shows that while parasitic effects are taking into

consideration in the capacitors, a 100fF capacitance is the best.

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Fig.25 The output voltage against various input power of a layout extracted simulation

Fig. 26 The conversion efficiency against various coupling capacitor values of a layout extracted

simulation

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Fig. 27 The output voltage against coupling capacitor values of a layout extracted simulation

Fig. 28 The conversion efficiency against the transistor aspect ratio of a layout extracted

simulation

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Fig.29 The output voltage against the transistor aspect ratio of a

layout extracted simulation

Based on (6),

Iout/(2πCVout) << fo (6)

The coupling capacitor has to be much larger than the time constant

of the circuit. The operating frequency is 900MHz. An output

voltage of 1.5V and an output current of 1.5uA have to be achieved.

Hence, the coupling capacitor has to be much larger than 0.1768fF.

It is verified by simulation in the layout level that 100fF is already

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good enough to achieve the desired result. It is predicted that an

even smaller capacitor value could give an even better result in

terms of conversion efficiency and output voltage after the

consideration of parasitic losses. The larger the capacitors, the

larger the losses are. This is less obvious in a general cap model

The parasitic effect is also true for the transistor aspect ratio. A

smaller transistor will suffer less from the parasitic effects that is

proportional to the size of the active region in the process. Fig. 28

and Fig. 29 verifies the prediction.

Fig. 30 Transient response of an extracted layout

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Fig. 30 is a transient response of the extracted layout. The rectifier

requires a 200ns to reach a steady state. It employs a transistor

aspect ratio of 5um/0.35um and coupling capacitors of 100fF with

proper LC matching. An output load of 1MΩ is assumed.

C. Matching

Fig. 31 Smith Chart showing the S11 before and after matching

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Fig. 32 Smith Chart showing a matched sweep of frequency band

(899MHz to 901MHz)

Fig. 31 shows the S11 of the voltage multiplier before and after

matching. Fig. 32 shows the amount of mismatch due to a small

band of frequency deviation from 899MHz to 901MHz. The effect is

negligible to the conversion efficiency and so the read range given

by (8).

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Fig.33 Comparison of conversion efficiency between a voltage

multiplier with and without matching

Fig.34 Comparison of output voltage between a voltage multiplier

with and without matching

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The significance of mismatch is, however, quite serious if we

compare two voltage multipliers with the same configuration and

design with and without a proper matching network. Fig. 33 and Fig.

34 shows such effect to the 2 parameters that we continuously

analyze. It is obvious that a proper matching is required given the

S11 of the unmatched voltage multiplier.

D. The Proposed Layout

Fig.35a) The complete proposed layout b) Layout without the input capacitors

The proposed layout is shown in Fig. 35a and b. The complete voltage

multiplier has a size of 0.8mmx0.69mm. The other one does not have a

couple of input coupling capacitors and has a size of 0.48mmx0.69mm.

The difference is to observe the effect of such parasitics in a real IC.

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5.Discussions
A. Comparison of performance

The design of a voltage multiplier for the RFID passive tag application has

been a new topic for investigation in review to the RFID boom after the

Wal-mart effect. Recently, IEEE journals of similar designs are available for

comparison.

This Work [8] [6] [11]

Operating Frequency 900MHz 2.45GHz 900MHz 869MHz

Sensitivity -14dBm -25.7dBm -19.25dBm -19dBm

Vout 1.679V 1V 1.5V 1.5V

Iout 1.679uA 1uA 1.5uA 0.95uA

Output Power 2.82uW 1uW 2.25uW 1.425uW

Conversion Efficiency 9.644% 37% 18.56% 14.5%

Antenna Impedance 50Ω 300Ω / /

Read Range 8.41m 12m / /

Table 1. A comparison of various design of power rectifier

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B. Design Limitations

The current voltage multiplier is designed for RF power rectification in a

RFID passive transponder application. However, to simplify the analysis and

design of the circuit, only the parameters regarding the voltage multiplier

and the matching network are considered for analysis. The parts of the

antenna, modulation and detection are not included. These parts in a passive

RFID transponder bear also some effect to the overall conversion efficiency

and read range of the RFID system.

Besides, most of the simulations are based on parameter models from the

technology library. These libraries have parameter limitations that restrict

the freedom of the design. Applying these models out of the given boundary

results in unexpected and unreliable performance outcomes that are not

guaranteed by the technology process.

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C. Further Improvement Work

A more thorough design can be obtained by involving the other parts in a

passive transponder, including the antenna design, and the modulators and

detectors. More detail adjustment and optimization work can be carried out

in the layout procedure.

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6.Conclusions

A set of design criteria for the radio frequency section of a passive RF

identification (RFID) transponders operating at 900MHz industrial, scientific

and medical (ISM) range is derived in this thesis report. Particular focus is put on

the analysis, verification and IC implementation of the voltage multiplier and the

power matching sections. A reader-to-tag read range of around 4m is achieved

with a 4W Effective Isotropic Radiated Power (EIRP) from the base station. A

voltage multiplier sensitivity of –14dBm is achieved with proper power matching

to give at the output of the voltage multiplier an approximate 1.5V and 1.5A to

drive the digital section of the RFID passive transponder with a 10% conversion

efficiency. Two IC designs are submitted to AMS for manufacturing. The first

design includes the complete set of the voltage multiplier circuit. The second has

the input capacitors omitted to see the effect of such an omission to conversion

efficiency and size reduction.

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7.References
[1] http://en.wikipedia.org/wiki/RFID

[2] Nath, B.; Reynolds, F.; Want, R., RFID Technology and Applications,

Pervasive Computing, IEEE, Volume: 5 Issue: 1 Jan.-March 2006

[3] Kent Walters, Bob Werner, MicroNote Series 401

[4] Maysam Ghovanloo and Khalil Najafi, “Fully integrated wideband

high-current rectifiers for inductively powered devices”, IEEE J. Solid-State

circuits, vol.38, no. 11, Nov., 2004

[5] Qiang Li, Yifeng Han, Hao Min and Feng Zhou, ‘’Fabrication and Modelling

of Schottky Diode Integrated in Standard CMOS Process”

[6] Yuan Yao, Yin Shi, and Foster F. Dai, “A Novel Low-Power

Input-Independent MOS AC/DC Charge Pump”, 2005

[7] Giuseppe De Vita and Giuseppe Iannaccone, “Design Criteria for the RF

Section of UHF and Microwave Passive RFID Transponders”, IEEE Trans.

On Microwave Theory and Tech., Vol.53, No.9, Sept. 2005

[8] Jari-Pascal Curty, Norbert Joehl, Catherine Dehollain and Michael J.

Declercq, “Remotely Powered Addressable UHF RFID Integrated System”,

IEEE J. Solid-State Circuits, Vol.40, No.11, Nov., 2005

CMOS RF Power Rectifier Design

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[9] Pavel V. Nikitin, K.V.Sshagiri Rao, Sander F. Lam, Vijay Pillai, Rene

Martinez, and Harley Heinrich, “Power Reflection Coefficient Analysis for

Complex Impedances in RFID Tag Design”, IEEE Trans. Microwave Theory

and Tech., Vol.53, No.9, Sept., 2005

[10] Jari-Pascal Curty, Norbert Joehl, Catherine Dehollain and Michael J.

Declercq, “A Model for u-powered Rectifier Analysis and Design”, IEEE

Trans. Circuits and Systems, Vol.52, No.12, Dec., 2005

[11] Udo karthaus and martin Fischer, “Fully Integrated Passive UHF RFID

Transponder IC with 16.7uW minimum RF Input Power”, IEEE Journal

Solid State Circuits, Vol.38, No.10, Oct., 2003

CMOS RF Power Rectifier Design