Experiment 2

Overview of combinational circuits and implementation of 8 bit full

ripple carry adder
Combinational Circuits

A combinational logic circuit is one in which the present state of the combination of the logic
inputs decides the output. The term combination logic means combining of two or more logic
gates to form a required function where the output at a given time depends only on the input.The
logic gates are the fundamental building blocks of a combinational circuit. By using the
combination of logic gates more complex combinational circuits can be implemented such as
multiplexers and de-multiplexers, comparators, adders and subtractors, etc.

A combinational circuit comprises of input variables, logic gates and output variables. The logic
gates accepts the inputs and depending on the type of functioning of the logic gate,output signals
are generated from them.The required output data is obtained from this process by transforming
the binary information given at the input. The figure below shows the schematic representation
of a generalized combinational logic circuit consisting of n input variable and m output variables.

In the above figure, there are n input variables and hence there will be 2n possible combinations
of bits at the input. By a Boolean expression of input variables, each output is expressed. So the
result of above generalized combinational logic circuit can be expressed by m Boolean
expressions.

In the above figure, the circuit accepts the binary variables and depending on the logical
combination of gates it generate outputs.

Verilog Design Styles

Verilog, like any other hardware description language, permits a design in either Bottom-up or
Top-down methodology.
Bottom-Up Design
The traditional method of electronic design is bottom-up. Each design is performed at the gate-
level using the standard gates. With the increasing complexity of new designs this approach is
nearly impossible to maintain. New systems consist of ASIC or microprocessors with a
complexity of thousands of transistors. These traditional bottom-up designs have to give way to
new structural, hierarchical design methods. Without these new practices it would be impossible
to handle the new complexity

Top-Down Design
The desired design-style of all designers is the top-down one. A real top-down design allows
early testing, easy change of different technologies and a structured system design along with
many other advantages.
Lab task: Implementation of 8 bit ripple carry adder.
Block diagram of 2 bit ripple carry adder

Verilog code of 2 bit ripple carry adder

module ADDER_2_BIT(a,b,cin,s,cout);
input[1:0]a,b;
input cin;
output[1:0]s;
output cout;
wire w1;
FULL_ADDER_1_BIT fo(a[0],b[0],cin,s[0],w1);
FULL_ADDER_1_BIT f1(a[1],b[1],w1,s[1],cout);

Endmodule

Test bench
module ADDER_2_BIT_TB;
// Inputs
reg [1:0] a;
reg [1:0] b;
reg cin;

// Outputs
wire [1:0] s;
wire cout;

// Instantiate the Unit Under Test (UUT)

ADDER_2_BIT uut (
.a(a),
.b(b),
.cin(cin),
.s(s),
.cout(cout)
);
 initial begin
// Initialize Inputs
a = 2'b01;
b = 2'b10;
cin =2'b11;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule

Simulation

Block diagram of 4 bit ripple carry adder

Verilog code of 4 bit ripple carry adder
module ADDER_4_BIT(a,b,cin,s,cout);
input[3:0]a,b;
input cin;
output[3:0]s;
output cout;
ADDER_2_BIT fo(a[1:0],b[1:0],cin,s[1:0],w1);
ADDER_2_BIT f1(a[3:2],b[3:2],w1,s[3:2],cout);
endmodule
Test bench
module ADDER_4_BIT_TB;

// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;

// Outputs
wire [3:0] s;
wire cout;

// Instantiate the Unit Under Test (UUT)

ADDER_4_BIT uut (
.a(a),
.b(b),
.cin(cin),
.s(s),
.cout(cout)
);

initial begin
// Initialize Inputs
a = 4'b0001;
b = 4'b0010;
cin = 1;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

end

endmodule
Simulation

Block diagram of 8 bit ripple carry adder

Verilog code of 8 bit ripple carry adder

module ADDER_8_BIT(a,b,cin,s,cout);
input[7:0]a,b;
input cin;
output[7:0]s;
output cout;
wire w1;
ADDER_4_BIT fo(a[3:0],b[3:0],cin,s[3:0],w1);
ADDER_4_BIT f1(a[7:4],b[7:4],w1,s[7:4],cout);
Endmodule
Test bench
module ADDER_8_BIT_TB;
// Inputs
reg [7:0] a;
reg [7:0] b;
reg cin;
// Outputs
wire [7:0] s;
wire cout;

// Instantiate the Unit Under Test (UUT)

ADDER_8_BIT uut (
.a(a),
.b(b),
.cin(cin),
.s(s),
.cout(cout)
);
initial begin
// Initialize Inputs
a = 8'b00001111;
b = 8'b11110000;
cin = 0;

// Wait 100 ns for global reset to finish

#100;

end
endmodule
Simulation