Microprocessor Based

Systems
Lecture No 03 Introduction to Von
Neumann Architecture

By Nasir Mahmood
 Overview of Last Lecture
  Main components of a computing system?
  CPU, Memory, Busses or Interconnections, I/O
  Difference between Computer Architecture and
Computer Organization?
  Architecture is those attributes visible to the
programmer
  Organization is how features are implemented,
typically hidden from the programmer
  Approach to understand Computer System?
  Top-Down approach to understand computer
Overview of Last Lecture Contd..
  Main Functions of computer?
  Data processing, Data storage, Data movement, Control
  Major components of the CPU?
  CU, ALU, Registers, CPU interconnect
  Major components of of Control Unit (CU)?
  Sequencing Logic – Controlling the order of events
  Microprogram Control Unit – Internal controls
  Microprogram Registers, Memory
  New trends in interconnections and processing?
  Multicore architectures and NOC
 Today’s Outline
  IC Integration Trends
  Moore’s Law and Intel’s Response
  Von Neumann Architecture
 Moore’s Law
  Gordon Moore, founder of Intel,
  In 1965 he noted that the number of transistors
on a chip was doubling every 18 to 24 months
Intel’s Response to Moore’s Prediction
 Von Neumann Architecture

  Stored Program concept

  Main memory storing programs and data
  ALU operating on binary data
  Control unit interpreting instructions from memory
and executing
  Input and output equipment operated by control unit
  Princeton Institute for Advanced Studies
  IAS
  Completed 1952
 Structure of von Nuemann
machine

Arithmetic and Logic Unit

Input
Output Main
Equipment Memory

Program Control Unit

 IAS - details
  1000 x 40 bit words
  Binary number
  2 x 20 bit instructions
  Set of registers (storage in CPU)
  Memory Buffer Register
  Memory Address Register
  Instruction Register
  Instruction Buffer Register
  Program Counter
  Accumulator
  Multiplier Quotient
 Structure of IAS - detail
Central Processing Unit
Arithmetic and Logic Unit

Accumulator MQ

Arithmetic & Logic Circuits

Input MBR
Output Instructions
Equipment & Data Main
Memory

IBR PC
MAR
IR Control
Circuits
Address
Program Control Unit
 Program Concept

  Hardwired systems are inflexible

  General purpose hardware can do different
tasks, given correct control signals
  Instead of re-wiring, supply a new set of
control signals
 What is a program?

  A sequence of steps
  For each step, an arithmetic or logical
operation is done
  For each operation, a different set of control
signals is needed
 Function of Control Unit

  For each operation a unique code is provided

  e.g. ADD, MOVE
  A hardware segment accepts the code and
issues the control signals
 Components

  The Control Unit and the Arithmetic and

Logic Unit constitute the Central Processing
Unit
  Data and instructions need to get into the
system and results out
  Input/output
  Temporary storage of code and results is
needed
  Main memory
Computer Components:
Top Level View
 Instruction Cycle

  Two steps:
  Fetch
  Execute
 Fetch Cycle

  Program Counter (PC) holds address of next

instruction to fetch
  Processor fetches instruction from memory location
pointed to by PC
  Increment PC
  Unless told otherwise
  Instruction loaded into Instruction Register (IR)
  Processor interprets instruction and performs
required actions
 Execute Cycle

  Processor-memory
  data transfer between CPU and main memory
  Processor I/O
  Data transfer between CPU and I/O module
  Data processing
  Some arithmetic or logical operation on data
  Control
  Alteration of sequence of operations
  e.g. jump
  Combination of above
Example of Program Execution
 Instruction Execution Further division
of a single
Cycle m a c h i n e
instruction
  Fetch   Fetch Operands
  Get the next instruction from   Performs memory read operation
program memory (If specified)
  Usually the address of next   Execute
instruction is stored in a special   ALU performs the operation (If
register (Program Counter)
specified)
  Increment the PC   Sends data to target operand
  Decode   Updates status flags
  Controller determines the type of   Store output
instruction to be executed
  Write to memory (If required)
  Passes operands to ALU (if
specified)
  Signals the ALU about the
operation to be performed
 Instruction Execution Cycle
PC program
I-1 I-2 I-3 I-4
  Fetch
  Decode memory fetch
  Fetch operands op1
read
op2
  Execute registers registers
  Store output instruction
I-1 register

decode
write

write

flags ALU

execute
(output)
21
Instruction Execution
in a Microprocessor
 Fetch Processor

Control unit Datapath

  Get next ALU

Controller
instruction into Control
/Status
IR
  PC: program Registers
counter, always
points to next
instruction
PC 100 IRload R0, M[500] R0 R1
  IR: holds the
fetched
instruction I/O

Memory
...
100 load R0, M[500]
500 10
101 inc R1, R0
102 store M[501], R1
501
...
 Decode Processor

Control unit Datapath

  Determine what ALU

Controller
the instruction Control
/Status
wants
Registers

PC 100 IRload R0, M[500] R0 R1

I/O

Memory
...
100 load R0, M[500]
500 10
101 inc R1, R0
102 store M[501], R1
501
...
 Fetch
Operand Processor

Control unit Datapath

  Move data Controller

ALU

Control
from memory /Status

to datapath
register Registers

10
PC 100 IRload R0, M[500] R0 R1

I/O

Memory
...
100 load R0, M[500]
500 10
101 inc R1, R0
102 store M[501], R1
501
...
 Execute Processor

Control unit Datapath

  ALU ALU
Controller Control
/Status

Registers

PC 100 IRload R0, M[500] R0 R1

I/O

Memory
...
100 load R0, M[500]
500 10
101 inc R1, R0
102 store M[501], R1
501
...
 Store
Results Processor

Control unit Datapath

  Write data Controller

ALU

Control
from register /Status

to memory
Registers
  This particular
instruction
does nothing 10
PC IRload R0, M[500]
during this 100 R0 R1

sub-operation
I/O

Memory
...
100 load R0, M[500]
500 10
101 inc R1, R0
102 store M[501], R1
501
...
 Instruction Cycles
PC=100 Fetch Processor
Store
Fetch Decode ops Exec. Control unit Datapath
results
ALU
clk Controller Contro
l
/
Status
Registers

10
PC 100 IR R0 R1
load R0, M[500]

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
28
 Instruction Cycles
PC=100 Processor

Fetch Decode Fetch Exec. Store Control unit Datapath

ops result ALU
clk s Controller Contro +1
l
/
PC=101 Status
Registers
Fetch Decode Fetch Exec. Store
ops result
clk s 10 11
PC 101 IR R0 R1
inc R1, R0

I/O

100 load R0, M[500] Memory

...
500 10
101 inc R1, R0
102 store M[501], R1
501
...
29
 Instruction Cycles
PC=100 Processor

Fetch Decode Fetch Exec. Store Control unit Datapath

ops result ALU
clk s Controller Contro
l
/
PC=101 Status
Registers
Fetch Decode Fetch Exec. Store
ops result
clk s 10 11
PC 102 IR R0 R1
store M[501], R1
PC=102
Fetch Decode Fetch Exec. Store I/O
ops result
100 load R0, M[500] Memory
...
clk s 500 10
101 inc R1, R0 501 11
102 store M[501], R1 ...
30
 Summary
  IC Integration Trends
  Intel has plans to continue riding on the Moore’s Law curve for another
ten years and has announced a 2.9 billion transistor chip for the
second quarter of 2011.
  The chip will fit into an area the size of a fingernail and use 22
nanometer technology

  Von Neumann Architecture

  Execution of program stored in memory
  Instruction cycle

  Fetch, decode, Fetch operand, Execute, Store results

THE END