Microprocessor Based

Systems
Lecture No 05 Virtual Machines and
Pipelining Concept

By Nasir Mahmood
 Overview of Last Lecture
  ISA
  Describes the processor at a logical level
  Difference Between RISC and CISC
Architectures
  CISC controlled by micro-programmed control
  Why to write programs in Assembly Language
  More optimization and efficient code
  Harvard Architecture Versus Von Neumann
Architecture
  In Harvard Architectures separate instructions and data
paths, in Von Neumann it has common paths
 Assembly Language & Machine
Language
  Machine language is a numeric language specifically understood by a
computer’s processor (the CPU). IA-32–compatible processors
understand a common machine language.

  Assembly language consists of statements written with short

mnemonics such as ADD, MOV, SUB, and CALL. Assembly language
has a one-to-one relationship with machine language: Each assembly
language instruction corresponds to a single machine-language
instruction.

  High level Languages have a one-to-many relationship with Assembly

Language. A single statement in C++ corresponds to multiple
instructions in Assembly Language.

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 A comparison
C++ Assembly Language

mov eax,Y
int Y; add eax,4
int X = (Y + 4) * 3; mov ebx,3
imul ebx
mov X,eax

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Comparison of Assembly Language to
High-Level Languages

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 Virtual Machine Concept

  Each virtual machine can be used to write programs that

will translate into the lower level VM
  Java is an example of the VM: Java Compiler translates
code into Java Byte Code which is then executed at run
time by a Java Virtual Machine

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 Virtual Machines 0 thru 5
  Level 0 represents the Digital
Logic Hardware
  Level 1 is an interpreter
hardwired into the processor
  Level 2 is the 1st level where
user can write programs but it
consists only of 0 & 1s

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 Levels of Representation
temp = v[k];
High Level Language v[k] = v[k+1];
Program
v[k+1] = temp;
Compiler
lw $15, 0($2)
Assembly Language
Program lw $16, 4($2)
sw $16, 0($2)
Assembler sw $15, 4($2)
0000 1001 1100 0110 1010 1111 0101 1000
Machine Language 1010 1111 0101 1000 0000 1001 1100 0110
Program 1100 0110 1010 1111 0101 1000 0000 1001
0101 1000 0000 1001 1100 0110 1010 1111

Machine Interpretation

Control Signal ALUOP[0:3] <= InstReg[9:11] & MASK

Specification
°
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 Multi-Stage Pipeline
  Six Stages
  Bus Interface Unit
  Code Prefetch Unit

  Instruction Decode Unit

  Execution Unit

  Segment Unit

  Paging Unit
 Six Stage Non-pipelined
Execution

  for k execution stages, n instructions require

(n * k) cycles to process
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 Pipelining

  Pipelining is an implementation technique

whereby multiple instructions are overlapped
in execution.
  It takes advantage of parallelism that exists
among the actions needed to execute an
instruction.
  Pipelining is a key technique used to make
CPUs fast.

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 Pipelining contd….

  A pipeline is like an assembly line e.g. An automobile

assembly line
  There are many steps in assembling a car
  Each step contributes something to the car
  Each step operates in parallel with other steps, although on a different
car
  In a computer pipeline, each step in the pipeline completes part of an
instruction. Different steps are completing different parts of different
instructions.
  Each of these steps is called a pipe stage or pipe segment.
  The stages are connected to form a pipe.
  Instructions enter at one end, progress through the stages and exit at the
other end, just as cars would in an assembly line.

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 Six Stage Pipelined Execution

  When pipeline is full, all 6 stages are in use.

  for k execution stages, n instructions require
k + (n-1) cycles to process

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 Pipelining - Throughput
  In an automobile assembly line, throughput is defined as No.
of cars / hour & determined by how often a completed car
exits assembly line. Likewise, the throughput of an instruction
pipeline is determined by how often an instruction exits the
pipeline.
  The time required b/w moving an instruction one step down
the pipeline is a processor cycle.
  As all stages proceed at the same time, the length of a
processor cycle is determined by the time required for the
slowest pipe stage. In a computer, this cycle is usually 1 clock
cycle or 1 tick.

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 Superscalar Architecture

  A superscalar CPU architecture implements a form of

parallelism called instruction-level parallelism within a
single processor.
  Can be thought of as having 2 pipelines.
  It therefore allows faster CPU throughput than would
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otherwise be possible at a given clock rate.
 Single Pipeline Execution

  If execution stage requires more than one cycle then we have wasted
cycles
  In general, for k stages (where one stage requires two cycles), n
instructions require (k +2n - 1) cycles to process.
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 Superscalar 6-Stage Pipelined
Processor

  Wasted cycles are removed, so n instructions can be executed in (k + n)

cycles, where k indicates the number of stages.

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 Summary
  Assembly Language & Machine Language
  How the translation is done
  Compiler, Assembler, OS
  Multistage Pipeline Concept
  Concept of Stages and cycles execution
  Make the execution fast by parallel pipelines

  Superscalar Processor
THE END