Experiment No.

Introduction to layout Design rules

DRC Rules for 180nm technology

You have to multiply each value with 2

Example: Minimum Nwell width -------------------------------->1.2um

Nwell to Oxide spacing must be ------------------------------------>0.6 um

Design rules write with pen

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 Experiment No-2

Layout, physical verification, placement route for complex design.

CMOS inverter

Aim: To verify CMOS Inverter characteristics using gpdk_MIET 180nm

Technology.

Tools:

Schematic:

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Dc Response:

Transient Response:

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Layout:

Result:

16BD1A0445
 Experiment No -3

Layout, physical verification, placement route for complex

design.

CMOS NAND

Aim: To find DC, Transient analysis and post layout simulation of NAND gate

Tools:

Schematic Diagram:

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Dc Response:

Transient Response:

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Layout:

Result:

16BD1A0445
 Experiment No -4

Layout, physical verification, placement route for complex

design.

CMOS NOR

Aim: To find DC, Transient analysis and post layout simulation of NOR gate

Tools:

Schematic Diagram:

16BD1A0445
Dc Response:

Transient Response:

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Layout:

Result:

16BD1A0445