EXPERIMENT : 4

AIM: To study 4-bit Multiplier using VHDL .

REQUIREMENTS: Active-HDL (Student Edition)

PROGRAM CODE:
-------------------------------------------------------------------------------
-
-- Title : multiplier4
-- Design : Logic4
-- Author : multiplier
-- Company : Hewlett-Packard Company
--
-------------------------------------------------------------------------------
-
-- File : c:\my_designs\Logic4\src\multiplier4.vhd
-- Generated : Wed sep 11 10:04:39 2019
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
-- Description :
-------------------------------------------------------------------------------

--{{ Section below this comment is automatically maintained

-- and may be overwritten
--{entity {multiplier4} architecture {multiplier4}}

library IEEE;
use IEEE.std_logic_1164.all;

entity multiplier4 is
port(
A : in STD_LOGIC_VECTOR(3 downto 0);
B : in STD_LOGIC_VECTOR(3 downto 0);
S : out STD_LOGIC_VECTOR(7 downto 0)
);
end multiplier4;

--}} End of automatically maintained section

architecture multiplier4 of multiplier4 is

signal S21, S31, S32, S41, S42, S51, C11, C21, C22, C31, C32, C33, C41, C42,
C43, C51, C52, C61 : STD_LOGIC;
begin
S(0) <= (A(0) AND B(0));
 S(1) <= (A(1) AND B(0)) XOR (A(0) AND B(1));
C11 <= (A(1) AND B(0)) AND (A(0) AND B(1));
S21 <= (A(1) AND B(1)) XOR (A(0) AND B(2));
C21 <= (A(1) AND B(1)) AND (A(0) AND B(2));
S(2) <= (A(2) AND B(0)) XOR S21 XOR C11;
C22 <= ((A(2) AND B(0)) AND S21) OR (S21 AND C11) OR ((A(2) AND B(0)) AND C11);
S31 <= (A(1) AND B(2)) XOR (A(0) AND B(3));
C31 <= (A(1) AND B(2)) AND (A(0) AND B(3));
S32 <= (A(2) AND B(1)) XOR S31 XOR C21;
C32 <= ((A(2) AND B(1)) AND S31) OR (S31 AND C21) OR ((A(2) AND B(1)) AND C21);
S(3) <= (A(3) AND B(0)) XOR S32 XOR C22;
C33 <= ((A(3) AND B(0)) AND S32) OR (S32 AND C22) OR ((A(3) AND B(0)) AND C22);
S41 <= (A(2) AND B(2)) XOR (A(1) AND B(3)) XOR C31;
C41 <= ((A(2) AND B(2)) AND (A(1) AND B(3))) OR ((A(1) AND B(3)) AND C31) OR
((A(2) AND B(2)) AND C31);
S42 <= (A(3) AND B(1)) XOR S41 XOR C32;
C42 <= ((A(3) AND B(1)) AND S41) OR (S41 AND C32) OR ((A(3) AND B(1)) AND C32);
S(4) <= (S42 XOR C33);
C43 <= (S42 AND C33);
S51 <= (A(3) AND B(2)) XOR (A(2) AND B(3)) XOR C41;
C51 <= ((A(3) AND B(2)) AND (A(2) AND B(3))) OR ((A(2) AND B(3)) AND C41) OR
((A(3) AND B(2)) AND C41);
S(5) <= (S51 XOR C42 XOR C43);
C52 <= (S51 AND C42) OR (C42 AND C43) OR (S51 AND C43);
S(6) <= (A(3) AND B(3)) XOR C51 XOR C52;
C61 <= ((A(3) AND B(3)) AND C51) OR (C51 AND C52) OR ((A(3) AND B(3)) AND C52);
S(7) <= (C61);

-- enter your statements here

-end multiplier4; WAVEFORM :

RESULT: 4-bit Multiplier has been studied and implemented successfully using VHDL.