Chapter 6 ■ VHDL 101

Answers

1. The following code is for a home security alarm system.

library ieee;
use ieee.std_logic_1164.all;
entity alarm_system is
port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
F: out std_logic
);
end alarm_system;
architecture behavioral of alarm_system is
signal D: std_logic;
signal E: std_logic;
begin
D <= A and B;
E <= C and B;
F <= D or E;
end behavioral;

2. Full Adder block diagram (Figure 6-5) and digital design.

Figure 6-5.  Full Adder block diagram

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 Chapter 6 ■ VHDL 101

library ieee;
use ieee.std_logic_1164.all;
entity fulladder is
port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
SUM: out std_logic;
Carrout: out std_logic
);
end fulladder;
architecture behavioral of fulladder is
signal D: std_logic;
begin
D <= A xor B;
SUM <= D xor C;
Carrout <= ((D and C) or (A and B));
end behavioral;

6.3 Summary
VHDL is a hardware description language. It will be much easier for you to design an FPGA when you can
start to see things from a hardware point of view. Any complex digital design should be able to be broken
down into smaller-size modules for you to implement them in VHDL.
Each VHDL has the following structure:
• library
• entity
• architecture
The chapters that follow will give more detail on how to use VHDL to design more hardware!

■■Tip  Notepad ++ is a very good (and free) editor which supports VHDL! 

“A person who never made a mistake never tried anything new.”

—Albert Einstein

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CHAPTER 7

Number Theory for FPGAs

Number theory is “the Queen of Mathematics.” It is the foundation of mathematics and includes all the basic
elements. Don’t worry, you did pick up a book on FPGA (field-programmable gateway array) design, but
we’re going to have to cover just a little math in order for you to be able to actually do anything useful with
an FPGA. In this chapter we are going to show you several basic elements of VHDL (VHSIC (very high speed
integrated circuit) Hardware Description Language), such as identifiers and numbers. All of the stuff shown
in this chapter will help you write better VHDL code. You should bookmark this chapter because you will
likely come back to frequently when you actually start to write your own VHDL code.

7.1 Vocabulary in VHDL
Vocabulary is the first thing you learn in any new language such as VHDL. There are some basic rules for
VHDL words. Listing 7-1 provides an example.
• VHDL is NOT case sensitive
• It doesn’t care about how many spaces or tabs in the code
• None of the words can start with number

Listing 7-1.  Not Case Sensitive and Doesn't Care About Whitespace
NotCaseSensitive <= Spaces Or Tabs;

nOtcAsEsEnsItIvE <= spaceS OR TABS;

7.1.1 Identifiers
An identifier is defined by the VHDL designer to name items in a VHDL model (Figures 7-1 and 7-2).
Examples of VHDL items are port names and signal names. The rules for identifiers are as follows:
• Can only contain a combination of alphabetic letters ( A-Z, a-z ), numbers ( 0-9 ) and
underscores (_)
• Must start with alphabetic letters (A-Z, a-z)
• Cannot end with an underscore (_) and cannot have consecutive underscores
• The identifier should be self-describing

© Aiken Pang and Peter Membrey 2017 125

A. Pang and P. Membrey, Beginning FPGA: Programming Metal, DOI 10.1007/978-1-4302-6248-0_7
Chapter 7 ■ Number Theory for FPGAs

■■Tip Smart choices for identifiers make your VHDL code easier to read and understand, which in turn
means less effort required to find and fix problems in the code.

Figure 7-1.  Valid identifiers

Figure 7-2.  Invalid or bad-style identifiers

■■Note  In VHDL-93, VHDL supports extended identifiers, which allows you to use any character in any order.
We suggest you don’t use these in your design files as they tend to confuse and complicate rather than improve
the situation.

7.1.2 Reserved Words—Keywords
Some identifiers, called reserved words or keywords, are reserved for special use in VHDL, so we cannot use
them as identifiers for the items we define. Table 7-1 shows the full list of reserved words.

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Table 7-1.  VHDL Reserved Words
Reserved Word
constant, generic, in, inout, map,
out, of, port, signal
if, then, elsif, else, case, select,
when, is, end, null
srl, sra, sll, sla, rol, ror
and, nand, nor, not, or, xnor, xor
abs, mod, rem
entity, architecture, process, begin,
variable, function, component
downto, to, type, subtype, others,
array, range, record
library, all, use, package, body
after, assert, exit, file, inertial, new,
on,open, report, reject, return,
severity, transport, unaffected,
until, wait
for, generate, loop, next, while
access, alias, block, buffer, bus,
disconnect, guarded, impure,
linkage, postponed, procedure,
pure, register, shared, units
attribute, group, label, literal
configuration
Chapter 7 ■ Number Theory for FPGAs
Description
Entity reserved words: port, in, out, and map are used in the entity
section. Inout is another port mode that allows a bidirectional port to
be read and updated within the entity model.
Signal represents a wire or a placeholder for a value. Signals are assigned
in signal assignment statements and declared in signal declarations.
Constants can hold a single value of a given type.
Generic is similar to port but it is a constant value. It is used to pass
environment information to submodules.
Conditional logic statements: if, then, elsif, else, case, select, and when
are used in conditional logic.
“End” is used at the end of statement.
“is” equates the identity portion to the definition portion in the
declaration.
“null” is sometimes used with “case”. There’s an example for it in
Chapter 8.
Shift operators: srl, sra, and ror are shift left; sll, sla, and rol are shift
right.
Logic operators: In Chapter 8 we will cover these in more detail too.
Arithmetic operators: Abs = absolute value; Mod = modulus;
Rem = remainder
Most of the VHDL models need to use these reserved words. We used
entity, architecture, and begin Chapter 6’s full adder example.
Process is sequential or concurrent code to be executed.
Variable and function are used to define a function in VHDL code.
These reserved words are used to define signals and types in VHDL
code. You will see examples of them later in this chapter.
All is a suffix for selecting all declarations that are contained within the
package or library denoted by the prefix.
These reserved words are very useful when simulating VHDL code. All
of these reserved words cannot be used to generate REAL hardware.
Don't use them in your hardware design VHDL code.
for and while loop are very useful when you need to generate multiple
identical components.
It’s strongly recommended that you don’t use these reserved words in
your FPGA designs.
Attribute reserved words
When designing for portability, you need to use configuration. We will
not talk about this in this book as it’s a fairly advanced topic.
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