Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables

3.
In the Project Navigator, select Files. Right-click the file four_bit_adder.vhd and
click Set as Top-Level Entity.
4.
Click Processing ➤ Start ➤ Start Analysis & Elaboration from the Quartus
Prime menu or click on the blue triangle with green tick box in the tool bar to
start analysis & elaboration.
5.
Click Tools ➤ Run Simulation Tool ➤ RTL Simulation from the Quartus Prime
menu to start simulation.
6.
In the ModelSim transcript type the following to run simulation

a. ModelSim ➤ vsim work.four_bit_adder
7.
Type add wave -position insertpoint sim:/four_bit_adder/* in the transcript
box. The wave windows should show as Figure 8-22.

Figure 8-22.  4-bit adder simulation wave windows

8.
Copy the tcl to transcript (Listing 8-5) and hit Enter.

Listing 8-5.  tcl for Generating Four-Bit Adder Inputs

force -freeze sim:/four_bit_adder/D1 0000 0
force -freeze sim:/four_bit_adder/D2 0000 0
force -freeze sim:/four_bit_adder/Carrin 0 0
run 100 ns
force -freeze sim:/four_bit_adder/D1 0001 0
run 10 ns
force -freeze sim:/four_bit_adder/D1 0010 0
run 10 ns
force -freeze sim:/four_bit_adder/D2 0010 0
run 10 ns
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force -freeze sim:/four_bit_adder/D2 0011 0

run 10 ns
force -freeze sim:/four_bit_adder/D2 0111 0
run 10 ns
force -freeze sim:/four_bit_adder/D1 0110 0
run 10 ns
force -freeze sim:/four_bit_adder/D1 1110 0
run 10 ns
force -freeze sim:/four_bit_adder/D1 0110 0
run 10 ns
force -freeze sim:/four_bit_adder/Carrin 1 0
run 10 ns

9.
Wave windows will show all the calculation results from the four-bit adder
(Figure 8-23). All the input and output are in binary number (Figure 8-24).
Select D1, D2, and Sum with Ctrl key and then right-click it to select unsigned
(Figure 8-25).

Figure 8-23.  4-bit adder simulation result

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Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables

Figure 8-24.  How to change the data radix in simulation

Figure 8-25.  p Data radix in unsigned

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 Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables

8.3 Combinational Logic Design in FPGA

Combinational logic can be implemented in three different ways: Boolean equations, truth tables, and logic
gates. Figure 8-26 shows an example of using the different ways to get VHDL logic.

Figure 8-26.  Example Boolean equations

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Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables

A FPGA designer usually uses Boolean equations to build combination logic. They are simple and clear;
however, they may not provide the best performance (speed) design.

8.4 Summary
Boolean algebra is used to model simple true/false operations with AND/OR/NOT. In VHDL, the IEEE
provides a std_logic_1164 library to add more features on Boolean algebra in std_logic and std_logic_vector
data types.
This chapter also teaches you how to call modules from another module. It is one of the main reasons
you are using HDL to design hardware—you can reuse your modules!

■■Tip  Break down big problems into small pieces and solve them one small piece at a time. 

“Logic will get you from A to B. Imagination will take you everywhere.”
—Albert Einstein

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