Chapter 15 ■ Two-Way Communications with Your Raspberry Pi: SPI

elsif(spi_clk_falling_edge = '1') then

spi_dataout_shifter <= spi_dataout_shifter(6 downto 0)& '0';
end if;
end if;
end process;

rspi_miso <= spi_dataout_shifter(7); -- msb send to the SPI master

end arch;

--=============================================================================
-- architecture end
--=============================================================================

15.4 Create the FPGA Top-Level Design

We need to have a top-level design to use the output from the SPI slave to control the LEDs on the BeMicro
MAX10 board. The top-level design should look like Figure 15-17. The top design includes the SPI slave, SPI
data register, and the Altera PLL IP (Internet Protocol).

Figure 15-17.  FPGA top-level block design

We will reuse the same PLL from Chapter 13 which is 50 MHz in and generate a 29.5 MHz clock out. The
SPI slave and SPI data register will directly use this output clock as a system clock.
The SPI DATA register is updated by the SPI slave wr_enable output. The value of the register will be
used to drive the LED outputs.

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15.4.1 Top-Level Design VHDL Code

Figures 15-18 and 15-19 are the top-level design. Lines 12 to 15 are the port list for the SPI to the Raspberry
Pi. The top-level design included an Altera PLL IP—pll-29p5M (see Chapter 13).

Figure 15-18.  Raspberry Pi SPI top-level design Part 1

We use the locked signal from the PLL as an active low reset (rst_i). The signal will go high when the PLL
output is stable. This reset (rst_i) and output clock (clk_29Mz_i) are used in the rest of the logic.
SPI_DATA register is updated with data_out when the spi_slave, which is instantiated as spi_slave_pm
output wr_enable, is high. The LED outputs are an inverted version of the SPI_DATA (line 72) because the
LEDs are active low logic outputs.

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Chapter 15 ■ Two-Way Communications with Your Raspberry Pi: SPI

Figure 15-19.  Raspberry Pi SPI top-level design Part 2

The RTL design view in Quartus looks like Figure 15-20 when you compile the design and select the RTL
view from the top-level design (see section “Using Altera Quartus to Understand the FSM,” in Chapter 11, for
more information on how to use the RTL view).

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Figure 15-20.  RTL view of the Raspberry Pi SPI top-level design

15.4.2 Generate and Program the FPGA

You can create the project in the same way you did in Chapter 13, or you can add the two new VHDL design
files (spi_slave.vhd and raspberryPi_spi_top.vhd) under the same project from that chapter and set
raspberryPi_spi_top.vhd as the top-level entity. Your Altera Quartus Project Navigator should look like
figure 15-21 (box 1) after you set the top level as raspberryPi_spi_top.vhd.
Figure 15-21 shows the steps (Box 2 and Box 3) to generate the bit file (.sof file) and start programming
the design. Figure 15-22 shows the steps for selecting the SOF file and starting to program the FPGA. All you
need to do is follow the arrow steps in the figure. After you have programmed the FPGA, it only has the red
LED on. The green LEDs are not blinking because the Raspberry Pi SPI master is not running. Let's go to the
next section to get the SPI master running.

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Figure 15-21.  Generate the bit file for the FPGA

Figure 15-22.  Programming the bit file for the FPGA

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