Wireless Personal Communications

https://doi.org/10.1007/s11277-020-07611-9

Analyzing the Impact of Sigma‑Delta Modulation

on Performance Parameters of Adaptive Filters

Aneela Pathan1,2   · Tayab D. Memon3,4

© Springer Science+Business Media, LLC, part of Springer Nature 2020

Abstract
Sigma-delta modulation (SDM), initially introduced for ADCs and DACs is now well
known in an alternative domain of short word-length (SWL) algorithm based digital sys-
tem design. Its applications start from simple arithmetic operations to very complex cir-
cuits, like the adaptive filters. The conventional multi-bit processing systems consume
more resources in their implementation on ASICs and FPGAs, whereas, SDM based sys-
tems being processing the data in a single-bit result a compact design. This paper is an
effort towards SDM based single-bit, design of adaptive filter using Wiener–Hopf equa-
tion on FPGA, along with analyzing the impact of SDM on performance parameters, like,
Signal to Noise Ratio (SNR), Probability of Error (PE), and Mean Square Error (MSE).
Besides, the error graph, showing the difference between the filtered signal in multi-bit and
SDM based is also shown and analyzed using Matlab. As, the mobile phone operates in a
continuous varying environment (for example, during the travel), and hence the statistical
parameters (SNR, MSE, and PE) due to varying channel also vary accordingly in its con-
ventional operations and architectures, but results show that instead if SDM is used, those
statistical parameters remain constant, and in comparison to the multi-bit approach the
SDM based system outdoes in all means of functionality as well as performance. Hence,
it may be concluded that for continuous varying environments of wireless communication,
especially the mobile communication systems, the SDM based approach may be adopted
for reasons of good performance as well as compact system design.

Keywords  Sigma delta modulation · Short word length · Adaptive filters · Matlab

* Aneela Pathan
pathan_aneela@quest.edu.pk
1
Department of Electronic Engineering, Quaid-e-Awam University of Engineering Science
and Technology, QUEST, Larkana, Sindh, Pakistan
2
Institute of Information and Communication Technologies, Mehran University of Engineering
and Technology, Jamshoro, Pakistan
3
Department of Electronic Engineering, Mehran University of Engineering and Technology,
Jamshoro, Pakistan
4
HHCMS Lab, National Center for Robotics and Automation, MUET, Jamshoro, Pakistan

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 A. Pathan, T. D. Memon

1 Introduction

The ways seen in the optimized implementation of DSP systems include: algorithm optimi-
zation, electronic design automation (EDA) tools, and word-length optimization [1].
The two prior methods are widely adapted since the concept of optimization, whereas
the third is still an active research domain even its various hardware-based implementa-
tions on FPGA and ACISs are found in research.
The DSP system, for example, mobile phones comes with sensing, computational, stor-
age, and communication resources [2], and gives communication services, wireless inter-
net services, multimedia and entertainment services [3], and other computational intensive
services [3].
Phones are powered from batteries which are limited in size and therefore capacity.
Computation intensive applications reduce the battery life of mobile handsets to a few
hours of operation due to multi-bit processing [2].
The solution to this may be the word-length optimization (converting multi-bit into sin-
gle bit and making the system compact) that may be used from general-purpose DSP sys-
tem design to complex adaptive system identification, adaptive noise cancellation, adaptive
linear prediction, and adaptive channel equalization.
The word-length optimization comes in the domain of SWL algorithms the key to that is
the sigma-delta modulation.
SDM, like Pulse Code Modulation (PCM), converts the analog signal into a digital sig-
nal in its normal mode of operation [4]. But since decay or two its application is diversified
towards compact DSP system design [5].
Research proves the SDM as a major component in the short word length algorithm, as
it is used to transform the data from multi-bit to single-bit [6, 7].
Some of the research in this domain include the design of simple arithmetic units [6,
10], FIR filters(fully or partially transformed in a single bit) [8, 9], IIR filters [11–13] and
some very complex structures of adaptive filters [5, 14–16].
In the references cited above, the FPGA based implementations of the proposed archi-
tectures are also shown and discussed.
Recently [17, 18], authors have also implemented SDM based and conventional adap-
tive channel equalizers on Xilinx Spartan 6 FPGA using a new µ-less approach for the
steepest-descent method and wiener-filter.
Various performance parameters in both implementations were simulated and brought
into results for statistical calculations and area-performance analysis; but the work is lack-
ing in comparing the approaches one to one in channel performance characteristics (SNR,
PE, and MSE).
This paper is an effort towards SDM based single-bit adaptive filter using Wiener- Hopf
equation on FPGA, along with analyzing the impact of SDM on performance parameters,
including Signal to Noise Ratio (SNR), Probability of Error (PE), and Mean Square Error
(MSE). Besides, the error graph, showing the difference between the filtered signal in
multi-bit and SDM based is also shown and analyzed using Matlab. As, the mobile phone
operates in a continuous varying environment (for example, during the travel), and hence
the statistical parameters (SNR, MSE, and PE) due to varying channel also vary accord-
ingly in its conventional operations and architectures, but results show that instead if SDM
is used, those statistical parameters remain constant, and in comparison to the multi-bit
approach the SDM based system outdoes in all means of functionality as well as perfor-
mance. Hence, it may be concluded that for continuous varying environments of wireless

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Analyzing the Impact of Sigma-Delta Modulation on Performance…

communication, especially the mobile communication systems, the SDM based approach
may be adopted for reasons of good performance as well as compact system design.
The paper further proceeds as follows: In Sect. 2 the architecture of conventional multi-
bit and SDM based systems is given and elaborated. In Sect. 3, Matlab based simulation of
both architectures are given along with their graphs and results. Section 4 shows Vertex-7
FPGA based implementation of single-bit and multi-bit adaptive channel equalizer and the
conclusion of the paper and the future work is conveyed in Sect. 5.

2 Architecture of Conventional and Proposed Design Approach

The adaptive channel equalizer is one of the key modules of the communication system
that is used to get out of the effect of Inter Symbol Interference (ISI) that is caused by
multi-channel propagation of the same signal [19].
The theme of adaptive filter is the adaptation to adjust the characteristics of the filter
through an interaction with the environment [20].

• The basic components of the adaptive filter shown in Fig. 1 include:

• The signals being processed by the filter.
• The structure that defines how the output signal of the filter is computed from its input
signal.
• The parameters within this structure that can be iteratively changed to alter the filter’s
input-output relationship.
• The adaptive algorithm that describes how the parameters are adjusted from one time
instant to the next [21].

In a channel equalizer (Fig. 1) the desired signal d(n) is sent before to the receiver for a
short training period and is set to be the delayed version of the signal that we need to filter.
The difference between desired and channel-affected noisy signals generates the error
e(n) which is used later to update the filter coefficient of the adaptive filter to produce a
reverse response, and hence to mitigate the channel effects (inter-symbol interference in
particular).
Amongst many available methods, wiener belongs to a class of adaptive filters that has
various applications in the field of communication.

White Noise

u(n) d(n)
d(n) channel ∑ Channel Equlizer

e(n)
∑

Fig. 1  Block diagram of general adaptive filer

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 A. Pathan, T. D. Memon

Desired signal d11(n)

x(n) Noisy Signal u11(n)

Z-N ∑

Noise v2(n)

w(n+1)=R-1P
y(n)

Fig. 2  Conventional wiener filter-based model of adaptive channel equalizer

Desired signal d11(n) d1t(n)

SDM

x(n) Noisy Signal u11(n)

-N u1t(n)
Z ∑ SDM

Noise v2(n)

w(n+1)=R-1P
flt2
Decimation Filter
y(n)

Fig. 3  Proposed architecture of SDM based adaptive channel equalizer using wiener filter

It works on the principle of solving the system of linear equations. This is because the
filter weights get updated as follows: 𝜔opt = R−1 P [22]. This is known as the Wiener–Hopf
equation.
Proposed Model In the models simulated in this work (Figs. 2 and 3 for multi-bit and
single-bit approach respectively), the input signal is a delayed version of the desired signal.
Let the desired signal D11 using an autoregressive process be written as:
D11 (z)
H1 (z) = (1)
V1 (z)

where, v1 is the independent and identically distributed random variable. The discrete-time
representation of the desired signal is given by:
v1 (n) = d11 (n) + a × d11 (n − 1) (2)
To include the effects of random noise in the channel, a second input signal v2 (n) is added
to the model whose all samples are independent of each other and is uncorrelated to the
desired signal.

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Analyzing the Impact of Sigma-Delta Modulation on Performance…

The channel (perturbation) model is more complex. It involves a low pass filter with a
transfer functions:
X(z)
H2 (z) = (3)
D11 (z)

The function X(z) can be approximated by x(n) in the difference equation:

x(n) = bx(n − 1) + d11 (n) (4)
And a white noise (v2) corrupted signal (u11) at channel output becomes:
u11 (n) = x(n) + v2 (n) (5)
For the case of a single-bit domain (Fig. 3), the desired signal and the noise corrupted
input signal shown as ult(n) and dlt(n) is passed through the SDM block, hence making the
system to operate in a single-bit domain.
As the weight updating is also carried out in a single bit, it results in the filtered signal
be in the same form.
But as conventional, the signal generated at the input is in multi-bit representation;
therefore it is necessary to re-convert the filtered output in the same format.
The decimation block in Fig. 3 is used for this purpose. It works in reciprocal to interpo-
lation, the key of SDM used to over-sample the signal to higher rates, to mitigate the effect
of noise.

3 Matlab Based Simulation and Results

The Matlab based simulation results of the above-discussed architectures are shown in pro-
ceeding graphs.
Figure 4, shows the data sequence given as the input to conventional and SDM based
adaptive wiener filter. To model the channel impairments, some of the noise is added to
this signal.
To the SDM based system, the desired input is first converted into a single bit using
sigma-delta modulation and then is passed through an analog decimation filter to analyze if
the actual and one passed through the SDM system have the same information and statisti-
cal characteristics.
It may be seen in the graphs that all 200 samples in both approaches exhibit almost the
same characteristics and representation.
The given below graphs show the desired data sequence given to multi-bit and conven-
tional approaches. The desired data is a noise-free and shifted version of the input data.
For SDM based approach the desired data is first coded into single bit and then is re-
converted to multi-bit.
The SDM based system relies on two operations, the interpolation at transmitter side
and decimation at the receiver.
As it is evident from the graphs, the decimation filter does not produce the perfect
analog output; but this information loss may be negligible for less sensitive applications
like video or voice communication.
The noisy input sequences were given to the SDM based and conventional wiener based
filters. The results are shown in Fig. 5.

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 A. Pathan, T. D. Memon

Fig. 4  200 samples of the input data sequence

Fig. 5  200 samples of desired data sequence

In Fig. 6, it may be seen that for the same input the output differs in single-bit and
multi-bit domain.
In a conventional multi-bit wiener based approach the filtered signal shows some var-
iations in signal amplitude when comparing to desired data. Whereas, for SDM based
systems, this effect is negligible. This effect is further elaborated in Fig. 7.
Figure  7, shows the graphs of the desired signal versus filtered signal of both
approaches. It is worth noting that compared to the multi-bit approach the single bit fil-
ter works better on input data and produces the output very similar to the desired signal.

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Analyzing the Impact of Sigma-Delta Modulation on Performance…

Fig. 6  200 samples of filtered data sequence

Fig. 7  200 samples of filtered and desired data sequence

The difference between the filtered signals may be seen in Fig. 8. The graph shows the
amount of difference between the two outputs calculated as the subtraction of each sample
value of one filter from the other.
Channel characteristics vary with change in the environment. The performance param-
eters needed to analyze to see if the designed filter suits to channel impairments like Signal
to Noise Ratio (SNR), Probability of Error (PE), and Mean Square Error (MSE).
The graphs shown below are the simulation results showing these parameters against
the change in the environment in terms of channel noise variance.
A very important point to notice is the constant performance of SDM based approach in
terms of SNR, even with a change in variance value. This is due to the inherent character-
istics of SDM, as it deals with sampling the signal with a high sampling ratio that in conse-
quence produces the output that is more immune to noise (Figs. 9, 10, 11).

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 A. Pathan, T. D. Memon

Fig. 8  200 samples of error signal as the difference between two outputs

Fig. 9  Variance versus SNR for conventional and SDM based design

Fig. 10  Variance versus PE for

conventional and SDM based
design

The same may be observed for the other two parameters as well. The variance versus
probability of error values show the dominating performance of SDM based design in
two ways, its lower value and is constant for a range of noise variance.
All this analysis and the graph showing the less probability of error value of a single
bit domain make it feasible to be adapted in a constantly changing environment of wire-
less communication.

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Analyzing the Impact of Sigma-Delta Modulation on Performance…

Fig. 11  Variance versus PE for

conventional and SDM based
design

4 FPGA Based Implementation

To validate the compactness of SDM based architecture and compare it with a conven-
tional multi-bit algorithm, an FPGA based implementation of the design was carried out
targeting a Xilinx Virtex7 FPGA using version 14.2 of the ISE.
The input data type to the conventional multi-bit adaptive channel equalizer simu-
lated in MATLAB was floating-point decimal values. Before FPGA implementation,
those floating-point decimal values were converted to IEEE-754, the 32-bit floating-
point data format supported by the FPGA synthesis tools. Hence, the first multi-bit
implementation of the adaptive channel equalizer involved 32-bit processing that was
carried out by instantiating 32-bit floating-point IP cores (built-in blocks of FPGA).
On the other hand, the SDM based implementations used a combination of binary
input data, comprising the values [17], and ternary coefficients from the set {+ 1, 0,.
The SDM portion of the design was carried out in MATLAB as this involved analog
signals, not supported by most FPGAs; while the adaptive filter was then implemented
in Xilinx. The single-bit implementation was achieved using simple logic gates like
AND, OR, and XOR only. The difference in data width caused a commensurate reduc-
tion in resources when implementing a multi-bit and single-bit system.
Table 1, compares post place and route results (very near to real-time implementation
in FPGA) obtained for the two approaches. It is evident from the results that the pro-
posed SDM approach is superior to the multi-bit approach in all aspects of area and per-
formance. For example, its operating frequency is just over six times that of the equiva-
lent multi-bit filter.

Table 1  FPGA based Factors Multi-bit SDM-based

implementation results of an
adaptive channel equalizer
LUTS 101,319 12
DSP48 0 0
BRAM 0 2
Delay (ns) 12.66 2.144
Logic Levels 101 1
Frequency (MHz) 78.963 466.364

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 A. Pathan, T. D. Memon

5 Conclusion and Future Work

In this work, two different approaches (multi-bit and single-bit) of wiener filter for adap-
tive channel equalizer were simulated in MATLAB to analyze the impact of sigma-delta
modulation on performance parameters of the adaptive filter along with their hardware-
based implementation on Vertex7 FPGA.
The results indicate that in continuously varying environments, the SDM based
approach exhibits the constant performance characteristics in terms of SNR, PE, and
MSE, and hence making it more suitable for applications, like mobile communications.
Besides, the FPGA based implementation also shows plausible results in terms of
consumed resources and the achieved frequency as well.
Hence it may be concluded that the SDM based approach may be adopted in wireless
communication systems for reasons of good performance as well as compact system
design.
In the future, integration of SDM systems in real-time environments will be simu-
lated on Matlab along with its hardware implementation on FPGAs.

Acknowledgments  This research work is supported by the Higher Education Commission (HEC), Pakistan
under the National Research Program for Universities (NRPU) grant Number 8521 and National Center for
Robotics and Automation (NCRA) joint lab titled “Haptics, Human Robotics and Condition Monitoring
Systems (HHCMS) Lab” established at Mehran University of Engineering and Technology, Jamshoro.

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Publisher’s Note  Springer Nature remains neutral with regard to jurisdictional claims in published maps and
institutional affiliations.

Aneela Pathan  received degrees of BE in Telecommunication from

Mehran UET, Jamshoro Sindh, Pakistan in 2008 and ME in Electronic
Engineering from NED university Karachi in 2010. Currently, she is
pursuing her PhD degree (FPGA based DSP system Design) from
Meharn UET. Mrs. Pathan worked as Assistant Manager (satellite
receivers’ design) in SUPARCO from March 2008 to February 2013.
Since then she serves as Assistant Professor in Quaid-Awam Univer-
sity College of Engineering Science and Technology Larkana.

Tayab D Memon  received a BE (Hons) Electronics Engineering (First

Class) and a PG Diploma Telecommunication and Control Engineer-
ing (First Class) from Mehran University of Engineering & Technol-
ogy, Jamshoro, Pakistan, in 2003 and 2006 respectively. He received
PhD from Royal Melbourne Institute of Technology (RMIT) Mel-
bourne Australia in 2012. Currently he is working as Associate Profes-
sor in the Department of Electronic Engineering, MUET. His research
interests include short word length DSP Systems, embedded systems,
and their FPGA-based implementation.

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