CMSC 411 Computer Architecture

Another MIPS64 ISA Quiz Fall, 2014

Dr. Michelle McElvany Hugue

Address Comments Anyone?

(1) DADDI R4, R0, # 6400 ;;; Make an integer 6400
(2) MTC1 F4, R4 ;;; copy bit pattern from R4 to F4
(3) CVT.L.D F4, F4 ;;; F4 has a float constant
(4) DADD R1,R0,R0 ;;; init byte counter to 0
(5) Loop: L.D F2,800(R1) ;;; F2 is array element,
(6) L.D F3,1600(R1) ;;; F3 holds array element
(7) SUB.D F5,F3,F2 ;;; perform subtraction
(8) ADD.D F5,F5,F4 ;;; perform addition of a constant
(9) S.D 3200(R1),F5 ;;; store the result
(10) DADDI R1,R1,#8 ;;; increment byte counter
(11) DADDI R5,R1,#-800 ;;; stop after the 100th iteration
(12) BNEZ R5,Loop ;;; branch while not done
(13) DADDIU R8, R0, #-32768 ;;; A fancy place holder–don’t analyze

MIPS is Magnificent!
The code fragment that follows was written for a byte addressable Big Endian MIPS64 machine. I hope you
enjoy answering a few questions about it.

1 Circle the numbers of all MIPS R-Type instructions in the code fragment. What MIPS instruction type
are the instructions that you did not circle?
Answers: Register 4, 5; Immediate 1, 3, 8, 9; Displacement 2, 6, 7, 10. At most 3 points of 10 if you
gave any other description of these instructions, such as ALU, Branch, Jump, Memory.
2 Suppose that the code fragment starts at address PC base. Write an expression for the address of the
next instruction to be executed after instructions (13).
Answer: PC base plus 52 since we have to skip 13 instructions at 4 bytes per instruction and we have
byte addressable memory.
3 In instruction (6), what are the last four bytes of the address of the half-word containing the displacement
1600? Assume that the last four bytes of the address of instruction (7) are 0x 0000 FFFC? Justify
your answer as always.
Answer: Since we have a Big Endian byte addressable memory organization, instruction (6) will span
addresses with the last four bytes given by 0x 0000 FFF8, 0x 0000 FFF9, 0x 0000 FFFA, and
0x 0000 FFFB. Since the immediate operand is in the two low order bytes of the I-type instruction,
the half-word (two bytes) corresponding to the immediate operand will have an address having the last
the last four bytes given by bytes 0x 0000 FFFA?
4 Are any additional assumptions necessary to ensure that this code exhibits the desired run-time behavior?
If you think not, circle the word: None. Otherwise, explain for full credit.
Answer: This is a teensy bit subtle. Apologies if there really is a problem with the code and I missed
it. The only assumption that I can see is that PC base needs to be 0 mod 4.

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5 What is the bit pattern in the 64 bit register R1 after instruction (1) has been executed? For brevity
and consistency, please express your answer in hexadecimal assuming that the least significant bit of
its binary equivalent is the rightmost bit, and the most significant bit of its binary equivalent is the
leftmost bit.
Answer: Fail! instruction (1) doesn’t modify R1. However, if we assume that I really meant the value
of R4 after instruction (1), then we must examine what happens when the bit pattern corresponding
to 640010 is sign extended. Either visit your favorite conversion program or do it by hand...no one
cares, but you should get 0x1900. After extending the sign bit of zero to make a 64 bit constant, you
have 0x0000 0000 0000 1900

6 What is the result of executing instruction (13)? Be as specific as possible, representing any numerical
result in hexadecimal.
Answer: The command uses immediate addressing mode. But, the 16-bit value in the immediate
field of the that instruction will not be sign extended because the instruction as a U for unsigned
present. That means that regardless of the value of the sign bit, the 16 bit (or 4 hex digit string) will
be zero filled. The original is 0x8000, which is the bit pattern of the most negative 16 bit number in
2’s complement. But, when we zero extend it to satisfy the unsigned operator, we will have our 64 bit
(8 byte) wide register R8 containing 0x 0000 0000 0000 8000.

7 Is the code fragment properly aligned in memory? If so, explain why. If not, what condition(s) must be
met to maintain the correct alignment of the instructions.
Answer: As discussed previously, all that I can see is that PC base needs to be 0 mod 4 because the
all MIPS instructions are 4 bytes long.

8 How many times is instruction (9) executed? Explain your answer for full credit.
Answer: Sorry, I’m not even attempting this with my migraine-in-progress. The intent was 100
iterations.

9 What does this code fragment do? No code or pseudocode. A few sentences should be sufficient.
Answer: It was intended to initialize each element of array C with a linear function of the corre-
sponding elements in two other arrays and the constant 6400. Computations go from index 0 to index
99.

10 This code fragment operates on the elements of the associated arrays in increasing index order. A
standard optimization is to access the array elements in decreasing order; that is, the last element in
memory is processed first. Determine what instructions, if any, need to be changed. Then, explain
why this is called an optimization.
Answer: The bytecounter needs to be initialized to the end of the arrays, with 8 subtracted to get
the next array element. The test to exit the loop merely requires comparison between the bytecounter
and zero, requiring one less instruction. Now, since there is always the possiblity of an off-by-one error
here, I’ll ask someone to write me the appropriate code fragment.

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The CODE of MIPS
Write down valid MIPS64 code fragments that satisfy the requirements given for each problem. When asked
for two valid fragments, you must do more than change the names of the registers to receive full credit. Or, if
no such fragment(s) can be constructed, explain why. You should assume that the MIPS64 implementation
is BigEndian.

B.1 Write two (2) valid MIPS64 code fragments that will store the sum of the 64-bit integers in registers
R2 and R3 at an address which is 256 more than the contents of register R6.
Answer: The purpose of this problem is to get you to recognize that displacement mode has one
drawback: dissimilar code fragments can refer to the same address in memory. There are several valid
answers; hopefully these will give you some ideas.

1. I think this is the most straightforward.

DADD R4, R2, R3

SD 256(R6), R4
2. This is just one of the many tricks that one can play with offsets. When the fragment ends, the
value of R6 will remain unchanged, register R7 will contain 56 more than R6, and the value in
R4 will be stored at the correct address.

DADD R4, R2, R3

DADDI R7, R6, #56
SD 200(R7), R4

B.2 Write a MIPS64 code fragment that will load register F3 with the double precision floating point number
at address 1024.

L.D F3, 1024(R0)

B.2 Write a MIPS64 code fragment that stores the product of the double precision floating point numbers
in registers F10 and F12 at memory address 8192.

MUL.D F8, F10, F12

S.D 8192(R0), F10

B.3 Write a MIPS64 code fragment with the post condition that F9 contains the double precision floating
point number located in memory at an address which is 57 bytes past the contents of register R20.

L.D F9, 57(R20)

B.4 Write a MIPS64 code fragment that puts a floating point zero (0) into register F0.

SUB.D F0, F0, F0

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B.6 Write a MIPS64 code fragment with the post condition that register F16 contains the result when
the pair of single precision floating point numbers packed into register F6 is multiplied by the single
precision floating point pair packed into register F16.

MUL.PS F16, F16, F6

B.7 Write a MIPS64 code fragment that transfers control to an instruction with label sandy when the value
in register F2 is less than or equal to that of F12.

Even I have to look this one up. We need one instruction that will determine if F2 is less than or equal
to F12...and it may be more convenient to check to see if F12 has a value greater than that in F2.
Then, we need to move to an instruction with label sandy based on the result of first instruction.

C.LE.D F2, F12

BCIT sandy

B.9 Write two (2) valid MIPS64 code fragments that will load register F3 with the double precision floating
point number at address 1024.

1. The most straightforward is

L.D F3, 1024(R0)

2. For a second version, we employ yet another trick to make displacement mode do the same job
as absolute mode.

DADDI R7, R0, #1024

L.D F3, 0(R7)

B.11 Write two (2) valid MIPS64 code fragments that put a floating point zero (0) into register F0.

1. More of the same tricks, eh?

SUB.D F0, F0, F0

2. Move a zero from an integer register to a floating point register. We don’t have to convert because
64 zeros is zero in both integer and floating point formats.

MTC1 R0, F0

B.12 Write one (1) valid MIPS64 code fragment that will pack register F9 with the two single precision
floating point numbers at addresses 2048 and 2052.

L.D F9, 2048(R0)

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B.13 Write a valid MIPS64 code fragment that would initialize F25 with the constant 42.5

DADDI R1, R0, #85

DADDI R2, R0, #2
MTC1 F1, R1
MTC1 F2, R2
CVT.L.D F1, F1
CVT.L.D F2, F2
DIV.D F25, F1, F2

B.14 Write a valid MIPS64 code fragment with the post condition that register F16 has the contents of the
memory address contained by register R9

LD R8, 0(R9)
L.D F16, 0(R8)

B.15 Write a valid MIPS64 code fragment that will initialize registers F12 and F13 with the contents of
register F16.
Note: at most half credit for using anything other than MIPS64 FP ALU instructions in your code
fragment..

SUB.D F2, F2, F2

ADD.D F12, F2, F16
ADD.D F13, F2, F16