IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-30,NO.
9, SEPTEMBER 1983
Univ. of California, Berkeley, 1983.
[52] A. R. Newton, “The simulation of large scale integrated circuits,”
Ph.D. dissertation, Univ. of California, Berkeley, July 1978; also
Univ. of California, Berkeley, MemoUCB/ERL M78/52, July
1978.
[53] J. Kleckner and A. R. Newton, “Advanced techniques for iterated
timing analysis,” in preparation.
[54] D. Senderowicz, “An NMOS integrated vector-locked loop,” Univ.
of California, Berkeley, Memo. No. UCB/ERL M82/83, Nov. 12,
1982.
[55] J. White and A. Sangiovanni-Vincentelli, “RELAX2: A new wave-
form relaxation approach for the analysis of LSI MOS circuits,” in
Proc 1983 Int. Symp. Circuits Syst., May 1983.
[56] E. Lelarasmee and A. Sangiovanni-Vincentelli, “Some new results
on waveform relaxation algorithms for the simulation of integrated
circuits,” in Proc.1982 IEEEInt. Large-ScaleSyst.Symp., pp.
371-376, Oct. 1982.
[57] J. Kaye and A. Sangiovanni-Vincentelli, “Solution of piecewise
linear ordinary differential equations using waveform relaxation and
Laplace transforms,” in Proc. 1982 Int. Conf. Circuits Comput., pp.
CAzM: A Circuit Analyzer with
Macromodeling
WILLIAM M. COUGHRAN, JR., ERIC GROSSE, AND DONALD J. ROSE
Abstract -A prototype circuit simulator, based on a revised formulation perform the specified logical function. Circuit analysis is
of the circuit equations, is described. The formulation is basedon func-
tional models of active elements, which can be derived from either equiva-
lent-circuit or black-box models. The implementation is oriented towards
the simulation of digital MOS circuits and takes advantage of the special
form of suchcircuits. Some oftheimplementation issues are discussed, ~91.
particularly the hierarchical structuringof the circuit equationsand the use
of splines to facilitate macromodeling; continuation methods for computing
transfercurvesare also discussed.Finally,theresults of computational
experiments are presented.
I. INTRODUCTION
D IGITAL integrated circuits may be viewed as a col-
lection of transistor devices interconnected topologi-
cally on asubstrate silicon chip. Although the circuit is
designed to perform two-valued logical functions, the de-
tailed electrical behavior of the individual devices, and
therefore the circuit itself, is analog. That is, the basic
physics describing the devices and the circuit behavior is
modeled by differential equations.
The task of circuit analysis is to solve these differential
equations accurately enough to predict the circuit’s dy-
namic analog behavior [3], [13]. This insures that the de-
vices and interconnections will function as required to
Manuscript received January 4, 1983; revised March 21, 1983.
The authors are with the ComputingMathematics Research Depart-
ment, Bell Laboratories, Murray Hill, NJ 07974.
0018-9383/83/0900-1207$01.00 01983 IEEE
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1207
180-183, Oct. 1982; also IEEE Trans.Circuits Syst., to be pub-
lished.
[58] M.Guariniand 0. A. Palusinski “Integration of partitioned dy-
namic systems using waveform relaxation and modified functional
linearization,” 1983 Summer Computer Simuhtion Proc., July 11-13,
1983.
[59] T. Y. Feng, “A survey of interconnection networks,” Comput., no.
11, pp. 12-27,1981.
[60] D. D. Gajski, D. J. Kuck, and D. A. Padua,“Dependence driven
computation,” Proc. IEEE SpringCompcon, pp. 168-172, Feb.
1981.
[61] D. A. Padua, D. J. Kuck, and D. H. Lawrie, “High-speed mul-
tiprocessors and compilation techniques,” IEEE Trans.Comput.,
vol. C-29, no. 9., pp. 763-776, Sept. 1980.
[62] D. H. Lawrie, “Access and alignment of data in an array processor,”
IEEE Truns. Comput., vol. C-24, no. 12, pp. 1145-1155, Dec. 1975.
[63] J. T. Deutsch and A. R. Newton, “Data-flow lbased behavioral-level
simulation and synthesis,” Proc. IEEE ICG4D Con!., Sept. 1983.
[64] J. T. Deutsch, “Multiprocessorcomputer architecture,” Worcester
Polytechnic Institute, MQP Rep. June 1980.
often subdivided into three phases called circuit, timing,
and logic simulations; a number of simulation programs
based on various formulations and algorithms are in use
The logic phase simulates the binary behavior of the
circuit at the transistor or gate level. Timing simulation
attemptsto analyze the various de1a:ys in the circuit’s
critical paths without solving the differential equations to
great accuracy. Circuit simulation solves the differential
system accurately enough to predict detailed electrical
properties.
Circuit analysis provides several interesting numerical
problems. This paper tersely describes some of the numeri-
cal procedures incorporated in CAzM, a prototype circuit
simulator under development. Section I1 focuses primarily
on the formulation of the circuit equations with special
emphasis on MOS transistor circuits. Since the transient
aspects of the simulation reduce numerically to solving a
sequence of static operating-point prob’lems, the formula-
tion of the static case is given. We briefly discuss in Section
I11 a damped-Newton method that has proven effective in
simulation. Continuation methods for computing static
transfer curves are explained in Section IV. Section V
contains a briefoverview of variation-diminishing tensor
splines, which we use for functional models of transistors
1208
and gates. The models for MOS transistors and a simple
NAND gate are described in Section VI. The results of
computational experiments are presented in Section F'II.
Finally, in Section VIII, some conclusions are drawn.
11. FORMULATION
Circuits are governed by Kirchhoff's current and voltage
laws as well as constitutive relations. The current law is
Ai = 0
where A E R n X mis the circuit's reduced-incidence matrix
[4]and i E Rmis the vector of branch currents. The volt.age
law implies that
u = ATu
where u E R" and u E R" are the node and branch vcdt-
ages, respectively. The constitutive relations are of the form
K ( i , u ) = 0 E R"
which becomes i = f( u ) for voltage-controlled devices.
If these equations are linearized around some pent
( uo, uo, io), the linearized constitutive equations are
KiSi+K,6u=s
where Kiand K , are m X m matrices given by Ki = dK/ ai
and K , = d K / d u , respectively and s is a source vector. The
equations can be summarized in matrix notation as
Mo is the tableau matrix popularized by Hachtel, Braytcln,
and Gustavson [8]. Note that M,, has a trivialblock 1,U
factorization, corresponding to the substitution u = ATu, as
Let
"=[A
K~ K , A ~
0
We call M , the reduced-tableau matrix.
I.
In the tableau approach, the linear system involving .M0
issolved bya general sparse solver that recognizestile
special ( - 1,0,1) entries in A but otherwise takes litlle
account of the nature of the circuit. The "elimination
order" is determined by heuristics that attempt to optimize
the arithmetic and memory costs of the equation solution;
these heuristics may not preserve the "locality" of the
circuit equations.
Most formulations of the network equations can be
derived by starting with the tableau matrix, or the reduccd
form, and performing various block LU factorizations [dl],
[5]. In particular, the nodal and modified-nodal[ l l ] forrnl-
lations can be obtainedin this way. Moreover, the formula-
tion can be extended to allow state variables. The circuit
equations have hierarchical character, reflecting the u r t -
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IEEE TRANSACTIONS O N ELECTRON DEVICES, NO.
VOL. ED-30, 9, SEPTEMBER 1983
SUECIRCUIT
Fig. 1. Hierarchical view of circuit.
derlying circuit [14], [9]; we propose assembling the equa-
tions in a hierarchical fashion.
A circuit 'may be viewed as a collection of I subcircuits,
some of which may consist of individual devices such as
transistors, whose terminals are connected together at nodes
(see Fig. 1); let u be the vector of voltages at the intercon-
nection nodes. Each subcircuit Sj can beviewed as a
multiterminal element with its terminals attached to nodes;
each terminal has an associated voltage, which is inherited
from the node the terminal is connected to, and current.
Let ij be the vector of 3 ' s terminal currents. Let iT=
(ir, * - ,iT) be the blockvector of currents. Then Kirch-
hoff's current law at the interconnections is still Ai = 0
where A is the appropriate incidence matrix. Moreover,
v = ATu where uT = (UT,. -,UT)
. is the block vector of volt-
agedifferences. Finally, there is a constitutive relation
K ( i , u ) = (K,(z,, u,); * . , K / ( i / ,u , ) ) ~ =0. Matrix assembly
can be done with the usual two-terminal elements, devices,
or subcircuits; transient problems can be incorporated by
viewing K as a functional.
Let us consider the special case of an MOS transistor in
some detail. Transistors canbe dealt with individually
when we perform Gaussian elimination. We will consider a
block-elimination strategy that treats a particular transistor
T, in the circuit.
Suppose the terminals of transistor T, are attached to
four nodes n,, . * n4, not necessarily distinct. One terminal
a ,
is distinguished as the reference terminal; the selection of
the terminal is arbitrary so assume the terminal connected
to n , is the reference. Note that the reference terminal need
not be grounded and the reference terminal of one transis-
tor need not be connected to the reference terminal of
another attached transistor. There is a current and voltage
associated with each terminal. However, Kirchhoff's cur-
rent law insures that Cij = 0 so only three currents need
enter into the constitutive relation for T,. Similar consider-
ations dictate the dependence of the constitutive relation
upon the terminal voltages; u2 - u,, u3 - u 2 , and u4 - u1
are the relevantdifferences of node voltages. Thus the
general constitutive relation for T, takes the form
f(i,, i,, i,, u2 - u l , u g- u,, u4 - u,) = 0 .
The part of the reduced incidence matrix associated with
COUGHRAN et ai.: CAZM: A CIRCUIT ANALYZER WITH MACROMODELING
where the three columnscorrespond to the dependency
edges introduced by the voltage differences.
We can write
where Kil and K,, correspond to the constitutive relation
for Tl while K i R and K , , represent the remainder of the
circuit. Let us partition A , i , and u as A = [ A l A , ] ,
ir= (iF, z i
) ,u T =
and (UT,
u ; ) where i, E R 3 and u1 E R4.
We then can write the reduced-tableau matrix as
The formal block factorization indicates how the transistor
"assembles" into the lower right block.
We can select other transistors T/ and eliminate them.
After eliminating 7 transistors, we obtain a further reduced
matrix
L j=l
The 1;'s can share nodes so the - Aj KG1KUjAT'~ can
overlap. Thus,the elimination of transistors involves a
matrix-assembly process not unlike finite-element tech-
niques [15].
Let us consider the form of the constitutive relation
K j ( i J ,u j ) for a subcircuit S,. Let uj be the vector of
termnal voltages associated with q; these terminal volt-
ages can be viewed as boundary conditions for Sj. Simi-
larly, let ij be the vector of terminal currents associated
with Sj. Then S, satisfies local relations
qj(ij, sj,uj; u,) = o
where A j , qj,uj, and {,are theappropriate incidence
matrix, the generalized constitutive relations, and the inter-
nal node voltages and currents, respectively. Note that Aj is
not a part of the incidence matrix governing the terminal
connections of the circuit. The internal node voltages uj
and currents {,may be thought of as states.
The nMOS-NAND circuit shown in Fig. 2 provides an
example of subcircuit assembly. Let u l , u 2 , and u,, be the
node voltages that correspond to the two input and one
output terminals, respectively. Each of the transistors has a
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1209
VDD
P
+INTERNAL NODE n
Fig. 2. NAND circuit and logic symbol.
drain-to-source current so there are three internal currents
- ,s3
11, . thatcorrespond to the groundedenhancement,
the other enhancement, and the depletion transistors, re-
spectively. There is also the current i o associated with the
output terminal; since we are considering the static case,
we neglect the zero currents associated with the gates of the
two enhancement transistors. Then Kirchhoff's current law
for the NAND subcircuit is
Note that the second equation states that the output cur-
rent is the difference of two transistor currents. The con-
stitutive relations for the NAND are just the constitutive
relations for the individual transistors.
If each subcircuit or deviceisvoltage controlled, the
assembly process will terminate with the nodal matrix.
Elements that are not voltage controlled are ignored in the
assembly phaseandanextended set of equations must
then be solved. Fortunately, many interesting circuits com-
posed of MOS transistors are voltage controlled.
If the internal voltages and currents of a subcircuit S, are
not of interest, a macromodel (a function) characterizing
the voltage and current behavior at q's terminals can be
used; in this way, unnecessary computaticrnof values inter-
nal to a subcircuit may be avoided. A macromodel is an
approximation to the constitutive relation K j . The voltage
and current behavior at the terminals may be sampled by
independently analyzing q. Section VI discusses the con-
struction and use of a NAND macromod~:l in CAzM.
111. DAMPED-NEWTON'S METHIOD FOR
OPERATING-POINT ANALYSIS
The operating-point problem is simply a system of non-
linear equations
g( u ) = 0.
The form of g is described in the previous section; g is a
poorly-scaled sparse nonlinear system. Note that u may
represent currents and voltages in this section. We propose
using a damped-Newton algorithm [l]for solvingthese
equations.
1210 IEEE TRANSACTIONSON ELECTRON DEVICES, VOL. ED-30, NO. 9, SEPTEMBER 1983

The Newton step for such a problem is found by solvi.xg differential equations
the Jacobian equations
guu’ + A%, =0
JkXk = - gk
where Jk = g,( uk) = ag( u k ) / d u and gk = g( uk).The nC:Xt
l\u’\\$ + \x12=1.
iterate is taken as The differential equations can be viewed as an initial-value
problem if the operating-point problem g ( u , A,) = 0 is
U k + l = uk + tkxk solved first.
where 0 < tk ,<1is chosen to satisfy the sufficient decrease Suppose we know the solution ( u j , A j ) and its tangent
condition (u;, X j ) for some sj and now wish to advance from sj to
This can be done by making the nonlinear equations
g ( u j + lA, j + l ) = 0 and the pseudo arc-length equation

for fixed S > 0, which we usually take to be the machine u~’~(u~+~-u~)+A’~(A~+~-A~)=s~+~-s~~As~

epsilon. If tk =1, the algorithm is the usual Newton’s
method. However, the algorithm damps the Newton slep
when tk < 1.
The strategy for computing t , is analogous toa llne
search, but attempts to minimize the search effort. In
particular, if the previous damped-Newton step satisfied
the sufficient decrease condition with t k , a trial value for
the next step is selected as
obtained by a forward-Euler discretization of the arc-length
equation, hold usingNewton’s method. This method,
popularized by Keller [12],can be viewed as a forward-Euler
scheme with Newton as a corrector; s is no longer arc-length
but is a pseudo arc-length. The initial guess is given by the
forward-Euler equation

The Jacobian for the augmented nonlinear system is

Iterative application of this formula causes the tk’s to
approach one. If astep does not satisfy the sufficient
decrease condition then we try a sequence of decreasing
steps, based on the last successful step tk-1 This formal block factorization implies that
ti’)= tk-1(~IIUkIl/(lXk\l)j2’~*

-
f o r j = 1, .,I until the decrease condition is satisfied; 1’ is a
given integer, which we usually take as nine. This sch.c:me should be solved by the following steps:
decreases the step slowly for small j but then quic.kly 1) Solve g u y = gh and g,z = r ;
reduces it for largerj. 2 ) SA = ( t - U j ‘ Z > / ( X j - ujTy);
This algorithm with this method of picking tk is globdly 3) S u = z - S A y .
convergent if g satisfies certain technical assumptions (:see
[l]for details); we are investigating these assumption,$ in Note that gu may be ill-conditioned for some A)’s.
the circuit context. Since portions of a circuit may be Once ( u ~ +A~j +,l ) is known, we mustcompute
“off”, isolated rows and columns of the Jacobian mag be A)+l) in order to take another step in s. This can be
zero as well as the corresponding components of gk; defla- done using they = g;lgh computed above and forming
tion of these singular systems suffices to compute xk jn a
bounded way. A’= f Ilyll;
u’ = A‘y
Iv. CONTINUATION FOR STATIC TRANSFER where the sign of A’ is chosen in the appropriate way.
ANALYSIS The means of selecting Asj obviously influences the
We are interested in solving the transfer analysis prob- efficiency of the overall procedure. We find that a modifi-
lem given by cation of algorithm I11 in [ l o ] iseasy to implement and
effective; its main advantage is that no quality measure for
g(u,A)=OforXE[A,,A.]. the corrector iterates need be computed. For brevity, we
In other words, we are interested in finding u ( A ) for a will defer a detailed discussion of the steplength algorithm
range of input voltages A, < A G A,. We have found con- and computational results to a later paper.
tinuation techniques attractive for computing transfer With many circuits, it is possible to enforce only
curves. g(ui+l, = 0 at each point and use an initial guess
Parametrize the system by arc-length based on the forward-Euler equation. (Essentially, any
circuit where a particular value of A gives a unique u can be
g ( u ( s > ,A(sN = 0 treated in this way.) This saves an extra solvefor each
and then differentiate to obtaina system of ordinary Newton iteration. This is an option in CAzM.

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COUGHRAN et a[.: CAZM: A CIRCUIT ANALYZER WlTH MACROMODELING 1211

Our experience with continuation for transfer analysis

indicates that the input voltage A should be stepped in
tenths of a volt in some parts of an interval to ten-thou-
sandths of a volt when a digital circuit is changing a
latched state, The user cannot preselect easily an adequate
set of sample values for A to properly resolve a transfer
curve. Continuation does this automatically at a low cost.
I

v. SPLINES FOR MODELING

4
E l
._
Various models have been suggested for active circuit
elements, including analytic and table look-up schemes.
We advocate the use of tensor-product splines that pre-
serve mononicity.
We begin with the problem of approximating a uni-
variate function f on the interval [ a , b]. Suppose we are
given a knot sequence C
a = t , = t , = t , < * * . < tn-2 = t n P l= t , = b . 0 I 2 3
V d s ( VOLTS I
Let
Fig. 3. Transistor static currenti = f( Vds)for several Vgsvalues.
PX(d = {At-”’ 2
ift>x
otherwise. VI. MACROMODELS
Then the B-splines of order three (piecewise quadratics) are Thestatic transistor model, neglecting substrate cur-
defined by rents, is simply given by
= (ti+3 - t i > [ t i ,t i + l , ti+2, ti+,lpx is=-id=f(Uds,Ugs,Ub.~)

where [ti,. . .,ti+ ,] indicates the third-order divided dif- ig=0

ference (see [2] for details). The variation-diminishing spline
of Schoenberg is we call this model a macromodel since it is not an equiva-
lent circuit. We use a semi-analytic enhancement-MOS
S ( X ) = C f (ti*)Bi(x) transistor model [16], [17] as the source of data for the
splines, although experimental data or the results from a
where ti* = ( t i + ti+,)/2. Note that computing S does not semiconductor-modeling program [6] could be used. A
require the solution of a linear system but does require square-root transformation of variables isused in u to
function values at specific points. gs
reduce the number of sample points in that variable since
S has several important properties: 1) [If - SI/ = O(At2) there is quadratic behavior in ugs. Figs. 3 and 4 illustrate
where At = max - til; 2) S preserves the monotonicity the spline approximation to the transistor.
o f f ; 3) S E C1; and 4) constructing S is a linear process. We obtain a depletion-transistor model by adjusting the
B-splines of higher order (piecewise cubics or higher) still flat-band voltage ufb of our enhancement model, that is
give a second-order approximation so piecewise quadratics
= f ( U d s , ugs + u f b , u b s ) .
are sufficient. The facts that S preserves monotonicity and Using the quasi-static approximation, the transient tran-
S is easily differentiated make possible the use of damped- sistor model can be written as
Newton methods [l]; moreover, by linearly extending S
outside of [ a , b ] we avoid constraints in the Newton proce-
dure.
Any linear univariate approximation process can be
extended to several variables through the use of tensor
products; the details of the computational method are Each of the components of q can be modeled with a tensor
described in [7]. For the variation-diminishing spline, a spline.
three-dimensional tensor variant with the same knotsin Let us consider the construction of astatic NAND
each variable is given by macromodel. (The usual nMOS-NAND circuit is shown in
Fig. 2.) The basic idea is to supply voltages on the two
s(x,Y , z > = C f ( t r 9 tj*,t : ) B , ( x ) B , ( y ) B , ( z ) input pins andthe usual output pin. Obviously, if the
ijk
supplied output voltage is not the one: that wouldhave
since the approximation operator is essentially the identity. occurred with the output voltage as an unknown then there
The computational costs of a tensor spline in p dimen- will be a residual current associated wit.h the output lead.
sions is O(nini)space if there are n , sample points for the By running CAzM with various sample voltages for the two
ith variable and O ( 3 P ) time for one evaluation. inputs and one output, we can obtain a tensor spline that

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1212
-a
E UI’O
.-
0
Vg,(VOLTSI
Fig. 4. Transistor static currenti = f ( V,,) for several vds values.
models the residual current
io = f ( u 1 , u 2 , u o ) .
Fig. 5 illustrates the NAND macromodel. Note that we can
writef as a function of node voltages because the NAN13 is
always connected to ground.
There is a node between the two enhancement tran.r,is-
tors, node n in Fig. 2, that is an important unknown .lor
determining the output voltage but does not usually con-
nect to other devices in the circuit. In other words, nodc n
is an isolated node whose value is not used outside of the
NAND. Hence, if the NAND is replicated several times in
a circuit, the value of the isolated node is computed each
time. The macromodel incorporates the output behawlor
once and for all, eliminating the need for computing Ihe
isolated node’s value. By using the macromodel in operat-
ing-point computations, it is possible to only solve for h e
unknown output voltage, reducing the number of utn-
knowns by a factor of two.
A further advantage of the NAND macromodel is ihe
character of the nonlinear equations that must be solved.
TheNAND expressedwith three transistors can ca.use
difficulties since enhancement transistors have a dou1,le
zero at ugs = 0. In particular, linear convergence of New-
ton’s method is observed when both of the enhancemlcnt
transistors are operating in the subthreshold range. ‘The
computational experiments described later demonstrate t lis
point.
The NAND macromodel is a three-dimensional temmr
spline so its computational complexity is the same as [he
transistor’s. Hence, the macromodel not only reduces fhe
number of unknowns in the nonlinear system but it :e-
places three function evaluations by one.
Static inverter and NOR macromodels can be ccln-
structed from simple linear combinations of transismr
models. Alternatively, we could construct a spline macro-
model representing an inverter or a NOR gate in order to
reduce the number of spline functions evaluated; for exa m-
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-30, NO. 9, SEPTEMBER 1983
0.2:
u1=5
u2 = 4
i UI=:
-a
.--
E C
-0.2!
I 5
OUT ( V O L T S )
Fig. 5. NAND macromodelcurrent.
ple, it takes three transistor evaluations to compute the
residual current for a simple NOR circuit whereas a specific
spline macromodel would require the same computational
effort as a single transistor evaluation. An XOR can be
computed via a NAND macromodel anda transistor
evaluation or, as before, a specific spline macromodel can
be constructed at the cost of a four-dimensional fit.
VII. NUMERICAL EXPERIMENTS
Wehave run experiments on several circuits, such as
combinational circuits of various sizes, memory cells, trig-
ger elements, and shift registers. The dramatic effectiveness
of macromodeling can be best demonstrated with a one-bit
full adder composed of 9 NAND elements (see Fig. 6);
larger ripple-carry adders can be constructed from the
one-bit adder.
We performed operating-point analyses with a series of
larger and larger adders. In the first set of experiments, the
input node voltages were taken to be zero volts as were the
carry-out and output node voltages of each one-bit adder
stage; a constant interior guess of V,,/2 was used for the
remaining nodes. The results are summarized in Table I.
In the second set of experiments, the input node voltages
were taken to be zero volts and the other node voltages
wereguessedaszero and V,, based on a switch-level
simulation. The results are summarized in Table 11.
The stopping criteria resulted in node voltages accurate
to a minimum of five digits. All computations were per-
formed in single precision on a Cray-1 computer.
The initial guess influences the number of damped-
Newton iterations needed; we believe that the results of a
switch-level simulator should be used as the initial oper-
ating-point guess.However, the method convergeseven
when the initial guessis poor and we observe similar
behavior when something other than zero is input to the
adders.
The first line in each table above shows the work neces-
sary tocompute the operating point when the NAND
elements in the one-bit adder are represented by one
COUGHRAN et al.: CAZM: A CIRCUIT ANALYZER WITH MACROMODELING 1213

TABLE I1

-+Y I

OUT
Bits

1
1
Work for full adders with switch-simulator guess
Transistors Unknowns Newtons

27
27
18
9
7+15
4 4
Macromodel?

u 4 - 108 36 4 4
216 8 72 4 4
CIN -I 16 432 144 4 4 Yes
Fig. 6. One-bit full adder circuit. 32 288 864 4 4. Yes

TABLE I connected to inputs and outputvoltages aS the previous set

Work for full adders with interior constant guess
Bits 1 Transistors 1 Unknowns I Newtons I Functions 1 Using NAND
1 Macromodel?
1 1 27 I 18 I 35+9 I 71
1 27 9 10 17
4 108 36 10 17
8 216 72 10 17
16 432 10 144 17
32 864 288 10 17
depletion and two enhancement transistors. Thirty-five and
seven damped-Newton steps in Tables I and 11, respec-
tivelygive the correct answer to three digits at each
NAND’s output node; yet it takes another nine and fifteen
Newton steps in Tables I and 11, respectively to settle the
values at -theinterior nodes of the NAND’s. The other lines
in each table show what happens when the NAND is
represented by a spline macromodel. Obviously, much less
work is required with the macromodel since fewer Newton
steps are taken and there are half as many node voltages to
solve for.
VIII. CONCLUSIONS
We have discussed the formulation of the circuit equa-
tions, a damped-Newton method for computing operating
points, a continuation method for calculating transfer
curves, and the use of variation-diminishing tensor splines
for modeling devices and gates. We have not described the
transient-analysis problem although the formulation easily
accommodates the time-dependent problem by viewing the
constitutive relations K ( i , u ) = 0 as functionals instead of
functions. CAzM currently performs transient analysis by
using the backward-Euler method to generate a series of
operating-point problems.
We have only begun to research the problem of macro-
models involving time dependence. Thestatic transistor
model is easily extended to a transient model by the
quasi-static approximation. However, it is not yet clear
under what circumstances quasi-static time macromodels
for gates are applicable.
Numerical logic simulation giving voltage levels instead
of switchlevels (“on” or “off”) is another possibility.
Consider theadders described in ’ the previous section.
There are no cycles in the dependency graph of the circuit
so it is possible to evaluate the output voltages of NAND’s
connected only to inputs, then output voltages of NANDs
of NAND’s, and so forth. At the end of this process, the
adders’ output voltages would be determined. Also, the
question of how the dependency graph of the circuit should
No be used in general is still being considered.
Yes
Yes ACKNOWLEDGMENT
Yes
Yes The authors appreciate the advice and efforts of R.
Yes Bank, W. Fichtner, J. Gannett, J. Hodgins, and G. Taylor.
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