Associate in Aviation Electronics Technology: Philippine State College of Aeronautics

Philippine State College of Aeronautics
Associate in Aviation Electronics Technology
MODULE 4 Digital Techniques Flexible Modalities

1
LEARNING OUTCOMES:
• 3: Demonstrate a practical ability to accurately identify, carefully formulate, digital number systems,
effectively solve complex logic gate circuit problems by properly applying basic principles and
standard method to digital electronics in aircraft.
• 4: Sketch and accurately interpret a pure logic circuit diagram of the graphical linear relationship
between logic gates and truth tables.
CLO • 9: Identify and properly apply technical concepts and practical terms used in the avionics field.
• 10: Comprehend and explain the proper procedures to resolve digital electronic circuits.
• 1: Demonstrate the fundamental theory and working principles of Logic gates.

• 2: Solve efficiently any fundamental problem involving on complex Logic circuits.
MLO • 3: Demonstrate and properly explore the practical applications of modern Logic circuits in aviation
electronics.
• 8: Investigate and explain Gate operations AND, OR, NOT, NAND, and NOR.
• 9: Analyze and evaluate the Digital Logic Gates Building Blocks along with the symbols, truth tables
TLO which describe the most common gates operation.
Weeks Topics/Activity Allotted Hours

Logic gates 1.7 Hrs
5 Activity No. 1 30 mins.
Combinational of logic gates 1.7 Hrs
Activity No. 2 30 mins.

2
CONTENTS
Introduction........................................................................................................................................4
1.0 Logic gates theory.......................................................................................................................4
1.1 The AND gate.............................................................................................................................4
1.2 The OR gate................................................................................................................................6
1.3 NOT gate ...................................................................................................................................8
1.4 The NAND gate.........................................................................................................................10
1.5 The NOR gate...........................................................................................................................10
1.6 The exclusive OR gate..............................................................................................................11
1.7 The exclusive NOR gate............................................................................................................11
1.8 Combinational of Logic gates.....................................................................................................12
1.8.1AND-OR pattern...................................................................................................................12
1.9 Summary ...................................................................................................................................17
1.11 Key Points ...............................................................................................................................17
Activity..............................................................................................................................................17
Honesty Clause...............................................................................................................................18
Rubrics.............................................................................................................................................19
References.......................................................................................................................................20

3
INTRODUCTION
A decision-making capability based on a variety of different factors is crucial for the safe operation
of a modern aircraft. So it is not surprising that today's logic systems are widely used in aircraft. In
this Module we introduce the basic building blocks of digital logic circuits (AND, OR, NAND, NOR,
etc.) along with the symbols and truth tables describing the operation of the most common logic
gates. We then demonstrate how these gates can be used before moving on in order to introduce a
simple combinational logic circuits.
1.0 LOGIC GATES THEORY
 In digital systems, the logic gate is the basic building block. With binary numbers, logic gates
operate. All voltages used with logic gates are either LOW or HIGH.
 A HIGH voltage in this topic would mean a binary 1. A LOW voltage means a 0 binary. Only
HIGH voltages (called 1s) or LOW (ground) voltages (called 0’s) will respond to these
circuits.
 Using only three basic logic gates, all digital systems are constructed. The AND gate, the OR
gate, and the NOT gate are what these basic gates are called. This topic deals with these
essential logic gates, or functions
1.1 THE AND GATE
 The gate AND is called "everything or nothing’’. In Figure 1, the schematic shows the idea of
the AND gate. Only when both input switches (A and B) are closed will the lamp (Y) light up.
For switches A and B, all the possible combinations are shown in Figure 1. The table in this
figure is referred to as a table of reality. The truth table shows that the output (Y) is enabled
only when both inputs are closed.
Input /Switches Output

A B Lights
Open Open NO
Closed Open NO
Open Closed NO
Closed Closed YES
Figure 1
Circuit and Truth Table of AND Gate

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 In Figure 2, the standard logic symbol for the AND gate is drawn. This symbol displays
entries as A and B. This is the symbol for an AND gate with 2 inputs. Figure 2 shows the
Truth table for the 2-input AND gate. The inputs are indicated as binary digits (bits).
 Note that only when both input A and input B are 1 will the output be 1. Binary 0 is defined as
voltage which is LOW or ground. Binary 1 is defined as a HIGH voltage. In this topic, a HIGH
voltage will mean about + 5 volts (V) if the integrated circuits (ICs) being used are from the
TTL family.
Inputs
A B Output
0 0 0
1 0 0
0 1 0
1 1 1
Truth Table of 2-input AND Gate
Figure 2
2 input AND gate and its Truth Table
 The Boolean expression is read as A AND (. means AND) B equals the output Y. The dot ( . )
means the logic function AND in Boolean algebra, not multiply as in regular algebra,
Sometimes the dot ( . ) is left out of the Boolean expression. The Boolean expression for the
2-input AND gate is then:
o Y=AB or Y=AB
Example Problem:
1. Write the Boolean expression for a 3-input AND gate.

2. Draw the logic symbol for a 3-input AND gate.
3. Draw a truth table for a 3-input AND gate
Solution
1. Y=A.B.C or Y=ABC
2.

5
3.
Inputs Output
A B C Y
0 0 0 0
1 0 0 0
0 1 0 0
1 1 0 0
0 0 1 0
1 0 1 0
0 1 1 0
1 1 1 1
1. 2 THE OR GATE
The OR gate is called the “any or all” gate. The schematic in Figure 3 shows the idea of the OR
gate. The lamp (Y) will glow when either switch A or switch B is closed. The lamp will also glow
when both switches A and B are closed. The lamp (Y) will not glow when both switches (A and B)
are open. All the possible switch combinations are shown in Figure 3 truth table. The truth table
details the OR function of the switch and lamp circuit. The output of the OR circuit will be enabled
(lamp light) when any or all input switches are closed.
Input /Switches Output

A B Lights
Open Open NO
Closed Open YES
Open Closed YES
Closed Closed YES
Truth Table OR gate
Figure 3
Circuit and Truth Table of OR Gate
 The standard logic symbol for an OR gate is drawn in Figure 4. Note the different shape of
the OR gate. The OR gate has two inputs labelled A and B. The output is labelled Y. The
shorthand Boolean expression for this OR function is given as Y=A + B.
 Note that the plus (+) symbol means OR in Boolean algebra. The expression (Y=A + B) is
read as A OR (+ means OR) B equals output Y. You will note that the plus sign does not
mean to add as it does in regular algebra.

6
Inputs
A B Output
0 0 0
1 0 1
0 1 1
1 1 1
Truth Table OR gate
Figure 4
2 input OR gate and its Truth Table
 The Boolean expression is read as A OR (+ means AND) B equals the output Y. The plus (+)
means the logic function OR in Boolean algebra, not addition as in regular algebra,
Sometimes the dot (+) is left out of the Boolean expression. The Boolean expression for the
2-input OR gate is then:
o Y=A+B
Example Problem:
4. Write the Boolean expression for a 3-input OR gate.

5. Draw the logic symbol for a 3-input OR gate.
6. Draw a truth table for a 3-input OR gate
Solution
1. Y=A+B+C
2.

7
3.
Inputs Output
A B C Y
0 0 0 0
1 0 0 1
0 1 0 1
1 1 0 1
0 0 1 1
1 0 1 1
0 1 1 1
1 1 1 1
1.3 NOT GATE (BUFFERS)
 A NOT gate is also called an inverter. A NOT gate, or inverter, is an unusual gate. The NOT
gate has only one input and one output. Figure 4 illustrates the logic symbol for the inverter,
or NOT gate.
Figure 5
Typically NOT gate Symbol and its Truth Table
 The process of inverting is simple. The input is always changed to its opposite. If the input is
0, the NOT gate will give its complement, or opposite, which is 1. If the input to the NOT gate
is 1, the circuit will complement it to give a 0. This inverting is also called complementing or
negating. The terms negating, complementing, Buffer and inverting all mean the same thing.

8
 The Boolean expression for inverting is shown in Figure 6. The expression A = A reads as A
equals the output not A. The bar over the A means to complement A. Figure 6 illustrates
what would happen if two inverters were used. The Boolean expressions are written above
the lines between the inverters. The input A is inverted to A (NOT A). The A is then inverted
again to form A (not not A) .The double inverted (A) is equal to the original A, as shown in
Figure 6. In the shaded section below the inverters, a 0 bit is the input. The 0 bit is
complemented to a 1. The 1 bit is complemented again back to a 0. After a digital signal goes
through two inverters, it is restored to its original form.
Figure 6
Inverting processes
Example Problem
1. What is the output at point (e) if the input (a) is a 0 bit?
Solution
1. The output at point e is 0.

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1.4 THE NAND GATE
 Consider the logic diagram on Figure 7. An AND gate is connected to an inverter. Inputs A
and B are ANDed to form the Boolean expression (A .B). The (AB) is then inverted by the
NOT gate. On the right side of the inverter, the over bar is added to the Boolean expression.
The Boolean expression for the entire circuit is Y=A .B. It is said that this is a not-AND or
NAND circuit.
Inputs
A B Output
0 0 0
1 0 0
0 1 0
1 1 1
Figure 7
The NAND Gate ant it’s Truth Table
 The standard logic symbol for the NAND gate is shown in the diagram in Figure 6.
 Note that the NAND symbol is an AND symbol with a small bubble at the output. The bubble
is sometimes called an invert bubble. The invert bubble provides a simplified method of
representing the NOT gate shown in the top diagram in Figure 6.
1.5 THE NOR GATE
 Consider the logic diagram in Figure 8. An inverter has been connected to the output of an
OR gate. The Boolean expression at the input to the inverter is (A+B). The inverter then
complements the ORed terms, which are shown in the Boolean expression with an over bar.
Adding the over bar produces the Boolean expression Y=A+B. This is a not-OR function. The
not-OR function can be drawn as a single logic symbol called a NOR gate. The standard
symbol for the NOR gate is illustrated in the bottom diagram of Figure 8. Note that a small
invert bubble has been added to the OR symbol to form the NOR symbol.
Inputs
A B Output
0 0 1
1 0 0
0 1 0
1 1 0
Figure 8
The NOR Gate ant it’s Truth Table

10
1.6 THE EXCLUSIVE- OR GATE
 The exclusive-OR gate is referred to as the “any but not all” gate. The exclusive-OR term is
often shortened to read as XOR. A truth table for the XOR function is shown in Figure 9.
Careful examination shows that this truth table is similar to the OR truth table except that,
when both inputs are 1, the XOR gate generates a 0. The XOR gate is enabled only when an
odd number of 1s appear at the inputs. Lines 2 and 3 of the truth table have odd numbers of
1s, and therefore the output is enabled with a 1. Lines 1 and 4 of the truth table contain even
numbers (0,2) of 1s, and therefore the XOR gate is disabled and a 0 appears at the output.
The XOR gate could be referred to as an odd-bits check circuit.
Inputs
A B Output
0 0 0
1 0 1
0 1 1
1 1 0
Figure 9
The XOR Gate ant it’s Truth Table
1.7 THE EXCLUSIVE-NOR GATE
 The output of an XOR gate is shown inverted in Figure 10. The output of the inverter on the
right side is called the exclusive-NOR (XNOR) function. The XOR gate produces the
expression A+B. When this is inverted, it forms the Boolean expression for the XNOR gate,
Y=A+B. The standard logic symbol for the XNOR gate is shown on diagram in Figure 10.
Note that the symbol is an XOR symbol with an invert bubble attached to the output.
Inputs
A B Output
0 0 1
1 0 0
0 1 0
1 1 1
Figure 10
The XNOR Gate ant it’s Truth Table

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 The right-hand column of the truth table in Figure 10 details the operation of the XNOR gate.
 Note that all outputs of the XNOR gate are the complements of the XOR-gate outputs. While
the XOR gate is an odd-number-of-1s detector, the XNOR gate detects even numbers of 1 s.
The XNOR gate will produce a 1 output when an even number of 1s appear at the inputs.
1.8 COMBINATION OF LOGIC GATES
 Logic circuits can be combined together using a standard range of logic levels (i.e. the
voltage levels used to represent the logic 1 and logic 0 states) to solve more complex logic
functions. For example, assume that a logic circuit that will produce logic 1 output is to be
constructed whenever two or more of its three inputs are logic 1.
1.8.1 AND-OR PATTERN
 Many everyday digital logic problems use several logic gates. The most common pattern of
gates is shown in Figure 11. This pattern is called the AND-OR pattern. The outputs of the
AND gates (1 and 2) are feeding the inputs of the OR gate (3). You will note that this logic
circuit has three inputs (ABC). The output of the entire circuit is labelled Y.
Figure 11
AND-OR pattern
 Let us first determine the Boolean expression that will describe this logic circuit. Begin the
examination at gate (1). This is a 2-input AND gate. The output of this gate will be A.B. This
expression is written at the output of gate (1) in Figure 11. Gate (2) is also a 2-input AND
gate. The output of this gate will be B.C. This expression is written at the output of gate (2).
 Next the outputs of gates (1) and (2) are ORed together by gate (3). AB being ORed with BC.
The resulting Boolean expression is Y=AB+BC. The Boolean expression Y= AB+BC is read
as (A AND B) OR (B AND C) will equal a 1 at output Y. You will note that the ANDing is done
first, and finally the ORing is done.

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 The next question arises. What is the truth table for the AND-OR logic diagram in Figure?
 Figure 8 will help us determine the truth table for the Boolean expression Y=AB + BC. The
Boolean expression tells us that if both variables A AND B are 1, the output will be 1. Figure
12 illustrates that the last two lines of the truth table have 1s in both the A and B positions.
 Therefore an output 1 is placed under the Y column.
Inputs
A B C Output
0 0 0 0
1 0 0 0
0 1 0 0 Y=AB + BC
1 1 0 1
0 0 1 0
1 0 1 0
0 1 1 1
1 1 1 1
Figure 12
Example Problem
1. Diagram an OR-AND logic circuit for the Boolean Expression Y=(A+B+C)•(A+B+C)

together with the Truth table.
Solution
Inputs
A B C Output
0 0 0 0
1 0 0 1
0 1 0 0
1 1 0 0
0 0 1 0
1 0 1 0
0 1 1 1
1 1 1 0

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 Now let’s look at a more practical example of the use of logic in the typical aircraft system
shown in Figure 13. This logic system's inputs consist of five switches that detect whether the
respective landing gear door is open or not.
 The logic system output is used to drive six warning indicators. Four of these are located on
the overhead display panel and show which door (or doors) are left open, whereas an
indicator located on the instrument panel of the pilot provides a warning for the master
landing gear. In order to enable or disable the five door warning indicators, a switch is also
provided.
 The landing gear warning logic primary module consists of the following integrated circuit
devices:
o A1 Regulated power supply for 5V

o A2 Regulated power supply for A7 and A11
o Ten inverting (NOT) gates
o Five input (NAND) gates
o Six inverting (NOT) gates
Figure 12
Source: Digital Technique Electronics Instrument System

14
 Note that the power supply for A1 and A2 is derived from the essential services DC bus. This
is a 28 V DC bus which is maintained in the event of an aircraft generator failure.
 Note also that the indicators are active-low devices (in other words, they require a logic 0
input in order to become illuminated).
 In order to understand how the landing gear warning logic works it is simply a matter of
tracing logic 0 and logic 1 states through the logic diagram on Figure 14.
 Figure 14 shows how this is done when all of the landing gear doors are closed (this is the
normal in-flight condition).
 Note how the primary door warning indicator shows the pilot that the system is active. When
all of the landing gear doors are closed all inputs to A5 are taken to logic 0, all outputs from
A5 are at logic 0, as is the output from A7.This, in turn, results in logic 1 inputs to the
indicators, which remain in the off (non illuminated) state.
Figure 14
 In Figure 15 the nose landing gear door is open. In this condition the output of A7 goes to
logic 1 and the master warning becomes illuminated on the pilot’s panel. At the same time,
the nose door open warning becomes illuminated.

15
Figure 15
 In Figure 16 both the left wing and the nose landing gear doors are open. In this condition the
output of A7 goes to logic 1 and the master warning becomes illuminated as before. This
time, however, both the nose-door open and left-wing-door-open warnings become
illuminated.
 Note that in a real passenger aircraft a secondary landing gear door warning logic system is
fitted. This system is identical to the primary system shown and provides a back-up in case
the primary system fails. Primary or secondary system operation can be selected by the pilot.
Figure 16

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1.9 Summary
Logic systems for aircraft comply with the same conventions and standards as those used in other
electronic applications. The MIL / ANSI standard logic symbols in particular are invariably used and
the logic elements they represent operate in exactly the same manner as those used in non-aircraft
applications.
1.10 Key Points
Logic circuits involve signals that can only exist in one of two mutually exclusive states. These two
states are usually denoted by 1 and 0, ON or OFF, HIGH or LOW, OPEN or CLOSED and TRUE or
FALSE.
Activity No. 2 (30 minutes to answer this Activity)
1. What are universal gates? Construct a logic circuit using NAND gates only for the expression
Y=A.(B+C)
2. With relevant diagram and truth table explain the working of a two input EX-OR gate?
3. What do you understand by truth table and truth function? How are these related?
4. Draw a logic circuit for Y=(A+B)(C+D)C
5. Draw a logic circuit for Y=A+BC+D
After your class schedule your appropriate response to these activity woks through
the Google Classroom platform. (Deadline of Submission to be discuss)

17
Honesty Clause
This honesty clause establishes a fundamental social contract within which the College community
agrees to live. This contract relies on the conviction that the personal and academic integrity of each
individual member strengthens and improves the quality of life for the entire community. It
recognizes the importance of honesty, trust, fairness, respect, and responsibility and wishes these
principles to be a defining part of Philippine State College of Aeronautics
The Institute of Engineering and Technology values and fosters an environment of academic and
personal integrity, supporting the ethical standards of the engineering profession, where we design
and build for the benefit and safety of society and our environment.
I agree that the submission of any academic work shall constitute a representation on my part both
that such work has been done, and its submission is being made, in compliance with honesty and
integrity. Furthermore, my responsibility includes taking action when I have witnessed or am aware
of another’s act of academic dishonesty.
_________________________
Students Name over Signature

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Rubrics serve as a basis for evaluating the activities provided.
Criteria Excellent Very Good Good Fair Poor

Content The content is The content is Content is not Content is an Incomplete content
Development comprehensive, precise comprehensive, comprehensive and incomplete the topic is not clearly
and encouraging, precise and encouraging, even is not clearly pointed out and not
clearly stated and well encouraging, clearly though the topic is not indicated and is not encouraging (1 out
supported by the stated and well well supported but encouraging (2 of the of 5 questions had
(50 pts) subject. The writing and supported by the addressed.) To have 5 questions been addressed
its purpose are very subject. The scripture the subject matter addressed) with)
clear (Exceptionally, all and its purpose are inconsistent with its
questions were clear. (4 of the 5 content and to clarify
addressed) questions were thoughts. (It
addressed in an addressed 3 out of 5
exceptional way) questions
(50-41 pts) (40-31 pts) (30-21 pts) (20-11 pts) (10-10 pts)
Organization & Paper structure and The paper structure The paper's Paper structure and Organization and
Structure organization are and organization is organization and organization is not structure are not
excellent easy to follow. very clear and easy to structure are clearly easy to follow. The suitable for the
The transitions of follow. Paragraph easy to follow. transitions to topic. Paragraph is
(20 pts) paragraphs are present transitions throughout Paragraph transitions paragraphs need confused and
and very logical and the paper are present throughout the paper improvement thought is lacking
maintain the thought and logical and are present and logical transition.
flow throughout the maintain the flow of and maintain the flow
paper. thought. of thought.
(20-17 pts) (16-13 pts) (12-9 pts) (08 -05 pts) (04 -01 pts)
Format and Paper follows the exact The paper follows Most of the guidelines Paper complies with Paper disorder
References designated guidelines most guidelines and go through paper. some guidelines. made of lacks of
and correctly includes includes incorrect Borderlines, size of Included are elements incorrect
complete references. spacing between text paper, inappropriate borderlines, paper formatting this
lines, using different ink used and 3 size, inappropriate include as such:
font sizes with 4 references are ink used and 2 borderlines, paper
(20 pts) references. included. references. size, improper ink
used, overlap text,
copied plagiarized
or prepared by
another person with
1 reference are
included.
(20-17 pts) (16-13 pts) (12-09 pts) (08 -05 pts) (04 -01 pts)
Grammar Grammar rules, usage Grammar rules, usage Grammar rules, usage Paper made few Language utilizes
Punctuation and are fully followed, is followed and is followed and mistakes in grammar misleading
Spelling spelling is correct. spelling is correct. The spelling is correct. and spelling, conversional tone,
Language is very clear language is very clear Language is clear and language lacks made of numerous
(10 pts) and precise; sentences and precise; the precise; sentences clarification or grammatical and
consistently display structure of phrases is display varied includes some spelling errors.
strong, varied structure. consistently strong structure consistently misleading The activity was
The activity was and varied. strong. conversional tone. submitted two
submitted on time. The activity was The activity was The activity was weeks late.
submitted two days submitted four days submitted one week
late. late. late.
(10-09 pts) (08-07 pts) (06-05 pts) (04-03 pts) (02-01 pts)

19
REFERENCES
Digital Logic Gates, Retrieved from:

https://www.electronics-tutorials.ws/logic/logic_1.html
Digital Techniques Electronics Instruments Aviation Maintenance Technician Certificate

Series, retrieved from:
ttps://www.scribd.com/document/427718484/MODULE-5-Digital-Techniques-Electronic Instrument-
Systems
Electronics Flight Instrument System, Retrieved from:

https://www.theairlinepilots.com/forumarchive/pilotslounge/efis.pdf
Logic Gate (AND, OR, XOR, NOT, NAND, NOR and XNOR); Retrieved from:
https://whatis.techtarget.com/definition/logic-gate-AND-OR-XOR-NOT-NAND-NOR-and-XNOR
(Mike Tooley 2007) Aircraft Digital Electronic and Computer Systems: Principle Operation and
Maintenance, retrieved from:
https://www.classicaviation.in/uploads/ebook/1539501241Mike_Tooley_Aircraft_Digital_Electronic_a
nd_Computer_Systems.pdf
Part 66 Cat. B1 Module 5 Digital Techniques/Electronic Instrument System, Retrieved from:

https://www.ksu.lt/wp-content/uploads/2017/06/M5-Selected-pages.pdf

20

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Associate in Aviation Electronics Technology

MODULE 4 Digital Techniques Flexible Modalities

• 1: Demonstrate the fundamental theory and working principles of Logic gates.

Weeks Topics/Activity Allotted Hours

MODULE 4 Digital Techniques Flexible Modalities

MODULE 4 Digital Techniques Flexible Modalities

1.0 LOGIC GATES THEORY

1.1 THE AND GATE

Input /Switches Output

MODULE 4 Digital Techniques Flexible Modalities

1. Write the Boolean expression for a 3-input AND gate.

MODULE 4 Digital Techniques Flexible Modalities

Input /Switches Output

MODULE 4 Digital Techniques Flexible Modalities

4. Write the Boolean expression for a 3-input OR gate.

MODULE 4 Digital Techniques Flexible Modalities

1.3 NOT GATE (BUFFERS)

MODULE 4 Digital Techniques Flexible Modalities

1. What is the output at point (e) if the input (a) is a 0 bit?

MODULE 4 Digital Techniques Flexible Modalities

1.4 THE NAND GATE

1.5 THE NOR GATE

MODULE 4 Digital Techniques Flexible Modalities

1.6 THE EXCLUSIVE- OR GATE

1.7 THE EXCLUSIVE-NOR GATE

MODULE 4 Digital Techniques Flexible Modalities

1.8 COMBINATION OF LOGIC GATES

1.8.1 AND-OR PATTERN

MODULE 4 Digital Techniques Flexible Modalities

 Therefore an output 1 is placed under the Y column.

1. Diagram an OR-AND logic circuit for the Boolean Expression Y=(A+B+C)•(A+B+C)

MODULE 4 Digital Techniques Flexible Modalities

o A1 Regulated power supply for 5V

Source: Digital Technique Electronics Instrument System

MODULE 4 Digital Techniques Flexible Modalities

Source: Digital Technique Electronics Instrument System

MODULE 4 Digital Techniques Flexible Modalities

Source: Digital Technique Electronics Instrument System

MODULE 4 Digital Techniques Flexible Modalities

1.10 Key Points

Activity No. 2 (30 minutes to answer this Activity)

MODULE 4 Digital Techniques Flexible Modalities

MODULE 4 Digital Techniques Flexible Modalities

Rubrics serve as a basis for evaluating the activities provided.

Criteria Excellent Very Good Good Fair Poor

MODULE 4 Digital Techniques Flexible Modalities

Digital Logic Gates, Retrieved from:

Digital Techniques Electronics Instruments Aviation Maintenance Technician Certificate

Electronics Flight Instrument System, Retrieved from:

Part 66 Cat. B1 Module 5 Digital Techniques/Electronic Instrument System, Retrieved from:

MODULE 4 Digital Techniques Flexible Modalities

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