Evaluation of Power Efficient Adder and Multiplier
Circuits for FPGA Based DSP Applications
1
Subhankar Bhattacharjee, 2Sanjib Sil, 3Biswajit Basak and 4 Amlan Chakrabarti
1,2
Dept-ECE,Techno India College of Technology, Newtown, Rajarhat, Kolkata-700156, India
3
Dept ECE,Hooghly Engineering & Technology College, Pipulpati, Hoogly, India
4
A.K.Choudhury School of Information Technology, University of Calcutta, Kolkata, India
Email: 1subhankarb42002@yahoo.co.in,2sanjib_sil@hotmail.com,3biswajitbsk@yahoo.co.in,4acakcs@caluniv.ac.in
Abstract— This paper describes the design and
implementation of low power arithmetic circuits for
digital signal processing (DSP) applications, using Xilinx
XC5VLX30 (Virtex-5) field programmable gate array
(FPGA) devices. DSP is a highly demanding application
domain in the present day technology wherein the
demands for enhanced performance and reduced
resource utilization have increased over the years.
Recent advancements in FPGA design technology
through the incorporation of DSP functional blocks along
with the inherent FPGA features like high flexibility
through reconfiguration, reusability, moderate cost and
feature extension has resulted in FPGA(s) becoming the
preferred platform for evaluating and implementing
DSP. The arithmetic circuits for addition and
multiplication are the core of any DSP hardware as
all the operations in DSP domain are a combination
of these. In this work we have implemented the
various forms of adder and multiplier circuits on
FPGA, to have an analysis for finding out the most
suitable arithmetic circuits for FPGA based DSP
implementation. We present an analysis of our
implementation results in respect to delay, power
requirement and implementation costs of the different 8,
16, 32 and 64 bit circuits that can be realized for
implementing the basic fixed-point arithmetic units in
FPGA.
Keywords: Arithmetic circuits, adder circuits, low power
design, FPGA, DSP, Xilinx Xpower
I. INTRODUCTION
The adders and multipliers are the most fundamental
arithmetic circuits w h i c h a r e used to build DSP [9]
hardware. Since these circuits perform key operations in
the present day VLSI, their speed and p o w e r optimization
are crucial quality factor in high performance DSP
applications. Typically DSP applications require a tradeoff
between power consumption and speed, hence there is
an immense need for low power [8,11] high speed design of
arithmetic circuits.
Nowadays, FPGA is a much favored platform for digital
VLSI design. This is due to the high flexibility, reusability,
low power, moderate cost, easy upgrading (due to usage
of hardware description languages (HDLs)) and feature
extension (as long as FPGA is not exhausted) facilities
available in the FPGAs. Field programmable gate arrays
(FPGAs) provide a configurable structure through an
array of adjustable logic modules interconnected by
programmable routing resources and surrounded by
programmable input/output blocks. In this research work
we have presented the FPGA based design and
implementation of low power faster adder and
multiplier circuits comparable with peer research works
[1,3,4,5,6,7]
for DSP applications, as well as their performance
analysis based on resource usage, delay and power
considerations.
This paper shows the results of our study
based on the implementation of different types of adders
and multiplier [12, 13] (fixed point arithmetic circuits) circuits
in respect to resource utilization, delay and power measure.
Though related work exists for the design of the arithmetic
circuits in VLSI domain for DSP applications [6, 7, 8, 10, 11, 12],
the FPGA based design issues were not considered in those.
The works on FPGA based design of arithmetic circuits [9, 13]
have focused more on custom design and their realization,
but a detailed analysis of the different arithmetic circuits in
terms of FPGA design metrics of resource utilization, delay
and power were not discussed. In [1] the author has discussed
about the adder and multiplier circuits for FPGA based
design, but no results of power analysis were demonstrated.
In our research we have tried to focus on the design and
implementation issues of the common arithmetic circuits used
in DSP applications, in terms of the FPGA design metrics.
The work done in our paper is quite extensive and it proves to
be a very good analysis in the domain of FPGA based circuit
design for DSP applications. Virtex-5 FPGA [2] has been
chosen for implementing our designs, since it possesses
arithmetic-support features.
The paper is divided into six sections. After the
introduction, Section II describes the design of different
adder circuits. S ection III describes t h e different
multiplier circuits. The simulation environment and results
are briefed in Section IV. The analysis of the results is
presented in Section V, and concluding remarks are discussed
in Section VI.
 II. DESIGN OF ADDER CIRCUITS Booth one, Booth two, Booth three singed multipliers
We have designed and implemented the following of base two, which increase the speed by computing
several bits of the results in one computational step.
adder circuits
• Carry chain adder (CCA): Basic adder structure
based on full adders connected into a chain. The IV. SIMULATION ENVIRONMENT & RESULTS
carry-out of the ith full-adder ( FA) is connected with We have performed all the fixed point arithmetic
the carry-in of the (i+1)th FA, to generate the n- circuits i.e. adders and multipliers implementation on
bit sum outputs and a carry out. This is the simplest Virtex-5, XC5VLX30 device with Xilinx ISE11.1 design
circuit for implementation and it is important for environment, for behavioral simulation purpose we have
comparison with the other adder circuits. used ModelSim and for optimized power estimation we have
• Carry select adder (CSA): In this circuit two used Xilinx Xpower tool.
sets of adders are used, one with the carry-in signal A. Introduction to Xilinx Xpower tool
driven to logic 0 and the second with the carry-in
signal driven to logic 1.The result is selected by Xpower [2] estimates the power based on the
multiplexers controlled by the actual carry-in signal. observation of the dynamic power consumption in CMOS
circuits due to switching activity. Each element (LUT, FF,
• Carry look ahead adder (CLA): The main idea
behind the carry look-ahead addition is an attempt to BRAM, and routing segment) that can switch has a
generate all incoming carries in parallel and avoid capacitance model associated with it. Clock signals and
waiting until the correct carry propagates from the primary input signals are assigned specific frequencies
stage (FA) of the adder where it has been by the user. Xpower estimates power as a summation of the
generated. The carry look ahead adder uses two power consumed by each element in the design. The power
special signals G (generate) and P (propagate) to consumed by each switching element in the design is given
predict the propagation of a carry signal without by:
using a carry chain. P = C * V2 * E * F * 1000
Where: P=Power in mW; C=Capacitance in Farads
• Carry skip adder (CKA): A carry-skip adder reduces V=Volts; E=switching activity
the carry-propagation time by skipping over groups
F=Frequency in Hz
of consecutive adder stages. The carry-skip adder
is usually comparable in speed to the carry look-ahead B. Results of fixed point addition
technique.
Table I shows the results of measurements carried out on
• Sign magnitude adder (SMA): This is simple carry the implemented adder structures of 16, 32 and 64 bit width
ripple adder with most significant bit used as sign on Virtex-5 FPGA. The results show that the best adder
bit. It takes more area as well as more power. structure in terms of both area and time is the carry look
ahead adder for 64 bit width.
III. DESIGN OF MULTIPLIER CIRCUITS
We have designed and implemented the following TABLE I: RESULTS OF FIXED POINT ADDERS IMPLEMENTED ON
VIRTEX-5, XC5VLX30,PACKAGE-FF243
multiplier circuits
• Basic multiplier (BM): The most basic parallel N=8Bit N=16Bit N=32Bit N=64Bit
mode multiplier circuit that computes
Area Delay Area Delay Area Delay Area Delay
multiplication in a human like way, i.e., going (Slices) (ns) (Slices) (ns) (Slices) (ns) (Slices) (ns)
through the bits of one operand and
simultaneously accumulating the second operand CCA 4 5.521 9 7.872 18 12.111 42 20.59
and shifting the sum.
CSA 4 5.521 7 7.64 17 11.879 50 20.358
• Carry save multiplier (CSM): A parallel
mode multiplier that uses a tree of carry save adders. CKA 4 5.752 7 7.872 20 12.111 50 20.5
Carrie save multipliers have a shorter delay than a 9
normal multiplier, also takes less number of slices. CLA 4 4.833 16 9.165 23 9.574 41 11.468
• Carry ripple multiplier (CRM): A parallel SMA 7 8.852 15 12.16 33 20.146 70 28.64
mode multiplier that uses carry ripple adders. Its
delay is greater than carry save multiplier and also
takes more slices than carry save multipliers.
• Booth multiplier for signed operands (BSM): This
is also a parallel mode multiplier that uses
Booth [10] recording. This enables us to compute
signed number multiplication. We have implemented
 implemented adder circuits of 16,32 and 64bit width on
Virtex-5 FPGA. In Figure 2 and Figure 3 we have compared
TABLE II : RESULTS OF POWER CALCULATION OF FIXED POINT ADDERS the highest and lowest total quiescent power and total dynamic
IMPLEMENTED ON VIRTEX-5, DEVICE-XC5VLX30,324 power between the adders.

N=8Bit N=16Bit N=32Bit N=64Bit

Total Total Total Total Total Total Total Total

Dynamic Quiescent Dy. Qui. Dy. Qui. Dy. Qui.
Power Power Pwr Pwr Pwr Pwr Pwr Pwr
CCA 0.01907 0.29612 0.03608 0.29647 0.0701 029719 0.13917 029865
Watt Watt Watt Watt Watt Watt Watt Watt
CSA 0.01907 0.29612 0.03604 0.29647 0.0702 0.29719 0.13932 0.29865
Watt Watt Watt Watt Watt Watt Watt Watt
CKA 0.01907 0.29612 0.03604 0.29647 0.07019 0.29719 0.13932 0.29865
Watt Watt Watt Watt Watt Watt Watt Watt
CLA 0.01904 0.29611 0.03625 0.29648 0.06824 0.29715 0.13532 0.29857
Watt Watt Watt Watt Watt Watt Watt Watt

SMA 0.01284 0.29599 0.03631 0.29648 0.07076 0.29720 0.14033 0.29867

Watt Watt Watt Watt Watt Watt Watt Watt

Are a Figure 2. Comparison between the highest and the lowest total
dynamic power
80

70

60

50

40 S er ies 1

30

20

10

0
C ar r y lo o k ahead ad d er S ig n m ag nit ud e ad d er
6 4 b it 6 4 b it

D e la y

35
Figure 3. Comparison between the highest and the lowest total quiescent
power
30
TABLE III. RESULTS OF FIXED POINT MULTIPLIER IMPLEMENTED
25 ON VIRTEX-5, DEVICE-XC5VLX30,PACKAGE-FF324

20 N=8Bit N=16Bit N=32Bit

S er ies 1
15 Area Delay Area Delay Area Delay
Slices (ns) Slices (ns) Slices (ns)
10
BM 30 15.668 124 28.543 445 54.262
5
CSM 21 8.904 93 14.260 392 24.846
0 RCM 23 14.075 107 30.023 434 60.223
C ar r y lo o k ahead ad d er S ing m ag nit ud e ad d er
6 4 b it 6 4 b it BSM 35 16.644 142 25.028 530 47.189
(I)
BSM 23 11.561 77 20.178 284 37.511
Figure 1. Comparison between the highest and the lowest area and delay of (II)
the 64bit adders BSM 26 11.520 108 16.644 383 27.781
(III)

In Figure 1, we have compared the highest and lowest area

and delay between the adders. Table II shows the results by Table III shows the results of measurements carried out
measurement of power using Xpower tools for the on the implemented multiplier circuits of 8, 16 and 32 bit
 width on Virtex-5 FPGA. The result shows that the TABLE IV. RESULTS OF POWER CALCULATION OF FIXED POINT
MULTIPLIERS IMPLIMENTED ON VIRTEX5XC5VLX30,FF3234
best multiplier structure in terms of area is Booth-two
multiplier for signed operands (Base 2) for 32 bit width. N=8Bit N=16Bit N=32Bit

Total Total Total Total Total Total

Ar e a
Dynamic Quiescent Dynamic Quiescent Dynamic Quiescent
Power Power Power Power Power Power
600 BM 0.03392 0.29643 0.06919 0.29717 0.14361 0.29874
500 Watt Watt Watt Watt Watt Watt
400 CSM 0.01722 0.29608 0.03569 0.29646 0.07605 0.29731
Area(Slices)

300 Series 1 Watt Watt Watt Watt Watt Watt

RCM 0.03389 0.29643 0.06713 0.29713 0.14084 0.29869
200
Watt Watt Watt Watt Watt Watt
100 BSM 0.03402 0.29643 0.06974 0.29718 0.14598 0.29879
0 (I) Watt Watt Watt Watt Watt Watt
BSM 0.03389 0.29643 0.06889 0.29716 0.14005 0.29867
r
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(II) Watt Watt Watt Watt Watt Watt

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BSM 0.03394 0.29643 0.05652 0.29690 0.04007 0.29656

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0.297 S eries1
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0.2965
0.296
60 0.2955
50 0.295
Delay(ns)

40

Carry save

Booth_one

Booth_three
Booth_two
Ripple carry
multiplier

multiplier

multiplier
multiplier
S e r ie s 1

multiplier

multiplier
Basic
30
20
10
0
r

M ultiplie r 32_Bit
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M u lt ip lie r 3 2 _ B it

V. ANALYSIS OF THE RESULTS

Figure 4. Comparison of cost between the best and the worst From the comparison of the fixed-point adder circuits as
multiplier circuits: Comparison of Area and Delay
shown in Figure 2 and Figure 3, we can say that minimum total
dynamic and total quiescent power is consumed by the Carry
look ahead adder for 64-bit width and maximum of both type
In Figure 4 we have compared the highest and lowest of power is consumed by the Sign magnitude adder for 64-bit
area and delay between the 32bit multiplier. In Table IV width. From the comparison of Figure 1 we can also observe
we have shown the results by measurements of power that minimum slices are used for 64-bit Carry look ahead adder
u s i n g Xpower tools for the implemented adder circuits and maximum slices are used for 64-bit Signed magnitude
of 8, 16 and 32bit width on Virtex-5 FPGA. In our adder. We can suggest that the better design objective would be
implementation we have observed that 64 bit multiplier is to design an adder circuit with less number of circuit
not possible to implement in Virtex-5 FPGA due to components i.e. slices which will give less power.
hardware constraint. In the Figure 5 we have compared
between the highest and lowest total quiescent power
and Figure 6 shows the comparison between the highest
and lowest total dynamic power of the 32bit multiplier.
 research we have focused both on delay and power
Total Dynamic Power
consumption of different types of arithmetic circuits on FPGA.
The Xilinx Virtex-5 FPGA [2] family was chosen as the
0.16
0.14 implementation platform, because it provides special features
Power(watt)

0.12
0.1 to support arithmetic operations, a trend that seems to be
0.08 Series1
0.06 common at the present time for FPGA chips. From our
0.04
0.02
research we have observed that not only the design with less
0 numbers of circuits i.e. less slices gives less power but also the
Carry save
multiplier

Booth_one

Booth_two

Booth_three
circuits having smaller delays consumes less power.
Ripple carry
multiplier

multiplier
multiplier
multiplier

multiplier
Basic

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Multiplier 32_Bit
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compared only about the delay and the area but did not
considered power consumption of the arithmetic circuits. In our