SoC Design

ectu e 5: Designing
Lecture es g g with
w t FPGAs
G s

Shaahin Hessabi
Department of Computer Engineering
Sharif University of Technology
 Outline
„ Designing for High Speed
„ Designing for Signal Integrity
„ Designing for Low Power
„ Designing for Security
„ Asynchronous Design Issues

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 Designing for High Speed
1. Provide high-
high-level floor planning
™ Intelligent pin assignment
– prevents routing congestion and poor performance
™ Natural structure:
– Data flows horizontally, Control flows vertically
– Vertical adders and counters, carry going upwards
™ Pick the best I/O standard

Place & route tool should not do all your work

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 Designing for High Speed (cont’d)
2. Design synchronously, use global clocks
™ Up to 16 Global Clocks are available
– Very low skew on these clock nets
™ DLL (Delay
(Delay--Locked Loop) eliminates clock distribution delay
– Inside the chip, or even on the pc-
pc-board
™ Do not gate the clock, use CE instead
– But you may need clock gating for lowest power
– Virtex--II has glitch
Virtex glitch--free clock gate and clock mux
™ Use Carry for adders, counters and comparators
– Superior speed, less logic, forces vertical orientation
™ Use predefined cores
– Have been tested and are guaranteed to work at speed

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 Designing for High Speed (cont’d)
3. Use local buffers to reduce clock skew
™ Global buffers are connected to dedicated routing
– Global clock network is balanced to minimize skew
™ All Xilinx FPGAs have global buffers
– XC4000 and Spartan have 8
XC4000
– Virtex and Spartan-
Spartan-II have 4
– Virtex--II has 16 BUFGs with g
Virtex glitch-free input
glitch- p mux
™ You can always use a BUFG symbol and the software will
choose an appropriate buffer type
– All major
j synthesis
th i ttools
l can iinfer
f global
l b lb
buffers
ff onto
t clock
l k signals
i l
that come from off-
off-chip

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 Designing for High Speed (cont’d)
4. Use timing constraints
™ The implementation tools do NOT try to find the placement and
routing that achieves the fastest speed
– They just try to meet your performance expectations
™ YOU mustt communicate
i t your expectations
t ti
– Through Timing Constraints
™ Timing
g Constraints improve
p p
performance
– By placing logic closer together and shortening the routing
– Timing constraints define your performance objectives
„ Tight
Ti ht titiming
i constraints
t i t iincreases compile
il titime
„ Unrealistic constraints causes the Flow Engine to stop
„ Logic Level Timing Report tells whether constraints are
realistic
Timing constraints are the best high-
high-level tool to achieve
guaranteed performance
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 Designing for Signal Integrity
1. Devices need good Vcc bypassing
™ Bypass capacitor is the only source of dynamic current
2. User needs understanding of transmission line effects
™ Characteristic impedance,
p reflections, dV/
dV/dt
™ Series termination, parallel termination
3. Decouple power supply
™ CMOS current is dynamic
– Icc current spike on every active clock edge
™ Peak current can be 5x the average current
– Instantaneous current peaks only supplied by decoupling capacitors
™ Use one 0.1 μF ceramic chip capacitor per Vcc pin

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 Designing for Signal Integrity (cont’d)
4. Use SLOW attribute where available
™ Increases transition time
– especially when driving transmission lines
™ Reduce fan-
fan-out and load capacitance
™ Add virtual ground
– Ground output pin inside and outside, give it max strength
5 Test for performance and reliability
5.
™ Manipulate circuit speed for testing purposes:
– Hot and low Vcc = slow operation
p
– Cold and high Vcc = fast operation
™ If it fails hot: insufficient speed
– U a ffaster
Use t speed d grade
d
– Modify the design, add pipelining

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Designing for Signal Integrity (cont’d)
™ If it fails cold: signal integrity and hold time issues
– Look for clock reflections
– Look for excessive internal clock delays
– Look for decoding spikes driving clocks
– Look for “asynchronous
asynchronous tricks
tricks”

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 Designing for Low Power
„ To extend battery life
„ To reduce chip temperature and cooling requirements
™ Tjmax = 125 °C (150
(150 °C in ceramic)
™ Delays
y increase 0.35
35%
% / °C
™ above the guaranteed 85 °C junction temperature
„ Use the free Xilinx Power Estimator
™ http://www.xilinx.com/cgi--bin/powerweb.pl
http://www.xilinx.com/cgi

Power is proportional to CV2f

Minimize all three !

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 Designing for Low Power (cont’d)
Power: clock power + I/O power + logic power
„ Clock Power
™ Minimize # of high-
high-speed clock nets
™ Use DLLs for pphase-aligned
phase- g sub-
sub-clocks
™ CE does not reduce clock power
„ I/O power
™ Avoid wasted current in input buffers
™ Use fast, full-
full-swing input signals
™ U output
Use t t registers
i t to
t avoid
id output
t t glitches
lit h
„ Logic power
™ Control Vcc tightly
– Power is proportional to Vcc2

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 Designing for Low Power (cont’d)
™ Minimize logic transitions and glitches
™ Optimize counters:
– Gray and Johnson are best
– Binary counters double the power
– Linear Feedback Shift Register are even worse
™ Minimize internal node capacitance
– Use aggressive timespecs
– Design for the highest speed possible, even if not needed
„ This assures lowest interconnect capacitance and provides the
lowest ppower at the lower clock frequency
q y

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 Designing for Security
„ Configuration bitstream can be intercepted
™ But not interpreted or reverse
reverse--engineered
™ Some users are concerned about IP theft
„ Virtex -II offers securityy through
g encryption
yp
™ Triple--DES with 3 x 56 bits
Triple
„ Bitstream Encryption

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 Configuration
g Modes: Serial Modes
„ Data is loaded one bit per CCLK
„ Master serial
™ FPGA drives configuration clock (CCLK)
™ FPGA
G provides all control logic
„ Slave serial
™ External
E ternal control logic generates CCLK
– Microprocessor

– Xilinx download cable

– Another FPGA

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 Configuration
g Modes
„ Byte--Wide Slave SelectMAP Mode
Byte
™ CCLK is driven by external logic
™ Data is loaded one byte per CCLK

„ Master SelectMAP Mode

™ CCLK is driven by the Virtex II FPGA
™ Data is loaded one byte per CCLK

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 Configuration Modes:
Boundary Scan Mode
„ External control logic required
„ Control and data drive the boundary
scan pins (TDI, TMS, TCK)
„ Data is loaded bit-
bit-serially one bit per
TCK

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 Asynchronous
y Issues: Metastabilityy
„ Most systems operate synchronously inside
™ But asynchronous inputs are a fact of life
„ Occasionally, an asynchronous input will cause a flip-
flip-flop
t go metastable
to t t bl
™ This is a rare, but unavoidable, probabilistic event
„ Violations occur when the flip
flip--flop input changes too close
to a clock edge
„ Th
Three possible
ibl results:
lt
™ FF clocks in old data value
™ FF clocks in new data value
™ FF output becomes
metastable

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 Metastability
„ Caused by asynchronous data input
™ Violates set-
set-up time requirement
™ Usually gets synchronized in the flip-
flip-flop without problem
„ But if data changes
g within a tiny
y set-
set-up
p time window
™ Then the flip-
flip-flop can go metastable
™ Resulting in unpredictable delay to reach stable 1 or 0
„ The 0 vs. 1 uncertainty is irrelevant
™ The slightest timing change would give a correct 1 or 0
„ Th unpredictable
The di t bl ddelay
l iis th
the problem
bl
™ It can violate set-
set-up times in the system, causing erratic
operation or even crashes

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 Synchronization
y Circuit
„ Solution:
™ Faster flip-
flip-flops recover faster
™ Double--synchronization reduces probability
Double

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