ECE 695R:

SYSTEM-ON-CHIP DESIGN
Module 3: Behavioral Synthesis
Lecture 3.3: Major Steps – Binding/Assignment

Anand Raghunathan
raghunathan@purdue.edu
Fall 2014, ME 1052, T Th 12:00PM-1:15PM
ECE 695R: System-on-Chip Design, Fall 2014 © 2013 Anand Raghunathan
 Register Binding
Registers
Implied

a
+
b
+
+ y
c
d
y=a+b+c+d

Clock cycle 1 2 3

ECE 695R: System-on-Chip Design, Fall 2014

 Register Binding: Lifetime Analysis

a
+
b
+
Registers R1 & R2 + y
can be shared c d

R1
R2
R3
Clock cycle 1 2 3
(R3 needed for output latch)
ECE 695R: System-on-Chip Design, Fall 2014
 Functional Unit Binding

a y= (a+b+c)*(d+e)
+
b
op1 +
op3 * y
c

d
+
e
op2

Clock cycle 1 2 3

ECE 695R: System-on-Chip Design, Fall 2014

 Functional Unit Binding Choices

Binding 1 Binding 2

Operation Binding Operation Binding

Op1 Add1 Op1 Add1
Op2 Add2 Op2 Add2
Op3 Add1 Op3 Add2

ECE 695R: System-on-Chip Design, Fall 2014

 Operation Binding
Binding 1 Results Op1 Add1
Op2 Add2
Op3 Add1
S2

a S1
+
c S2
S1,2
S3
b S1 *
S2,3 a
+
d S1 b op1 +
+ op3 * y
e c
d +
e op2

ECE 695R: System-on-Chip Design, Fall 2014

 Operation Binding
Binding 2 Results Op1 Add1
Op2 Add2
Op3 Add2

a + S1
b
S2 S1,2

S2 * S3

d S1
S2
a
c S2 + S1
+
b op1 +
e S1 c
op3 * y
d +
e op2

ECE 695R: System-on-Chip Design, Fall 2014

 A quick tour through behavioral
synthesis
• Advanced techniques
– Chaining and Multi-cycling
– Pipelining
• Using pipelined functional units
• Pipelining the entire algorithm
– Transformations
• Loop transformations
• Arithmetic transformations
• Control-flow transformations (e.g.,
speculation)

ECE 695R: System-on-Chip Design, Fall 2014

 Multi-Cycling and Chaining

Combinational Logic Block

latch
enable

CL1 CL2 latch

ECE 695R: System-on-Chip Design, Fall 2014

 Pipelining

Combinational latch
Logic Block

Combinational latch Combinational latch Combinational latch

Logic Block Logic Block Logic Block
(1/3) (2/3) (3/3)

ECE 695R: System-on-Chip Design, Fall 2014

 Loop Unrolling
• Increases the scope of optimization by exposing a
larger sub-program to the other steps (scheduling,
resource sharing)
• What happens to the control overhead when the
loop is unrolled?

FOR i IN 0 to 3 LOOP
1 adder, 4 cycles
result := result+ S(i);
END LOOP;
1 adder, 4 cycles
result := result + S(0) + OR
S(1) + S(2) + S(3) 2 adders, 2 cycles
OR
4 adders, 1 cycle

ECE 695R: System-on-Chip Design, Fall 2014

 Summary

• Behavioral Synthesis automatically

generates an RTL implementation
(architecture) from a behavioral
specification (algorithm)
• Rich history of research
– First attempts failed
– Recent resurgence due to improved
technology and higher need
• Basic steps in behavioral synthesis
– Scheduling, resource sharing
ECE 695R: System-on-Chip Design, Fall 2014
 References / Reading Material

• The following books are available at POTR

– High-level synthesis: From algorithm to digital circuit,
Philippe Coussy and Adam Morawiec, Springer, 2008.
[Online version available]
– High-level synthesis: Introduction to chip and system
design, Daniel D. Gajski, Nikil Dutt, Allen Wu, Steve Lin,
Kluwer Academic, 1992.
– Understanding behavioral synthesis: A practical guide to
high-level design, John P. Elliott, Kluwer Academic, 2000.
– High-level VLSI synthesis, Raul Camposano and Wayne
Wolf, Kluwer Academic, 1991.

ECE 695R: System-on-Chip Design, Fall 2014