THIRD INTERNAL ASSESSMENT QUESTION PAPER

SUBJECT CODE / NAME :EE8351 DIGITAL LOGIC CIRCUITS DATE : 21.10.2020 AN

YEAR / SEMESTER : II/III BRANCH : EEE TIME : 2.30 PM To 4.00 PM
ACADEMIC YEAR : 2020 – 2021 MARK : 50
CO3:Create various digital logic circuits using state diagram,state assignment and state
reduction
CO4:Apply the function of digital logic families, programmability logic devices.
CO5:Analyze various digital logic circuits using state diagram,state assignment and state
reduction.
CO6:Evaluate digital simulation for development of application oriented logic circuits.
BLOOM'S TAXONOMY
Remembering Applying Evaluating
Understanding Analysing Creating

PART A (5 x 2 = 10 marks)
U CO4 1. What is PROM? (2)
U CO4 2. Differentiate between Static 0 and Static 1 hazards (2)
U CO3 3. Define primitive flow table and critical Race (2)
A CO4 4. How does the architecture of PLA different from a PROM? (2)
An CO6 5. Write VHDL code for Half adder in data flow mode. (2)
PART B (13+ 13 + 14 = 40Marks)
An CO5 6. i.
Design an asynchronous sequential circuit that has two X2 and X1 and one
output Z.When X1=0,the output Z is 0.The first change in X2 that occurs while
(13)
X1 is 1 will cause output Z to be 1.The output Z will remain 1 until X1 returns
to 0.

E CO6 7. i. Write a VHDL program Code to realize a full adder using structural modeling and
(13)
Structural modeling

A CO4 8. i. Explain the various types of hazards in sequential circuit design and the (7)
methods to eliminate them. Give suitable examples
C CO3 ii. Obtain a state diagram and primitive flow table for a circuit with two inputs x1 (7)
and x2 and two outputs z1 and z2 that satisfies the following four conditions.
i) When x1x2=00 outputsz1z2=00
ii) When x1=1 and x2 changes from 0 to 1,the output z1z2=01
iii) When x2=1 and x1 changes from 0 to 1,the outputsz1z2=10
iv) Otherwise the output does not change.