Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Nivel_FMS is Port ( clk: in STDA_LOGIC; Reset: in STD_LOGIC; SV : in STD_LOGIC SL : in STD_LOGIC; SR : in STD_LOGIC; IV : in STD_LOGIC; ILL : in STD_LOGIC; ILO: in STD_LOGIC; IR: in STD_LOGIC; IA : in STD_LOGIC; B1 : in STD_LOGIC; B2 : in STD_LOGIC; End Nivel_FSM;
Architecture Behavioral of Nivel_FSM is
Type estados is (S0,S1,S2,S3,S4); Signal state_reg, state_netx: estados; Begin Process(clk, reset) Begin If reset = ‘1’ then state_reg <= S0; Elsif (clk’eent and clk=’1’) then state_reg <= state_next; end if; end process; process(state_reg, SV,SL, SR) begin IV <= ‘0’; ILL <= ‘0’; ILO <= ’0’; IR < = ‘0’; IA <= ‘0’ B1 <= ‘0’; Case state_reg is When S0 => IV <= ‘1’; B1 <= ‘1’; B2 <= ‘1’; If SV = ‘1’ and SL=’0’ and SR=’0’ then B1 <= ‘1’; B2 <= ‘1’; State_next <= S1; End if When S1 => ILL <= ‘1’; B2 <= ‘1’; If SV = ‘1’ and SL= ‘1’ and SR = ‘0’ then B1 <= ‘1’; B2 <= ‘0’; State_next < = S2; End if; When S2 => ILO <= ‘1’; B1 <=’1’; B2 <= ‘0’; If SV= ‘1’ AND SL=’1’ AND SR = ‘1’ then B1 <= ‘0’; B2 <= ‘0’; State_next <= S3 End if; When S3 => IR <= ‘1’; B1 <= ‘0’; B2 <=’0’; If SV=’1’ AND SL = ‘0’ AND SR=’1’ THEN B1 <= ‘0’; B2 <= ‘0’; State_next <= s4; End if When S4 => IA <= ‘1’; If (SV = ‘0’ AND SL=’0’ AND SR=’0’) THEN B1 <= ‘0’; B2 <= ‘0’; State_next <= S0; Elsif (SV= ‘1’ AND SL = ‘0’ AND SR = ‘0’) THEN B1 <=’1’; B2 <= ‘0’; State_next <= S2; Elsif (SV = ‘1’ AND SL = ‘1’ AND SR = ‘1’) THEN B1 <= ‘0’; B2 <= ‘0’; State_next <= S3; End if; End case; End process; End Behavioral