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VLSI Physical Design - Frequently Asked Question in Physical Design Interviews
VLSI Physical Design - Frequently Asked Question in Physical Design Interviews
Physical Verification Static Timing Analysis (STA) Signal Integrity Linux Basics CMOS Fundamental Low Power Design
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1. What all checks you will perform before starting floor planning?
2. What are inputs given to the floor planning stage?
Name
3. What kind of blockages you have given to your last project?
4. How you will determine the distance between two macros?
5. what is the size of your block? Email *
6. what are general guidelines you followed for Macro placement?
7. How many macros and standard cell were there in your block?
Message *
8. how will you place macro?
9. In your design memories are there but not connected anywhere, where you will place the
memory?
10. if your design is 8 layer and your block is 4 layer, how will you place.
Send
1. How many blockages are there in your design, how will you solve blockages
2. whether routing is possible in HALO Search This Blog
3. How will you solve routing congestion
4. How many type of congestion were there in your design Search
5. How will you find the distance between two macros
6. how you use to do routing
7. How will you solve the congestion when utilization and cell density is more? Translate
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10/31/2020 VLSI Physical Design: Frequently Asked Question in Physical Design Interviews
1. What is goal of CTS? Blog Archive
2. What are inputs to CTS?
▼ 2015 (115)
3. What is the target skew?
▼ August (29)
4. what are inputs you have given in CTS
List of Topics
5. how will you solve setup violation
About this blog
6. what is hold, how will you solve it
Frequently Asked Question in
7. suppose your design is of 500 mhz frequency, setup and hold are fix. If frequency is increased Physical Design Inter...
to 750 mhz, what will happen to setup and hold
Important Input Files in Physical
8. how will you build clock tree, describe the procedure Design Flow
9. what is slew, what is relation between transition and slew Floor Planning
10. how you use to do cts Power Planning Basics
11. what is virtual clock
Placement
12. how will you save time in cts optimizations
Routing
13. what are false path
Clock Tree Synthesis
14. How signal integrity impact setup and hold violation?
STA
15. How to fix setup and hold violation after p & r?
Physical Verification
Question Based on Physical Verfication Basics of IC Compiler
Physical Design Flow
1. what are the files getting evaluated during LVS stage
Types of Cell
Basic Linux Commands
References
Miscellaneous Questions Double Patterning
Advance Onchip Variation
Signal Integrity
Onchip Variation (OCV)
1. For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns
insertion delay and 0.25 skew for the same circuit then which one you will select and Why? Scripts used in IC Compiler
Blockages
2. What is partial floor plan? Aspect Ratio
Design Netlist
3. What are the steps that you have done in the design flow?What are the issues in floor plan?
Some Basic Rules For Placing
Macros
4. How can you estimate area of block?
IO Placement / Pin placement
Core Utilization
5. How much aspect ratio should be kept (or have you kept) a
IR Drop
15. What is setup Time and hold time? Why there are ? What if setup Violates and hold violates?In
a circuit, for reg to reg path ...
16. Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum
operating frequency?
17. How R and C values are affecting time?How ohm (R), fared (C) is related to second (T)?What Follow
is transition?
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24. What is difference between HFN synthesis and CTS?What is hold problem? How can you
avoid it?
25. What are the steps that you have done in the design flow?What are the issues in floor plan?
26. How can you estimate area of block?How much aspect ratio should be kept (or have you kept)
and
27. what is the utilization?How to calculate core ring and stripe widths?What if hot spot found in
some area of block?
28. How you tackle this?After adding stripes also if you have hot spot what to do?What is
threshold voltage?
29. What are DFM issues? What is the difference between synthesis and simulation?What is metal
density
30. metal slotting rule?What is OPC, PSM?Why clock is not synthesized in DC?What are high-Vt
and low-Vt cells?
31. What corner cells contains?What is the difference between core filler cells and metal fillers?
32. How to decide number of pads in chip level design?What is tie-high and tie-low cells and
where it is used?
34. What are the steps involved in designing an optimal pad ring?
35. What is grided and gridless routing?What is a macro and standard cell?What is congestion?
36. Whether congestion is related to placement or routing?What are clock trees?What are clock
tree types?
37. Which layer is used for clock routing and why?What is cloning and buffering?What are
placement blockages?
38. How slow and fast transition at inputs effect timing for gates?
40. What is logic optimization and give some methods of logic optimization.What is the
significance of negative slack?
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10/31/2020 VLSI Physical Design: Frequently Asked Question in Physical Design Interviews
45. What is core and how u will decide w/h ratio for core?What is effective utilization and chip
utilization?What is latency?
46. Give the types?How the width of metal and number of straps calculated for power and
ground?What is negative slack ?
48. In which layer do you prefer for clock routing and why?If in
49. your design has reset pin, then it’ll affect input pin or output pin or both?
50. During power analysis, if you are facing IR drop problem, then how did u avoid?Define
antenna problem and
51. how did u resolve these problem?How delays vary with different PVT conditions? Show the
graph.Explain the flow of physical design
52. and inputs and outputs for each step in flow.What is cell delay and net delay?What are delay
models and what is the difference
53. between them?What is wire load model?What does SDC constraints has?
54. Differentiate between a Hierarchical Design and flat design?Which is more complicated when
u have a 48 MHz and 500 MHz clock design?
55. Name few tools which you used for physical verification?What are the input files will you give
for primetime correlation?
56. What are the algorithms used while routing? Will it optimize wire length?How will you decide
the Pin location in block level
57. design?If the routing congestion exists between two macros, then what will you do?How will
you place the macros?How will you
58. decide the die size?If lengthy metal layer is connected to diffusion and poly, then which one
will affect by antennaproblem?
59. If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead
of using7LM?
60. In your project what is die size, number of metal layers, technology, foundry, number of clocks?
61. How many macros in your design?What is each macro size and no. of standard cell count?
64. What is SDC constraint file contains?How did you do power planning?How to find total chip
power?How to calculate core ring width, macro ring width and strap or trunk width?How to find
number of power pad and IO power pads?What are the problems faced related to timing?
68. What is core and how u will decide w/h ratio for core?* What is effective utilization and chip
utilization?
70. What are the steps involved in designing an optimal pad ring?
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71. What are the steps that you have done in the design flow?
73. How much aspect ratio should be kept (or have you kept) and what is the utilization?*
75. What if hot spot found in some area of block? How you tackle this?
76. After adding stripes also if you have hot spot what to do?
77. Why higher metal layers are preferred for Vdd and Vss?
78. What are clock tree types?H tree, Balanced tree, X tree, Clustering tree, Fish bone
80. Cloning is a method of optimization that decreases the load of a heavily loaded cell by
replicating thecell.Buffering is a method of optimization that is used to insert beffers in high
fanout nets to decrease thedealy.What parameters (or aspects) differentiate Chip Design &
Block level design??
83. inputs for PT (how it works and what format you take design)
84. how congestion you check what what was the ration, and how you fixed
85. What happen if you have insertion delay (apart for timing violation)
86. Floor planning, why we need .lib for floorplaning (apart from the power info)
88. how CLKBUF is differentiating with normal buffer, what if we use normal buffer.
90. why endcap, internal structure and how u differentiate with filler cell
99. What are the steps for fixing setup and hold violations?
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10/31/2020 VLSI Physical Design: Frequently Asked Question in Physical Design Interviews
101. In antenna violation fixing why we are going for higher layers in metal jogging?
105. What will you do if a path has both setup and hold violations?
108. How big was your previous design..?(Expectation was block size and gate count )
110. What were the challenges faced in your design and how did you overcome.?
111. How do you use the blockage technique effectively to reduce congestion.?
115. Buffer insertion technique, how the setup and hold varies with the buffer location(between source and destination)
116. What is antenna effect and the measures taken to over come.
119. what are the drastically changes come when u move from 180 nm to 28nm?
121. what are the timing challenges u faced in ur design. and how did u fixed?
127. IF u face congestion in ur design during routing stage. how will u fix it.
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Labels: asic, faq, faq in physical design, frequently asked question in physical design, interview
questions, pd, physical design, physical design interview questions, soc, vlsi
11 comments:
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Hi Ariful, I have added few more question in miscellaneous section it includes the question
from all the area
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Replies
tq
shafi
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Superb collection
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up to 25 questions he given answers select the blue lines according to d questions open
it...der u will get answers...
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10/31/2020 VLSI Physical Design: Frequently Asked Question in Physical Design Interviews
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