This document outlines a test for an Electronic Circuits I course, including:
- 3 parts (B, C, and D) containing multiple choice and numerical questions.
- Part B contains 3 questions, each with 2 sub-questions worth 12 marks. Topics include compensation techniques in BJTs, voltage divider bias, and small signal analysis of amplifiers.
- Part C contains 1 question with 2 sub-questions worth 14 marks, involving designing a voltage divider bias circuit and evaluating small signal voltage gain.
- The test was prepared by the Head of Department P. Manoj for second year ECE students, with a maximum mark of 50 over 1.5 hours.
This document outlines a test for an Electronic Circuits I course, including:
- 3 parts (B, C, and D) containing multiple choice and numerical questions.
- Part B contains 3 questions, each with 2 sub-questions worth 12 marks. Topics include compensation techniques in BJTs, voltage divider bias, and small signal analysis of amplifiers.
- Part C contains 1 question with 2 sub-questions worth 14 marks, involving designing a voltage divider bias circuit and evaluating small signal voltage gain.
- The test was prepared by the Head of Department P. Manoj for second year ECE students, with a maximum mark of 50 over 1.5 hours.
This document outlines a test for an Electronic Circuits I course, including:
- 3 parts (B, C, and D) containing multiple choice and numerical questions.
- Part B contains 3 questions, each with 2 sub-questions worth 12 marks. Topics include compensation techniques in BJTs, voltage divider bias, and small signal analysis of amplifiers.
- Part C contains 1 question with 2 sub-questions worth 14 marks, involving designing a voltage divider bias circuit and evaluating small signal voltage gain.
- The test was prepared by the Head of Department P. Manoj for second year ECE students, with a maximum mark of 50 over 1.5 hours.
This document outlines a test for an Electronic Circuits I course, including:
- 3 parts (B, C, and D) containing multiple choice and numerical questions.
- Part B contains 3 questions, each with 2 sub-questions worth 12 marks. Topics include compensation techniques in BJTs, voltage divider bias, and small signal analysis of amplifiers.
- Part C contains 1 question with 2 sub-questions worth 14 marks, involving designing a voltage divider bias circuit and evaluating small signal voltage gain.
- The test was prepared by the Head of Department P. Manoj for second year ECE students, with a maximum mark of 50 over 1.5 hours.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
ACADEMIC YEAR 2018-2019 (ODD SEMESTER) Prepared By HOD
PART B&C QUESTION TEST [P.MANOJ] Sub. Code &Name: EC8351– ELECTRONIC CIRCUITS I Date:08/10/2018 Year/branch/section: II-ECE Session &Duration: FN & 1hr 30 min. Semester: 03 Max. Mark: 50 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING ACADEMIC YEAR 2018-2019 (ODD SEMESTER) PART B (3×12=36) (Answer all Questions under “either or “ type) PART B&C QUESTION TEST 1 a) What are the types of compensation technique in BJT? and explain all Sub. Code &Name: EC8351– ELECTRONIC CIRCUITS I Date:08/10/2018 the Compensation techniques in detail. (12) Year/branch/section: II-ECE Session &Duration: FN & 1hr 30 min. (OR) Semester: 03 Max. Mark: 50 b) Construct voltage divider bias of BJT and formulate the Stability PART B (3×12=36) (Answer all Questions under “either or “ type) factors. (12) 1 a) What are the types of compensation technique in BJT? and explain all the Compensation techniques in detail. (12) 2 a) Discuss in detail about the small signal analysis of common source amplifier with un bypassed capacitor (12) (OR) (OR) b) Construct voltage divider bias of BJT and formulate the Stability factors. (12) b) Construct the small signal equivalent model of CC amplifier circuit and analyze the circuit to obtain its gain, input and output impedance. (12) 2 a) Discuss in detail about the small signal analysis of common source amplifier with un bypassed capacitor (12) 3 a) Discuss in detail about the analysis of Darlington amplifier and derive an expression for Ai and Ri. (12) (OR) (OR) b) Construct the small signal equivalent model of CC amplifier circuit and analyze the circuit to obtain its gain, input and output impedance. (12) b) Sketch emitter coupled differential amplifier and determine the differential Mode gain, Common mode gain and CMRR. (12) 3 a) Discuss in detail about the analysis of Darlington amplifier and derive an expression for Ai and Ri. (12) PART C (1×14=14) (Answer all Questions under “either or “ type) (OR) 4 a) Design the voltage divider bias circuit to have V CE=VE=5V, the (14) b) Sketch emitter coupled differential amplifier and determine the supply voltage is 15V, Assume the transistor hfe is 100 and ICQ=4mA. differential Mode gain, Common mode gain and CMRR. (12) (OR) b) Experiment the circuit shown in figure and evaluate the small signal PART C (1×14=14) (Answer all Questions under “either or “ type) voltage gain assume. Idss=12mA,Vp=-4V and λ =0.005V-1 4 a) Design the voltage divider bias circuit to have V CE=VE=5V, the (14) supply voltage is 15V, Assume the transistor hfe is 100 and ICQ=4mA. (OR) b) Experiment the circuit shown in figure and evaluate the small signal voltage gain assume Idss=12mA,Vp=-4V and λ =0.005V-1 Prepared By HOD [P.MANOJ]