Es ZG621 Revised Handout

First Semester 2020-2021
Course Title VLSI DESIGN
Course No ES ZG621 / MEL ZG621
Lead Instructor VILAS GAIDHANE
Contact Hour 1
Type Content Ref. Topic Title Study/HW Resource Reference
Pre CH Historical perspective of VLSI design T2 – 1.1
1.1 Overview of VLSI design T1 – 1.4, T2 – 1.1

methodologies
During CH
1.2 VLSI design flow T1 – 1.5
1.3 VLSI design styles T1 – 1.8
1.4 VLSI design quality T1 – 1.9
1.5 Issues in digital integrated IC design T2 – 1.2
Post CH
Contact Hour 2
Pre CH
2.1 Structure and operation of MOS T1 – 3.1 to 3.3

During CH transistor under external bias T2 – 3.3.1
R2 – 2.1, 2.2
2.2 MOSFET current - voltage T1 – 3.4

characteristics T2 – 3.3.2 – 3.3.4
R2 – 2.5
Post CH Quality metrics of a digital design T2 – 1.3
Contact Hour 3
Pre CH Scaling models and factors R1 – 5.1, 5.2

Manufacturing CMOS ICs T2 – 2.2
During CH 2.3 MOSFET scaling and small T1 – 3.5

geometry effects T2 – 3.5
R2 – 2.4
2.4 MOSFET capacitances T1 – 3.6

R2 – 2.3
Post CH
Contact Hour 4
Pre CH
During CH 3.1 Fabrication process flow: basic T1 – 2.1, 2.2

steps T2 – 2.2.1, 2.2.2
R2 – 1.5.1 – 1.5.2
3.2 CMOS n-well process T1 – 2.3

T2 – 2.2.4
Post CH MOS fabrication technologies R1 – 1.7, 1.8
Contact Hour 5
Pre CH Introduction T2 – 2.1
During CH 3.3 Layout design rules T1 – 2.4

T2 – 2.3
R2 – 1.5.3 – 1.5.5
3.4 Full custom mask layout design T1 – 2.5
Post CH
Contact Hour 6
Pre CH
During CH 4.1 Resistive Load Inverter T1 – 5.2
4.2 Inverters with n-type MOSFET load T1 – 5.3
Post CH Lab manual Design and simulation of MOS

inverter and plot its characteristics
Contact Hour 7
Pre CH Basic circuit concepts of CMOS R1 – 2.10, 4.3, 4.6, 4.7

inverter
During CH 4.3 CMOS inverter T1 – 5.4

T2 – 5.2, 5.3
Post CH
Contact Hour 8
Pre CH
During CH 5.1 Delay time definitions and T1 – 6.1, 6.2, 6.3

calculation T2 – 5.4
R2 – 4.1 – 4.3
5.2 Inverter design with delay T1 – 6.4

constraints T2 – 5.4
Post CH Lab Manual Design and verify the layout of
CMOS inverter
Contact Hour 9
Pre CH
During CH 5.3 Switching power dissipation of T1 – 6.7

CMOS inverters T2 - 5.5.1 – 5.5.3
Post CH
Contact Hour 10
Pre CH
During CH 6.1 MOS logic circuits with depletion T1 – 7.2

nMOS load
6.2 CMOS logic circuits T1 – 7.3

T2 – 6.2.1
Post CH Design and simulation of basic

CMOS gates
Contact Hour 11
Pre CH
During CH 6.3 Complex CMOS logic circuits T1 – 7.4, 6.2.2, 6.2.3

R2 – 9.2
6.4 CMOS transmission gates T1 – 7.5
R1 – 6.2
Post CH How to choose a logic style T2 – 6.4
Logical effort R2 – 4.5
Contact Hour 12
Pre CH Delay constraints R2 – 10.2
During CH 7.1 Timing metrics for sequential T2 – 7.1

circuits
7.2 Behaviour of bi-stable elements T1 – 8.2

T2 – 7.2.1, 7.2.2
7.3 SR latch circuit T1 – 8.3

T2 – 7.2.4, 7.2.5
R2 – 10.3.1, 10.3.3 – 10.3.6
Post CH Lab manual Design and simulation of S-R

latches
Contact Hour 13
Pre CH
During CH 7.4 Clocked latch and flip-flop circuits T1 – 8.4
7.5 CMOS D-latch and edge-triggered T1 – 8.5

flip-flop T2 – 7.2.3, 7.3.1, 7.3.2
R2 – 10.3.2
Post CH Lab manual Design and simulation of edge
triggered D flip-flop
Contact Hour 14
Pre CH
During CH 7.6 Latch vs register based pipeline T2 – 7.5.1
7.7 NORA-CMOS T2 – 7.5.2
Post CH The Schmitt trigger T2 – 7.6.1
Contact Hour 15 and 16: REVIEW SESSION
Contact Hour 17
Pre CH
During CH 8.1 Basic principles of pass transistor T1 – 9.1, 9.2

circuits T2 – 7.3.1
8.2 Voltage bootstrapping T1 – 9.3
Post CH
Contact Hour 18
Pre CH
During CH 8.3 Synchronous dynamic circuit T1 – 9.4, 9.5

techniques T2 – 6.3.1, 6.3.2, 7.3.2
8.4 High performance dynamic CMOS T1 – 9.6

circuits T2 – 6.3.3, 6.3.4, 7.3.3
Post CH Lab manual Design and simulation basic
Dynamic logic circuits
Contact Hour 19
Pre CH Introduction R2 – 5.1, 5.2
During CH 9.1 Overview of power consumption T1 – 11.1, 11.2

T2 – 5.5
9.2 Low power design through voltage T1 – 11.3

scaling
9.3 Estimation and Optimization of T1 – 11.4

switching activity
Post CH
Contact Hour 20
Pre CH
During CH 9.4 Reduction of switched capacitance T1 – 11.5

T2 – 11.7.1, 11.7.2
9.5 Adiabatic logic circuits T1 – 11.6

T2 – 11.7.3
Post CH Low power architectures R2 – 5.5
Contact Hour 21
During CH 10.1 Electrical wire model T2 – 4.3, 4.4
10.2 Capacitive parasitics T2 – 9.2

Post CH Logical effort with wires R2 – 6.5
Contact Hour 22
Pre CH
During CH 10.3 Resistive parasitics T2 – 9.3
10.4 Inductive parasitics T2 – 9.4
Post CH Networks on chip T2 – 9.6
Contact Hour 23
Pre CH Choosing a clock strategy T2 – 7.7
During CH 11.1 Timing classification of digital T2 – 10.2

systems
Post CH
Contact Hour 24
Pre CH
During CH 11.2 Synchronous design (Synchronous T2 – 10.3

timing basics, Source of skew and R2 – 13.4
jitter, Clock distribution
techniques, Latch based clocking)
Post CH Clock Synthesis and T2 – 10.6.1, 10.6.2
Synchronization Using a Phase-
Locked Loop
Contact Hour 25
During CH 12.1 Datapaths in digital processors T2 – 11.2

architectures
12.2 Adder architectures T2 – 11.3

R2 – 11.2.1 – 11.2.5
Post CH
Contact Hour 26
Pre CH
During CH 12.3 Multiplier architectures T2 – 11.4

R2 – 11.9
12.4 The shifter architectures T2 – 11.5

R2 – 11.8
Post CH Lab manual Design and simulation of basic

datapath architectures
Contact Hour 27
Pre CH Memory classification and T2 – 12.1

architecture
During CH 13.1 Read Only Memory circuits T1 – 10.4

T2 - 12.2.1, 12.2.2
R2 – 12.4
13.2 Static RAM circuits T1 – 10.3
T2 – 12.2.3
R2 – 12.2
Post CH
Contact Hour 28
Pre CH
During CH 13.3 Design of Dynamic RAM cells T1 – 10.2

R2 – 12.3
Memory peripheral circuits T2 – 12.3
Post CH Case Studies in Memory Design T2 – 12.6.1, 12.6.2
Contact Hour 29
Pre CH Introduction T2 – H.1
R2 – 15.1
During CH 14.1 Fault types and models T1 – 15.1, 15.2

T2 – H.4.1
R2 – 15.5.1, 15.5.6
14.2 Controllability and observability T1 – 15.3

T2 – H.3.1
R2 – 15.5.2 – 15.5.3
14.3 Ad hoc testable design techniques T1 – 15.4

T2 – H.3.2
R2 – 15.6.1
Post CH
Contact Hour 30

Pre CH
During CH 14.4 Scan based techniques T1 – 15.5

T2 – H.3.3, H.3.4
R2 – 15.6.2
14.5 Built-in self-test (BIST) techniques T1 – 15.6

T2 – H.3.5
R2 – 15.6.3
Post CH Logic Verification principles R2 – 15.3
Contact Hour 31 and 32: REVIEW SESSION
Laboratory Details: Lab sheets would be provided on the course page to carry out the experiments using open
source tool, Electric VLSI Design System. The students must download the software on their computing system
using Windows/Unix/Macintosh OS with java enabled. The link to download the software is provided in the lab
manual. Two evaluation components would be conducted on lab.
Evaluation Scheme:
Legend: EC = Evaluation Component; AN = After Noon Session; FN = Fore Noon Session
No Name Type Duration Weight Day, Date, Session, Time
EC-1 Quiz-I Online - 5% September 10-20, 2020
Quiz-II Online 5% October 20-30, 2020
Quiz-III Online 5% November 10-20, 2020
EC-2 Mid-Semester Test Closed 2 hours 35% Sunday, 11/10/2020 (FN)
Book 10 AM - 12 Noon
EC-3 Comprehensive Exam Open Book 3 hours 50% Sunday, 29/11/2020 (FN)
9 AM – 12 Noon
Note: If Assignment kindly remove Quiz-I, II, III

Syllabus for Mid-Semester Test (Closed Book): Topics in Session Nos. 1 to 16
Syllabus for Comprehensive Exam (Open Book): All topics (Session Nos. 1 to 32)
Important links and information:
Elearn portal: https://elearn.bits-pilani.ac.in
Students are expected to visit the Elearn portal on a regular basis and stay up to date with the latest
announcements and deadlines.
Contact sessions: Students should attend the online lectures as per the schedule provided on the Elearn portal.
Evaluation Guidelines:
1. EC-1 consists of either two Assignments or three Quizzes. Students will attempt them through the
course pages on the Elearn portal. Announcements will be made on the portal, in a timely manner.
2. For Closed Book tests: No books or reference material of any kind will be permitted.
3. For Open Book exams: Use of books and any printed / written reference material (filed or bound) is
permitted. However, loose sheets of paper will not be allowed. Use of calculators is permitted in all
exams. Laptops/Mobiles of any kind are not allowed. Exchange of any material is not allowed.
4. If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the student should
follow the procedure to apply for the Make-Up Test/Exam which will be made available on the Elearn
portal. The Make-Up Test/Exam will be conducted only at selected exam centres on the dates to be
announced later.
It shall be the responsibility of the individual student to be regular in maintaining the self study schedule as
given in the course handout, attend the online lectures, and take all the prescribed evaluation components such
as Assignment/Quiz, Mid-Semester Test and Comprehensive Exam according to the evaluation scheme provided
in the handout.

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First Semester 2020-2021

Course Title VLSI DESIGN

Course No ES ZG621 / MEL ZG621

Lead Instructor VILAS GAIDHANE

Type Content Ref. Topic Title Study/HW Resource Reference

Pre CH Historical perspective of VLSI design T2 – 1.1

1.1 Overview of VLSI design T1 – 1.4, T2 – 1.1

1.3 VLSI design styles T1 – 1.8

1.4 VLSI design quality T1 – 1.9

1.5 Issues in digital integrated IC design T2 – 1.2

Type Content Ref. Topic Title Study/HW Resource Reference

2.1 Structure and operation of MOS T1 – 3.1 to 3.3

2.2 MOSFET current - voltage T1 – 3.4

Post CH Quality metrics of a digital design T2 – 1.3

Pre CH Scaling models and factors R1 – 5.1, 5.2

During CH 2.3 MOSFET scaling and small T1 – 3.5

2.4 MOSFET capacitances T1 – 3.6

Type Content Ref. Topic Title Study/HW Resource Reference

During CH 3.1 Fabrication process flow: basic T1 – 2.1, 2.2

3.2 CMOS n-well process T1 – 2.3

Post CH MOS fabrication technologies R1 – 1.7, 1.8

Type Content Ref. Topic Title Study/HW Resource Reference

Pre CH Introduction T2 – 2.1

During CH 3.3 Layout design rules T1 – 2.4

3.4 Full custom mask layout design T1 – 2.5

Type Content Ref. Topic Title Study/HW Resource Reference

During CH 4.1 Resistive Load Inverter T1 – 5.2

4.2 Inverters with n-type MOSFET load T1 – 5.3

Post CH Lab manual Design and simulation of MOS

Type Content Ref. Topic Title Study/HW Resource Reference

Pre CH Basic circuit concepts of CMOS R1 – 2.10, 4.3, 4.6, 4.7

During CH 4.3 CMOS inverter T1 – 5.4

Type Content Ref. Topic Title Study/HW Resource Reference

During CH 5.1 Delay time definitions and T1 – 6.1, 6.2, 6.3

5.2 Inverter design with delay T1 – 6.4

Type Content Ref. Topic Title Study/HW Resource Reference

During CH 5.3 Switching power dissipation of T1 – 6.7

Type Content Ref. Topic Title Study/HW Resource Reference

During CH 6.1 MOS logic circuits with depletion T1 – 7.2

6.2 CMOS logic circuits T1 – 7.3

Post CH Design and simulation of basic

Type Content Ref. Topic Title Study/HW Resource Reference

During CH 6.3 Complex CMOS logic circuits T1 – 7.4, 6.2.2, 6.2.3

Post CH How to choose a logic style T2 – 6.4

Logical effort R2 – 4.5

Type Content Ref. Topic Title Study/HW Resource Reference

Pre CH Delay constraints R2 – 10.2

During CH 7.1 Timing metrics for sequential T2 – 7.1

7.2 Behaviour of bi-stable elements T1 – 8.2

7.3 SR latch circuit T1 – 8.3

Post CH Lab manual Design and simulation of S-R

Type Content Ref. Topic Title Study/HW Resource Reference

During CH 7.4 Clocked latch and flip-flop circuits T1 – 8.4

7.5 CMOS D-latch and edge-triggered T1 – 8.5

Type Content Ref. Topic Title Study/HW Resource Reference

During CH 7.6 Latch vs register based pipeline T2 – 7.5.1

7.7 NORA-CMOS T2 – 7.5.2

Post CH The Schmitt trigger T2 – 7.6.1

Contact Hour 15 and 16: REVIEW SESSION

Type Content Ref. Topic Title Study/HW Resource Reference

During CH 8.1 Basic principles of pass transistor T1 – 9.1, 9.2

8.2 Voltage bootstrapping T1 – 9.3