Digital Electronics: CT 304N

Unit–4 (Part:1)
Flip Flops
&
Sequential Logic and Circuits

Dr. Anand J. Patel

Combinational circuits
• Combinational circuits :
Combinational circuits are defined as the time independent circuits
which do not depends upon previous inputs to generate any output
are termed as combinational circuits.

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Sequential circuits
• Sequential circuits :
Sequential circuits are those which are dependent on clock cycles and
depends on present as well as past inputs to generate any output.

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Difference
Sr. No. Combinational Circuit Sequential Circuit

1 The output depends only upon the present

The output depends upon both present input and
input and there is no need for feedback for
present state (previous output), so memory element
input and output, so memory element is not
is required to save the feedback state.
required.
2 It is not easier to design, use and handle than
It is easier to design, use and handle.
combinational circuits.

3 Clock signals are not required and it is not Clock signals are required and it is dependent on
dependent on time. time and clock so need triggering.

4 Elementary building blocks are only logic

Elementary building blocks are Flip-Flops.
gates.
5 These circuits are slower than combinational
These are faster logic circuits.
circuits.
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 Sequential Circuits

Every digital system is likely to have combinational circuits,

most systems encountered in practice also include storage
elements, which require that the system be described in term
of sequential logic.

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Sequential circuits
Sequential circuits can be Asynchronous or
synchronous.
Asynchronous sequential circuits change their states
and output values whenever a change in input
values occurs.
Synchronous sequential circuits change their states
and output values at fixed points of time, i.e. clock
signals.
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Synchronous Clocked Sequential Circuit

A sequential circuit may use many flip-flops to store as many

bits as necessary. The outputs can come either from the
combinational circuit or from the flip-flops or both.

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Memory Devices
Latches A latch is a memory element whose excitation
signals control the state of the device. A latch has two
stages set and reset. Set stage sets the output to 1.
Reset stage set the output to 0.
Flip-flops A flip-flop is a memory device that has clock
signals control the state of the device.

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 Latches: SR Latch

The SR latch is a circuit with two cross-coupled NOR gates or

two cross-coupled NAND gates. It has two inputs labeled S
for set and R for reset.

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SR Latch with NAND Gates

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Timing Diagram of RS-Latch

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SR Latch with Control Input
The operation of the basic SR latch can be modified by
providing an additional control input that determines when
the state of the latch can be changed. In Fig. 5-5, it consists
of the basic SR latch and two additional NAND gates.

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D Latch

One way to eliminate the undesirable condition of the

indeterminate state in SR latch is to ensure that inputs S
and R are never equal to 1 at the same time in Fig 5-5. This
is done in the D latch.

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Graphic Symbols for latches
A latch is designated by a rectangular block with inputs on
the left and outputs on the right. One output designates the
normal output, and the other designates the complement
output.

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 Flip-Flops
• The state of a latch or flip-flop is switched by a change in the control input.
• This momentary change is called a trigger and the transition it cause is
said to trigger the flip-flop.
• The D latch with pulses in its control input is essentially a flip-flop that is
triggered every time the pulse goes to the logic 1 level.
• As long as the pulse input remains in the level, any changes in the data
input will change the output and the state of the latch.

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 Clock Response in Latch

In Fig (a) a positive level response in the control input

allows changes, in the output when the D input changes
while the clock pulse stays at logic 1.

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Clock Response in Flip-Flop

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Latch Flip-flop

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Latch and Flip-Flop Devices
Device # of Description
Elements
74LS73A 2 Negative-edge triggered JK flip-flop with clear
7474 2 Positive-edge triggered D flip-flop with preset and clear
74LS75 4 D Latch with enable
7476 2 Pulse-edge triggered JK flip-flop with preset and clear
74111 2 Master-slave JK flip-flop with preset, clear, and data lock out
74116 2 4-bit hazard-free D latch with clear and dual enable
74175 4 Positive-edge triggered D flip-flop with clear
74273 8 Positive-edge triggered D flip-flop with clear
74276 4 Negative-edge triggered JK flip-flop with preset and clear
74279 4 SR latch with active-low inputs
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Edge-Triggered D Flip-Flop

The first latch is called the master and the second the
slave. The circuit samples the D input and changes its output
Q only at the negative-edge of the controlling clock.

D 110011…
Y 110011…
Q ? 1 1 0 0 1 ….
CLK
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 D-Type Positive-Edge-Triggered Flip-Flop

Another more efficient construction of an edge-triggered D

flip-flop uses three SR latches. Two latches respond to the
external D(data) and CLK(clock) inputs. The third latch
provides the outputs for the flip-flop.

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Graphic Symbol for Edge-Triggered D Flip-Flop

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JK Flip Flop

Clk J K Qn+1
No
X X X
change

No
1 0 0
change

1 0 1 0
1 1 0 1
Toggle
1 1 1
(Q’)

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Racing in JK Flip Flop
• For this simple J K flip flop, the toggling will occur as soon as J=k=1
and clock is high (1) and the rate of toggling would be determined by
the propagation delay around the circuit. Thus, this makes the output
of the flip flop unpredictable at anytime from the clock state. This is
called ‘race around condition’ or racing.
• Therefore, to avoid such a condition we use a Master Slave circuit
arrangement. Using this makes the transmission of the J value
delayed by half a clock cycle to the output and thus not immediately
fed back to the input side.

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Master-Slave JK Flip-Flop

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 JK Flip-Flop
There are three operations that can be performed with a flip-flop: set it to 1,
reset it to 0, or complement its output. The JK flip-flop performs all three
operations. The circuit diagram of a JK flip-flop constructed with a D flip-
flop and gates.

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 JK Flip-Flop
The J input sets the flip-flop to 1, the K input resets it to 0, and when both
inputs are enabled, the output is complemented. This can be verified by
investigating the circuit applied to the D input:
D = J Q` + K` Q

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 T Flip-Flop

The T(toggle) flip-flop is a complementing flip-flop and can be obtained

from a JK flip-flop when inputs J and K are tied together.

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 T Flip-Flop

The T flip-flop can be constructed with a D flip-flop and an exclusive-OR

gates as shown in Fig. (b). The expression for the D input is

D=T Q = TQ` + T`Q

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Characteristic Tables

• Defines the logical properties of a flip-flop (such as a truth table does

for a logic gate).
• Q(t) – present state at time t
• Q(t+1) – next state at time t+1
Characteristic Tables (cont.)
SR Flip-Flop
S R Q(t+1) Operation
0 0 Q(t) No change/Hold
0 1 0 Reset
1 0 1 Set
1 1 ? Undefined/Invalid

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Characteristic Tables (cont.)
D Flip-Flop
D Q(t+1) Operation
0 0 Set
1 1 Reset

Characteristic Equation: Q(t+1) = D(t)

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 Characteristic Equations

D flip-flop Characteristic Equations

Q(t + 1) = D

JK flip-flop Characteristic Equations

Q(t + 1) = JQ` + K`Q

T flip-flop Characteristic Equations

Q(t + 1) = T Q = TQ` + T`Q

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JK Flip Flop

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 Direct Inputs

• Some flip-flops have asynchronous inputs that are used to force the flip-
flop to a particular state independent of the clock.
• The input that sets the flip-flop to 1 is called preset or direct set.
• The input that clears the flip-flop to 0 is called clear or direct reset.
• When power is turned on a digital system, the state of the flip-flops is
unknown.
• The direct inputs are useful for bringing all flip-flops in the system to a
known starting state prior to the clocked operation.

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D Flip-Flop with Asynchronous Reset

A positive-edge-triggered D flip-flop with asynchronous reset

is shown in Fig(a).

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D Flip-Flop with Asynchronous Reset

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Applications of Flip Flops
• There are various applications of the flip flops as they are one of the
most basic unit in electronic circuits. Some are specified as follows:
• Shift Registers
• Frequency dividers
• Storage registers (Memory)
• Counters

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Unit-4 (Part:1)

The End

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