CXP86212/86216, CXP86324/86332

CXP86440/86448/86460
CMOS 8-bit Single Chip Microcomputer

Description
The CXP86212/86216, CXP86324/86332, CXP86440/ 64 pin SDIP (Plastic) 64 pin QFP (Plastic)
86448/86460 are the CMOS 8-bit single chip
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time-base
timer, on-screen display function, I2C bus interface,
PWM output, remote control reception circuit, HSYNC
counter, watchdog timer, 32kHz timer/counter besides
the basic configurations of 8-bit CPU, ROM, RAM, I/O
ports.
The CXP86212/86216, CXP86324/86332, CXP86440/
86448/86460 also provide a SLEEP function that
enables to lower the power consumption.

Features 64 pin LQFP (Plastic)

• A wide instruction set (213 instructions) which covers
various types of data
– 16-bit operation/multiplication and division/
Boolean bit operation instructions
• Minimum instruction cycle 250ns at 16MHz operation
122µs at 32kHz operation
• Incorporated ROM 12K bytes (CXP86212)
24K bytes (CXP86324)
40K bytes (CXP86440)
16K bytes (CXP86216)
32K bytes (CXP86332)
48K bytes (CXP86448)
60K bytes (CXP86460) Structure
• Incorporated RAM 352 bytes (CXP86212/86216) 704 bytes (CXP86324/86332) Silicon gate CMOS IC
1536 bytes (CXP86440/86448/86460)
(Excludes VRAM for on-screen display and sprite RAM)
• Peripheral functions
– A/D converter 8-bit 6-channel successive approximation method
(Conversion time of 3.25µs at 16MHz)
– Serial interface 8-bit clock sync type, 1 channel
– Timer 8-bit timer
8-bit timer/counter
19-bit time-base timer
32 kHz timer/counter
– On-screen display (OSD) function 12 × 16 dots, 128 character types (CXP86212/86216),
256 character types (CXP86324/86332),
384 character types (CXP86440/86448/86460)
15 character colors, 2 lines × 24 characters,
frame background 8 colors/ half blanking,
background on full screen 15 colors/ half blanking
edging/ shadowing/ rounding for every line,
background with shadow for every character (CXP86440/86448/86460),
double scanning,
sprite OSD (CXP86440/86448/86460),
12 × 16 dots, 1 screen, 8 colors for every dot
– I2C bus interface
– PWM output 8 bits, 8 channels
14 bits, 1 channel
– Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO
– HSYNC counter 2 channels
– Watchdog timer
• Interruption 13 factors, 13 vectors, multi-interruption possible
• Standby mode Sleep
• Package 64-pin plastic SDIP/QFP/LQFP
• Piggyback/evaluator CXP86400 64-pin ceramic PQFP
CXP86490 64-pin ceramic PSDIP (Supports custom font)
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E96644A86
 Block Diagram

INT2
MP

EXTAL

INT1
VSS

RST

TX

INT0
VDD

XTAL

TEX
CLOCK GENERATOR
A/D CONVERTER SPC700 CPU CORE
AN0 to AN5 6 /SYSTEM CONTROL 8 PA0 to PA7
6CH

PORT A
RMC REMOCON FIFO ROM
RAM 8 PB0 to PB7
12K/16K/24K/32K/
352/704/1536 BYTES PORT B
40K/48K/60K BYTES
SI
SERIAL INTERFACE
SO 6 PC0 to PC5

INTERRUPT CONTROLLER
UNIT
SCK
PORT C

2 PC6 to PC7
8BIT TIMER/
EC 2
COUNTER 0
TO 8BIT TIMER 1 8 PD0 to PD7
PORT D

XLC
EXLC 2 PRESCALER/ 2 PE0 to PE1
R TIME BASE TIMER

–2–
G 2 PE2 to PE3
PORT E

B ON SCREEN 3 PE4 to PE6

I DISPLAY WATCHDOG TIMER
YS
YM 8 PF0 to PF7
32kHz
PORT F

HSYNC
TIMER/COUNTER
VSYNC

5 PG3 to PG7
HS0 HSYNC COUNTER 0
PORT G

2
I2C BUS
8BIT PWM 14BIT PWM
HS1 HSYNC COUNTER 1 INTERFACE UNIT

8
ADJ
PWM

SCL1

SCL0

SDA1

SDA0
PWM0 to PWM7
CXP86212/86216, CXP86324/86332, CXP86440/86448/86460
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Pin Assignment (Top View) 64-pin SDIP

PC3 1 64 PC4
PC2 2 63 PC5
PC1 3 62 PC6/PWM6
PC0 4 61 PC7/PWM7
EC/PD7 5 60 PF0/PWM0
RMC/PD6 6 59 PF1/PWM1
HS1/PD5 7 58 PF2/PWM2
HS0/PD4 8 57 PF3/PWM3
SI/PD3 9 56 PF4/SCL0
SO/PD2 10 55 PF5/SCL1/PWM4
SCK/PD1 11 54 PF6/SDA0
INT2/PD0 12 53 PF7/SDA1/PWM5
HSYNC/PA7 13 52 PE0/TO/ADJ
VSYNC/PA6 14 51 PE1/PWM
RST 15 50 PE2/TEX/INT0
VSS 16 49 PE3/TX
XTAL 17 48 VSS
EXTAL 18 47 VDD
PA5/AN5 19 46 NC
PA4/AN4 20 45 EXLC
PA3/AN3 21 44 XLC
PA2/AN2 22 43 PE4/YM
PA1/AN1 23 42 PE5/YS
PA0/AN0 24 41 PE6/I
PB7 25 40 B
PB6 26 39 G
PB5 27 38 R
PB4 28 37 PB0
PB3 29 36 PB1
INT1/PG7 30 35 PB2
PG6 31 34 PG3
PG5 32 33 PG4

Note)
1. NC (Pin 46) is left open.
2. Vss (Pins 16 and 48) are both connected to GND.

–3–
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Pin Assignment (Top View) 64-pin QFP

PC7/PWM7
PC6/PWM6

PF2/PWM2
PF1/PWM1
PF0/PWM0
PD6/RMC
PD7/EC

PC1
PC0

PC5
PC4
PC3
PC2
64 63 62 61 60 59 58 57 56 55 54 53 52

HS1/PD5 1 51 PF3/PWM3
HS0/PD4 2 50 PF4/SCL0
SI/PD3 3 49 PF5/SCL1/PWM4
SO/PD2 4 48 PF6/SDA0
SCK/PD1 5 47 PF7/SDA1/PWM5
INT2/PD0 6 46 PE0/TO/ADJ
HSYNC/PA7 7 45 PE1/PWM
VSYNC/PA6 8 44 PE2/TEX/INT0
RST 9 43 PE3/TX
VSS 10 42 VSS
XTAL 11 41 VDD
EXTAL 12 40 NC
PA5/AN5 13 39 EXLC
PA4/AN4 14 38 XLC
PA3/AN3 15 37 PE4/YM
PA2/AN2 16 36 PE5/YS
PA1/AN1 17 35 PE6/I
PA0/AN0 18 34 B
PB7 19 33 G

20 21 22 23 24 25 26 27 28 29 30 31 32
PB2
PB3

PG3
PB4

PG4
PB5

R
PG5
PB6

PB0
PG6

PB1
INT1/PG7

Note)
1. NC (Pin 40) is left open.
2. Vss (Pins 10 and 42) are both connected to GND.

–4–
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Pin Assignment (Top View) 64-pin LQFP

PC7/PWM7
PC6/PWM6

PF2/PWM2
PF1/PWM1

PF3/PWM3
PF0/PWM0
PD6/RMC
PD4/HS0
PD5/HS1

PD7/EC

PC4
PC1
PC0

PC2

PC5
PC3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

SI/PD3 1 48 PF4/SCL0
SO/PD2 2 47 PF5/SCL1/PWM4
SCK/PD1 3 46 PF6/SDA0
INT2/PD0 4 45 PF7/SDA1/PWM5
HSYNC/PA7 5 44 PE0/TO/ADJ
VSYNC/PA6 6 43 PE1/PWM
RST 7 42 PE2/TEX/INT0
VSS 8 41 PE3/TX
XTAL 9 40 VSS
EXTAL 10 39 VDD
PA5/AN5 11 38 NC
PA4/AN4 12 37 EXLC
PA3/AN3 13 36 XLC
PA2/AN2 14 35 PE4/YM
PA1/AN1 15 34 PE5/YS
PA0/AN0 16 33 PE6/I

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PB5

PG5

PB0
PB3

PG3

G
PG6
PB6

PB1
PB4

PG4

R
INT1/PG7
PB7

PB2

Note)
1. NC (Pin 38) is left open.
2. Vss (Pins 8 and 40) are both connected to GND.

–5–
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Pin Description

Symbol I/O Description

PA0/AN0
I/O/ (Port A) Analog inputs to A/D converter.
to
Analog input 8-bit I/O port. (6 pins)
PA5/AN5 I/O can be set in a
PA6/VSYNC I/O/Input unit of single bits. OSD display vertical sync signal input.
(8 pins)
PA7/HSYNC I/O/Input OSD display horizontal sync signal input.
(Port B)
PB0 to PB7 I/O 8-bit I/O port. I/O can be set in a unit of single bits.
(8 pins)

(Port C)
Lower 6 bits are I/O ports; I/O can be set in a unit of single bits. Upper
PC0 to PC5 I/O
2 bits are output port and large current (12mA) N-channel open drain
output. Upper 2 bits are medium drive voltage (12V); lower 6 bits are
5V drive.
PC6/PWM6 to (8 pins) 8-bit PWM output.
Output/Output
PC7/PWM7 (2 pins)
External interruption request input. Active at the
PD0/INT2 I/O/Input
falling edge.
PD1/SCK I/O/I/O (Port D) Serial clock I/O.
PD2/SO I/O/Output 8-bit I/O port. I/O Serial data output.
can be set in a
PD3/SI I/O/Input unit of single bits. Serial data input.
PD4/HS0 I/O/Input Can drive 12mA HSYNC counter (CH0) input.
synk current.
PD5/HS1 I/O/Input (8 pins) HSYNC counter (CH1) input.
PD6/RMC I/O/Input Remote control reception circuit input.
PD7/EC I/O/Input External event input for timer/counter.
I/O/Output/ Rectangular wave output 32kHz oscillation
PE0/TO/ADJ frequency dividing output.
Output for 8-bit timer/counter.
PE1/PWM I/O/Output 14-bit PWM output.
(Port E)
Bits 0 and 1 are I/O External interruption
Input/Input/ Connects a crystal for
PE2/TEX/INT0 port; I/O can be set request input. Active at
Input 32kHz timer/counter
in a unit of single. the falling edge.
clock oscillation. When
Bits 2 and 3 are
used as an event
PE3/TX Input/Output input port. Bits 4, 5
counter, input to TEX pin and leave TX pin open.
and 6 are output
port.
PE4/YM Output/Output
(7 pins)
PE5/YS Output/Output
PE6/I Output/Output OSD display 6-bit output.
B Output (6 pins)

G Output
R Output

–6–
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Symbol I/O Description

PF0/PWM0 to (Port F) 8-bit PWM output.
Output/Output
PF3/PWM3 8-bit output port (4 pins)
and large current
PF4/SCL0 Output/I/O I2C bus interface transfer clock I/O.
(12mA) N-channel
(2 pins)
PF5/SCL1/ Output/I/O/ open drain output.
8-bit PWM output.
PWM4 Output Lower 4 bits are
medium drive
PF6/SDA0 Output/I/O I2C bus interface transfer data I/O.
voltage (12V); upper
(2 pins)
PF7/SDA1/ Output/I/O/ 4 bits are 5V drive.
8-bit PWM output.
PWM5 Output (8 pins)
(Port G)
PG3 to PG6 I/O
5-bit I/O port. I/O can be set in a unit of single bits.
(5 pins)
External interruption request input.
PG7/INT1 I/O/Input
Active at the falling edge.
EXTAL Input Connects a crystal for system clock oscillation. When a clock is
supplied externally, input to EXTAL pin and input a reversed phase
XTAL Output clock to XTAL pin.
RST Input System reset; active at Low level.
EXLC Input OSD display clock oscillation I/O. Oscillation frequency is determined
XLC Output by the external L and C.

NC No connected.
VDD Positive power supply.
Vss GND. Connect two Vss pins to GND.

–7–
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Input/Output Circuit Formats for Pins

Pin Circuit format When reset

Port A

Port A data

Port A direction

PA0/AN0 “0” when reset

to
PA5/AN5 Data bus IP Hi-Z
Input
RD (Port A)
protection
circuit
Port A function selection
“0” when reset Input multiplexer
A/D converter

6 pins

Port A
Port A data

Port A direction
PA6/VSYNC “0” when reset
PA7/HSYNC
Data bus Schmitt input Hi-Z
IP

RD (Port A)

HSYNC, VSYNC Input polarity

2 pins “0” when reset

Port B
Ports B, C, G data
Port C
PB0 to PB7 Port G Ports B, C, G direction
PC0 to PC5 “0” when reset
PG3 to PG6
Schmitt input Hi-Z
PG7/INT1
Data bus only for PG7 IP

RD (Ports B, C, G)

19 pins INT1

Port C
Port F
PWM0 to PWM3
PC6/PWM6
PWM6, PWM7
PC7/PWM7
PF0/PWM0 Ports C and F
to function selection Hi-Z
PF3/PWM3 “0” when reset ∗

Ports C and F data

“1” when reset ∗ 12V drive voltage
6 pins Large current 12mA

–8–
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Pin Circuit format When reset

Port D
Port D data
PD0/INT2
PD3/SI Port D direction
PD4/HS0 “0” when reset ∗
PD5/HS1
Hi-Z
PD6/RMC
Data bus Schmitt input IP
PD7/EC
RD (Port D)

INT2, SI, HS0, ∗ Large current 12mA

HS1, RMC, EC
6 pins

Port D
SCK, SO
SIO output enable

Port D data
PD1/SCK
PD2/SO ∗
Port D direction Hi-Z
“0” when reset
IP
Schmitt input
Data bus only for PD1

RD (Port D)

2 pins SCK only ∗ Large current 12mA

Port E
Internal reset signal

Port E data 00
“1” when reset
TO 01 MPX
ADJ16K∗1 10 ∗2
ADJ2K∗1 11 High level
PE0/TO/ADJ (with
Port E function selection (Upper) approximately
Port E function selection (Lower) 150kΩ
∗1 ADJ signals are frequency resistor when
“00” when reset
dividing outputs for 32kHz reset)
Port E direction oscillation frequency IP
“1” when reset adjustment. ADJ2K provides
usage as buzzer output.
Data bus ∗2 Pull-up resistors approx. 150kΩ

1 pin RD (Port E)

–9–
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Pin Circuit format When reset

Port E
PWM
Port E function selection
“0” when reset
Port E data

PE1/PWM “1” when reset

High level
Port E direction
“1” when reset
IP
Data bus

RD (Port E)
1 pin

Port E
32kHz oscillation circuit control
“1” when reset
Schmitt input
INT0

Data bus

RD (Port E)
PE2/TEX/INT0
Data bus Oscillation
PE3/TX
halted
RD (Port E)
PE2/ Schmitt input Port input
TEX/ IP IP
INT0 Clock input

PE3/
2 pins TX

Port E

YM, YS, I
Output polarity
PE4/YM “0” when reset
PE5/YS
PE6/I Port E function selection Hi-Z
“0” when reset

Port E data

Writing data to output polarity

register and port data register
3 pins brings output to active.

– 10 –
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Pin Circuit format When reset

Port F SCL, SDA

I2C bus enable

∗

PF4/SCL0 PWM4, PWM5

PF5/SCL1/PWM4
Port F function selection
PF6/SDA0
“0” when reset Hi-Z
PF7/SDA1/PWM5
Port F data
“1” when reset Schmitt input

SCL, SDA IP
(I2C bus circuit)
BUS SW
4 pins ∗ Large current 12mA I 2C
To internal pins
(SCL1 for SCL0)

R, G, B

R Output polarity
G “0” when reset
B Hi-Z

Writing data to output

3 pins polarity register brings
output to active.

Oscillation control

EXLC IP OSD display clock

EXLC IP
XLC Oscillation
halted

2 pins XLC

EXTAL EXTAL IP
XTAL • Diagram shows the
circuit composition Oscillation
during oscillation.
• Feedback resistor is
XTAL removed during stop.
2 pins (This device does not
enter the stop mode.)

Pull-up resistor

RST
Low level

AA
OP Mask option
Schmitt input

AA
1 pin

– 11 –
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Absolute Maximum Ratings (Vss = 0V reference)

Item Symbol Ratings Unit Remarks

Supply voltage VDD –0.3 to +7.0 V
Input voltage VIN –0.3 to +7.0∗1 V
Output voltage VOUT –0.3 to +7.0∗1 V
Medium drive output voltage VOUTP –0.3 to +15.0 V
High level output current IOH –5 mA
High level total output current ∑IOH –50 mA Total of all output pins
Ports excluding large current output
IOL 15 mA
(value per pin)
Low level output current
Large current output ports
IOLC 20 mA
(value per pin∗2)
Low level total output current ∑IOL 130 mA Total of all output pins
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +150 °C
1000 mW SDIP-64P-01
Allowable power dissipation PD 600 mW QFP-64P-L01
380 mW LQFP-64P-L01
∗1 VIN and VOUT should not exceed VDD + 0.3 V.
∗2 The large current output port is Port C (PC6, PC7), Port D (PD) and Port F (PF).
Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should
be conducted under the recommended operating conditions. Exceeding those conditions may
adversely affect the reliability of the LSI.

Recommended Operating Conditions (Vss = 0V reference)

Item Symbol Min. Max. Unit Remarks

Guaranteed operation range for 1/2 and 1/4
4.5 5.5 V
frequency dividing modes
Guaranteed operation range for 1/16 frequency
VDD 3.5 5.5 V
Supply voltage dividing mode or sleep
2.7 5.5 V Guaranteed operation range for TEX mode
— — V Guaranteed data hold range for stop∗1
VIH 0.7VDD VDD V ∗2
High level input ∗3
VIHS 0.8VDD VDD V
voltage
VIHEX VDD – 0.4 VDD + 0.3 V EXTAL pin∗4, TEX pin∗5
VIL 0 0.3VDD V ∗2
Low level input ∗3
VILS 0 0.2VDD V
voltage
VILEX –0.3 0.4 V EXTAL pin∗4, TEX pin∗5
Operating temperature Topr –20 +75 °C
∗1 This device does not enter the STOP mode.
∗2 PA1 to 5, PB3 to 7, PC0 to PC5, PD2, PE0, PE1, PE3, PG3 to PG6, SCL0 to 1, SDA0 to 1 pins
∗3 VSYNC, HSYNC, INT2, SCK, SI, HS0, HS1, RMC, EC, INT0, INT1, RST pins
∗4 Specifies only during external clock input.
∗5 Specifies only during external event count input.
– 12 –
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Electrical Characteristics

DC characteristics (Ta = –20 to +75°C, Vss = 0V reference)

Item Symbol Pins Conditions Min. Typ. Max. Unit

PA, PB, PC0 to PC5, 4.0 V
VDD = 4.5V, IOH = –0.5mA
High level output PD, PE0 to PE1,
VOH
voltage PE4 to PE6, PG, R,
VDD = 4.5V, IOH = –1.2mA 3.5 V
G, B
PA to PD, PE0 to PE1, VDD = 4.5V, IOL = 1.8mA 0.4 V
PE4 to PE6, PF0 to
PF3, PG, R, G, B VDD = 4.5V, IOL = 3.6mA 0.6 V
Low level output
VOL PC6, PC7, PD, PF VDD = 4.5V, IOL = 12.0mA 1.5 V
voltage
PF4 to PF7 VDD = 4.5V, IOL = 3.0mA 0.4 V
(SCL0, SCL1,
SDA0, SDA1) VDD = 4.5V, IOL = 4.0mA 0.6 V
IIHE VDD = 5.5V, VIH = 5.5V 0.5 40 µA
EXTAL
IILE VDD = 5.5V, VIL = 0.4V –0.5 –40 µA
Input current IIHT VDD = 5.5V, VIH = 5.5V 0.1 10 µA
TEX
IILT –0.1 –10 µA
VDD = 5.5V, VIL = 0.4V
IILR RST∗1 –1.5 –400 µA
PA to PE, PG, R, VDD = 5.5V,
I/O leakage current IIZ ±10 µA
G, B, RST∗1 VI = 0, 5.5V
Open drain I/O PC6, PC7, PF0 to PF3 VDD = 5.5V, VOH = 12.0V 50 µA
leakage current ILOH
(in N-ch Tr off state) PF4 to PF7 VDD = 5.5V, VOH = 5.5V 10 µA
I2C bus switch VDD = 4.5V
SCL0: SCL1
connection impedance RBS VSCL0 = VSCL1 = 2.25V 120 Ω
SDA0: SDA1
(in output Tr off state) VSDA0 = VSDA1 = 2.25V
1/2 frequency dividing mode
IDD1 VDD = 5.5V, 18 28 mA
16MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3.3V,
IDD2 32MHz crystal oscillation 30 80 µA
(C1 = C2 = 47pF)
Sleep mode
Supply current∗2 IDDS1 VDD VDD = 5.5V, 1.2 2.1 mA
16MHz crystal oscillation
(C1 = C2 = 15pF)
VDD = 3.3V,
IDDS2 32MHz crystal oscillation 12 35 µA
(C1 = C2 = 47pF)
Stop mode∗3
VDD = 5.5V,
IDDS3 — — — µA
termination of 16MHz
and 32MHz oscillation

– 13 –
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Item Symbol Pins Conditions Min. Typ. Max. Unit

PA to PD, PE0 to PE3, Clock 1 MHz
Input capacitance R, G, B, PF4 to PF7, 0V other than the 10 20 pF
CIN
PG3 to PG7, EXTAL, measured pins
TEX, EXLC, RST
∗1 For RST pin, specifies the input current when pull-up resistance is selected, and specifies the leakage
current when non-resistor is selected.
∗2 When all output pins are left open. Specifies only when the OSD oscillation is halted.
∗3 This device does not enter the stop mode.

– 14 –
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

AC Characteristics

(1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pins Conditions Min. Typ. Max Unit
XTAL
System clock frequency fC Fig. 1, Fig.2 8 16 MHz
EXTAL
tXL, Fig. 1, Fig.2
System clock input pulse width EXTAL 28 ns
tXH External clock drive
System clock input rise and fall tCR, Fig. 1, Fig.2
EXTAL 200 ns
times tCF External clock drive
Event count input clock pulse tEH, EC Fig. 3 4tsys∗1 ns
width tEL
Event count input clock rise tER, EC Fig. 3 20 ms
and fall times tEF
VDD = 2.7 to 5.5 V
TEX
System clock frequency fC Fig. 2 (32kHz clock 32.768 kHz
TX
applied conditions)
Event count input clock input tTL, TEX Fig. 3 10 µs
pulse width tTH
Event count input clock rise tTR, TEX Fig. 3 ms
20
and fall times tTF
∗1 Indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits
(CPU clock selection).
tsys (ns) = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)

Fig. 1. Clock timing 1/fc

VDD – 0.4V
EXTAL
0.4V

tXH tCF tXL tCR

AAAAAAAAA AAAA
Fig.2. Clock applied conditions

AAAAA AAAA AAAA

Crystal oscillation 32kHz clock applied condition
Ceramic oscillation External clock Crystal oscillation

AAAAAAAAA AAAA
C1
EXTAL XTAL

C2
EXTAL

74HC04
XTAL

C1
TEX TX

C2

Fig. 3. Event count clock timing

TEX 0.8VDD
EC
0.2VDD

tEH tEF tEL tER

tTH tTF tTL tTR

– 15 –
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

(2) Serial transfer (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max. Unit

Input mode 1000 ns
SCK cycle time tKCY SCK
Output mode 8000/fc ns

SCK High and Low level tKH SCK input mode 400 ns
SCK
width tKL SCK output mode 4000/fc – 50 ns

SI input setup time SCK input mode 100 ns

(for SCK ↑)
tSIK SI
SCK output mode 200 ns

SI hold time SCK input mode 200 ns

(for SCK ↑)
tKSI SI
SCK output mode 100 ns
SCK input mode 200 ns
SCK ↓ → SO delay time tKSO SO
SCK output mode 100 ns

Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.

Fig. 4. Serial transfer timing

tKCY

tKL tKH

0.8VDD
SCK
0.2VDD

tSIK tKSI

0.8VDD
SI Input data

0.2VDD

tKSO

0.8VDD
SO Output data
0.2VDD

– 16 –
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

(3) A/D converter (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Typ. Max. Unit

Resolution 8 Bits
Linearity error ±3 LSB
Zero transition Ta = 25°C
VZT∗1 –10 10 70 mV
voltage VDD = 5.0V
Vss = 0V
Full-scale transition
VFT∗2 4910 4970 5030 mV
voltage
Conversion time tCONV 26/fADC∗3 µs
Sampling time tSAMP 6/fADC∗3 µs
Analog input voltage VIAN AN0 to AN5 0 VDD V

Fig. 5. Definitions for A/D converter terms

FFh
FEh
Digital conversion value

∗1 VZT: Value at which the digital conversion value changes

from 00h to 01h and vice versa.
∗2 VFT: Value at which the digital conversion value changes
from FEh to FFh and vice versa.
∗3 fADC indicates the below values due to the contents of bit
Linearity error 6 (CKS) of the A/D control register (ADC: 00F6h):

01h
00h
fADC = fc (CKS = “0”), fc/2 (CKS = “1”)
VZT VFT
Analog input

– 17 –
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max. Unit

INT0
External interruption High, tIH 1 µs
INT1
Low level width tIL
INT2
Reset input Low level width tRSL RST 32/fc µs

Fig. 6. Interruption input timing

tIH tIL

INT0
INT1 0.8VDD
INT2
(falling edge) 0.2VDD

Fig. 7. RST input timing

tRSL

RST
0.2VDD

– 18 –
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

(5) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max. Unit

SCL clock frequency fSLC SCL 0 100 kHz
Bus-free time before starting transfer tBUF SDA, SCL 4.7 µs
Hold time for starting transfer tHD; STA SDA, SCL 4.0 µs
Clock Low level width tLOW SCL 4.7 µs
Clock High level width tHIGH SCL 4.0 µs
Setup time for repeated transfers tSU; STA SDA, SCL 4.7 µs
Data hold time tHD; DAT SDA, SCL 0∗1 µs
Data setup time tSU; DAT SDA, SCL 250 ns
SDA, SCL rise time tR SDA, SCL 1 µs
SDA, SCL fall time tF SDA, SCL 300 ns
Setup time for transfer completion tSU; STO SDA, SCL 4.7 µs
∗1 The data hold time should be 300ns or more because the SCL rise time (300ns Max.) is not included in it.

Fig. 8. I2C bus transfer timing

SDA
tBUF
tR tF tHD; STA

SCL
tHD; STA
tSU; STA tSU; STO
P S tLOW tHD; DAT tHIGH tSU; DAT St P

Fig. 9. I2C bus device recommended circuit

I2C bus I2C bus

device device

RS RS RS R S RP RP

SDA0
(or SDA1)
SCL0
(or SCL1)

• A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the
spike noise caused by CRT flashover.

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 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

(6) OSD timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)

Item Symbol Pins Conditions Min. Max Unit

OSD clock frequency EXLC

fOSC Fig. 11 4 30.4 MHz
XLC

HSYNC pulse width tHWD HSYNC Fig. 10 2 µs

VSYNC pulse width tVWD VSYNC Fig. 10 1 H∗2
HSYNC afterwrite rise and fall
tHCG HSYNC Fig. 10 200 ns
times
VSYNC beforewrite rise and fall
tVCG VSYNC Fig. 10 1.0 µs
times

∗1 The maximum value of fosc is specified with the following equation.

fosc [max] ≤ fc × 1.9
∗2 H indicates 1HSYNC period.

Fig. 10. OSD timing

tHCG
tHWD

HSYNC 0.8VDD
For OSD I/O polarity register
(OPOL: 01FEh)
bit 7 at “0” 0.2VDD

tVCG
tVWD

VSYNC 0.8VDD
For OSD I/O polarity register
(OPOL: 01FEh)
bit 6 at “0” 0.2VDD

Fig. 11. LC oscillation circuit connection

EXLC XLC

R∗1
L

C1 C2

∗1 The series resistor for XLC (R = 1kΩ or less) can reduce the frequency of occurrence of the undesired
radiation.

– 20 –
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Appendix

Fig. 12. Recommended oscillation circuit

AAAA AAAA AAAAA

(i) Main clock (ii) Main clock (iii) Sub clock

AAAA AAAA
AAAA AAAA
EXTAL AAAAA
AAAAA XTAL EXTAL XTAL TEX TX

AA
Rd Rd Rd

A
C1 C2 C1 C2

A
C1 C2

Manufacture Model fc (MHz) C1 (pF) C2 (pF) Rd (Ω) Circuit example

CSA10.0MTZ 10.0
30 30
CSA12.0MTZ 12.0 (i)
CSA16.00MXZ040 16.0 5 5
MURATA MFG 0 ∗1
CO., LTD. CST10.0MTW∗ 10.0
30 30
CST12.0MTW∗ 12.0 (ii)
CST16.00MXW0C1∗ 16.0 5 5
8.0 18 18
RIVER
ELETEC CO., HC-49/U03 12.0 12 12 330 ∗1
LTD.
16.0 10 10
(i)
8.0 10 10
HC-49/U (-S) 12.0 5 5 0 ∗1
KINSEKI LTD.
16.0 OPEN OPEN
P3 32.768kHz 30 33 120k (iii)
∗ Models with an astarisk (∗) have the built-in ground capacitance (C1, C2).
∗1 The series resistor for XTAL (Rd = 500Ω or less) can reduce the effect of the noise caused by the
electrostatic discharge.

Mask Option Table

Item Content
Reset pin pull-up resistor Non-existent Existent

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 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Fig. 13. Characteristic curves

IDD vs. VDD IDD vs. fc

(fc = 16MHz, Ta = 25°C, Typical) (VDD = 5V, Ta = 25°C, Typical)
100

1/2 dividing mode

10 1/4 dividing mode
15 1/2 dividing mode

1/16 dividing mode

IDD – Supply current [mA]

IDD – Supply current [mA]

Sleep mode
1
10

1/4 dividing mode

0.1
32kHz operation mode 5

32kHz sleep mode

1/16 dividing mode

0.01
Sleep mode
0
1 2 3 4 5 6 7 0 5 10 15
VDD – Supply voltage [V] Frequency [MHz]

Parameter curve for OSD oscillator L vs. C

(Analytically calculated value)
100

10
L – Inductance [µH]

16MHz
20MHz
1
24MHz
28MHz
30MHz

1
fOSC = C = C1//C2
2π √ LC
0.1

0.01
0 10 20 30 40 50 60 70 80 90 100
C1, C2 – Capacitance [pF]

– 22 –
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

Package Outline Unit: mm

64PIN SDIP (PLASTIC) 750mil

0.05
+ 0.1
0.25 –
+ 0.4
57.6 – 0.1

64 33

17.1 – 0.1
+ 0.3
0° to 15°

19.05
1 32
1.778

+ 0.4
4.75 – 0.1
0.5 MIN
3 MIN
0.5 ± 0.1

0.9 ± 0.15

PACKAGE STRUCTURE
MOLDING COMPOUND EPOXY / PHENOL RESIN

SONY CODE SDIP-64P-01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE SDIP064-P-0750-A LEAD MATERIAL 42 ALLOY

JEDEC CODE PACKAGE WEIGHT 8.6g

64PIN QFP(PLASTIC)

23.9 ± 0.4
+ 0.4 + 0.1
20.0 – 0.1 0.15 – 0.05

51 33 0.15

52 32
17.9 ± 0.4
14.0 – 0.1
+ 0.4

16.3

64 20
+ 0.2
0.1 – 0.05

1
19
0.8 ± 0.2

+ 0.15 + 0.35
1.0 0.4 – 0.1 2.75 – 0.15

± 0.12 M

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE QFP–64P–L01 LEAD TREATMENT SOLDER/PALLADIUM

PLATING
EIAJ CODE ∗ QFP064–P–1420 LEAD MATERIAL COPPER /42 ALLOY

JEDEC CODE PACKAGE WEIGHT 1.5g

– 23 –
 CXP86212/86216, CXP86324/86332, CXP86440/86448/86460

64PIN LQFP (PLASTIC)

12.0 ± 0.2
∗ 10.0 ± 0.1

48 33

49 32

(11.0)
0.5 ± 0.2
A
64 17
(0.22)

1 16
+ 0.08 + 0.05
0.5
0.18 – 0.03 0.127 – 0.02
0.13 M + 0.2
1.5 – 0.1
0.1

0.1 ± 0.1
0.5 ± 0.2

0° to 10°

NOTE: Dimension “∗” does not include mold protrusion.

DETAIL A

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE LQFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM

PLATING
EIAJ CODE LQFP064-P-1010 LEAD MATERIAL 42/COPPER ALLOY

JEDEC CODE PACKAGE MASS 0.3g

– 24 –