Received: 19 May 2020 Revised: 2 September 2020 Accepted: 4 September 2020

DOI: 10.1002/cta.2879

RESEARCH ARTICLE

New simple transistor realizations of second- generation

voltage conveyor

Abdullah Yesil1 | Shahram Minaei2

1
Department of Electrical and Electronics
Engineering, Bandirma Onyedi Eylul
University, Balikesir, Turkey
2
Department of Electronics and
Communications Engineering, Dogus
University, Istanbul, Turkey
Correspondence
Abdullah Yesil, Department of Electrical
and Electronics Engineering, Bandirma
Onyedi Eylul University, Balikesir 10200,
Turkey.
Email: ayesil@bandirma.edu.tr
Summary
In this paper, two new complementary metal oxide semiconductor (CMOS)
realizations for second-generation voltage conveyor (VCII) are presented. The
first proposed VCII has a very simple structure employing only six transistors.
The second proposed VCII employs 11 transistors, and none of the transistors
at both proposed circuits suffer from the body effect. Small-signal analysis, par-
asitic elements, and input-referred noise of the proposed VCIIs are given.
Moreover, a new active element called voltage controlled second-generation
voltage conveyor (VC-VCII) is proposed as dual element of current controlled
second-generation current conveyor (CCCII) active element. Its parasitic resis-
tance at the Y terminal can be controlled electronically. Two presented CMOS
structures of VCII are worked as VC-VCII with slight modification. Proposed
circuits are simulated in Cadence Analog environment using TSMC 0.18-μm
process parameters with ±0.9-V supply voltages. Both CMOS structures occupy
a small chip area of 276.8 and 271 μm2, respectively. The bandwidth of the cur-
rent follower stage of the proposed VCIIs is found as 794 MHz, whereas the
bandwidth of the voltage follower stage for the first and second proposed VCIIs
is found as 2.57 and 1.92 GHz, respectively. As an application example,
voltage-mode first-order low-pass filter has been given with its tunable gain by
using VC-VCII.

KEYWORDS
active element, CMOS realization, VCII, VC-VCII

1 | INTRODUCTION

Current conveyor (CC), which is frequently used among active elements, has an important place in analog circuit
designs. There are three different generations of CC, namely, first-generation CC (CCI),1 second-generation CC (CCII),2
and third generation CC (CCIII).3 CCs consist of voltage follower at first stage and current follower (CF) structure at
the second stage. The type of CC is determined by Y terminal. For example, if no current flows through Y terminal, this
type is called the second-generation CC. CCs have high bandwidths, flexible terminal connections, wide dynamic range,
and high linearity. Nonetheless, a drawback of CC compared with operational amplifier (OPAMP) is its unity gain in
both voltage and current forms. Therefore, some of the voltage-mode transfer functions such as voltage amplification
require more CCs with respect to OPAMP-based ones. However, researchers have focused on different active elements
due to the disadvantages of OPAMP such as limited gain-bandwidth product. Voltage conveyor,4 which was introduced
as a concept in 1981, was presented in 2001 by eliminating the confusion.5 Voltage conveyor types offering different

Int J Circ Theor Appl. 2020;1–16. wileyonlinelibrary.com/journal/cta © 2020 John Wiley & Sons, Ltd. 1
2 YESIL AND MINAEI

current–voltage relationships4–6 are presented as first-generation voltage conveyor (VCI), second-generation voltage
conveyor (VCII), and third-generation voltage conveyor (VCIII). For instance, the terminal connections of the VCII can
be identified as follows: The current at terminal Y is transferred to the terminal X via a CF circuit. Then, the voltage at
terminal X is transferred to the Z terminal through a voltage follower with an impedance connected to its input. Unlike
the CCs, the input stage of a VCII consists of a CF, and the output stage consists of a voltage follower. Thus, much
fewer active elements can be used when performing the aforementioned voltage-mode signal processing operations.
For example, only one VCII is required to perform a voltage amplifier, while two CCIIs are required to perform the
same operation. In addition, a voltage amplifier can be obtained with a single OPAMP. Nevertheless, due to the
abovementioned disadvantages of the OPAMP, VCII seems to attract the attention of designers. The application areas
of VCII such as voltage integrator,7,8 transimpedance amplifier,9 first- and second-order filters,10–12 differential capaci-
tive sensor,13 inductor simulator,14 and full wave rectifier15 play an active role in the literature.
Considering complementary metal oxide semiconductor (CMOS) implementations of voltage conveyors such as cur-
rent differencing buffered amplifier (CDBA),16 differential current voltage conveyor (DCVC),17 and universal voltage
conveyor (UVC),18–21 some of their terminals may not be used in applications such as amplification, voltage differentia-
tion, current to voltage conversion, and voltage integration. Therefore, unutilized terminals cause extra power con-
sumption and chip area. Hence, there is a need for simple CMOS implementations by considering VCII as an
independent element. New CMOS realization of VCII with high performance is presented. Recently, a new CMOS reali-
zation of VCII with high performance is proposed employing 11 transistors and seven ideal current sources.7 CMOS
implementation of flipped voltage follower (FVF)-based VCII consists of 16 transistors, and seven ideal current sources
have been proposed in Barile et al.8 Barile et al9 present rail-to-rail VCII employing 29 transistors, five ideal current
sources, and two biasing voltage sources excepting DC supply voltages. As for another CMOS realization of VCII, it
includes 10 transistors and four ideal current sources.10 CMOS realization of class AB VCII is made up of 12 transistors
and four ideal current sources.22 However, the main disadvantage of the circuits reported in previous studies7–10,22 is
that they have too many ideal current sources that should be implemented with many transistors. It should be noted
that the ideal current sources used to set the direct current (DC) points in the circuits must either be provided with at
least one transistor and a biasing voltage source for each current source or implemented with a single current source
and a great number of copying transistors. In both cases, several transistors and/or biasing voltages will be required in
addition to the existing transistors. Thus, these extra transistors increase power consumption and the chip area of the
circuit.
In this paper, two different CMOS implementations of VCII are presented. The first proposed CMOS implementa-
tion of VCII consists of only six transistors. The second proposed VCII circuit includes only 11 transistors. In both cir-
cuits, ideal current sources are not used; nevertheless, only one biasing voltage source is employed. Among the
advantages of the second circuit, the offset voltage at the Z terminal is almost zero, while at the Z terminal of the first
circuit, there is an offset voltage equal to the VGS voltage of MOS transistor. In addition, the output resistance of the
voltage follower in the second proposed circuit is less than the first circuit one. Transfer functions of both circuits have
been obtained, and parasitic resistances of the ports are found. Moreover, the input referred noise (IRN) equations of
the ports in both circuits are extracted.
Furthermore, a new active element called voltage controlled second-generation voltage conveyor (VC-VCII) is pro-
posed by using the parasitic resistance appearing in the Y terminal of VCII. VC-VCII is proposed as dual element of cur-
rent controlled second-generation current conveyor (CCCII) active element.23 Given the presented CMOS structures of
VCII, both circuits can be operated as VC-VCII with minor modification.
In order to indicate performance of all circuit, their layouts are drawn, and DC, alternating current (AC), and tem-
perature analyses of the circuits have been given by using post layout results. Changing the dimensions of critical tran-
sistors, its effects on the performance of the circuit have been studied in detail. In addition, a voltage mode first-order
low-pass filter circuit is presented as an application example.

2 | C M O S R E A LI Z A T I O N OF VC I I

VCII is a useful and functionality active element in voltage-mode applications such as voltage amplifier, voltage integra-
tor, voltage differentiation, and I–V converter.7 Compared with CCII, VCII has lower power consumption and an occu-
pied layout area. The electrical symbol and the block scheme with a parasitic impedance of VCII are given in
Figure 1A,B, respectively. The structure of VCII contains a CF and a voltage follower.
YESIL AND MINAEI 3

F I G U R E 1 (A) The schematic

diagram of VCII and (B) its schematic
with parasitic resistance

The first stage of VCII, which is a CF, has ideally zero input impedance (at port Y) and infinity output impedance
(at port X), while the second stage of VCII, which is a voltage follower, has ideal zero output impedance (at port Z).
The nonideal VCII with parasitic impedances can be modeled at low frequencies by the following matrix:
2 3 2 32 3
IX 1=r X β 0 VX
6 7 6 76 7
4VY 5 = 4 0 r Y 0 54 I Y 5: ð1Þ
VZ α 0 rZ IZ

In 1, rY, rX, and rZ are defined as input impedance at port Y, output impedance at port X, and output impedance at port
Z, respectively. These parasitic impedances take place at ports Y, X, and Z due to transconductance gains and output
resistance of transistors. Besides, α and β are voltage and current transfer ratios of the VCII (ideally equal to unity),
respectively. Note that all currents flow into the VCII. CMOS realization and AC small-signal equivalent circuit of the
first proposed VCII are shown in Figure 2A,B, respectively. It is composed of only six transistors without utilizing any
current source. In addition, it can be observed from Figure 2 that there is no body effect of transistors, and thus, the
VCII can be operated with low DC supply voltages. Stage of CF is composed of M1–M4 transistors24 whereas voltage fol-
lower stage, which is called as source follower, is made up of M5–M6 transistors.
Analyzing AC small-signal equivalent circuit of the first proposed circuit given in Figure 2B, the current gain of the
CF is obtained as follows:

r01 r03 ðgm2 + gm4 Þ g + gm4

β= ≈ m2 : ð2Þ
r01 r03 ðgm1 + gm3 Þ + r01 + r03 gm1 + gm3

Assuming that gm1 = gm2 and gm3 = gm4, the current gain is arranged as β = 1. The current gain of VCII can be also
tuned by transconductance gains of the related transistors differently from unity gain. Similarly, a gain of voltage fol-
lower (α) can be calculated as follows:

F I G U R E 2 (A) The first

CMOS realization of VCII and
(B) its AC small-signal
equivalent circuit
4 YESIL AND MINAEI

gm6 ðr 06 jjr 05 Þ
α= : ð3Þ
gm6 ðr 06 jjr 05 Þ + 1

Assuming that generally gmro > > 1, gain of voltage follower is found as unity. The input parasitic resistance at port
Y of VCII and the output parasitic resistance at port X and Z of VCII can be obtained as follows:
 
1 1
rY = k kr 01 kr 03 ,
gm1 gm3
ð4Þ
1 1
rY ≈   k  
μp COX WL 1 ðV DD −V Y − jV TH jÞ μn COX WL 3 ðV Y −V SS − V TH Þ

r X = r 02 jjr 04 , ð5Þ

1
rZ = kr 05 jjr 06 : ð6Þ
gm6

It is clear from Equation 4 that input parasitic resistance rY is reduced through DC supply voltages (VDD, VSS). On the
other hand, input parasitic resistance can be adjusted by DC supply voltages (VDD, VSS). This property will be men-
tioned in the next section. In addition, the parasitic resistance of the X terminal can be increased using cascode stage.
On the other side, there is offset voltage between X and Z terminals of VCII because of DC voltage between gate to
source terminals of M6 transistor. The offset voltage can be minimized by increasing the width and length of the M6
transistor.
In order to investigate the noise performance of the proposed VCII, IRN equations belonging to Y and X terminals
are calculated. A literature survey shows IRN or output noise equations for the terminals of the VCII active element
have not been obtained yet. By extracting IRN equations, CMOS realization of VCII with low IRN can be designed.
Here, IRN is preferred instead of output noise so that it can be fairly compared with the CMOS realization of other
active elements.25
Figure 3 depicts a noise equivalent circuit including thermal noise of each transistor. Flicker noise of a transistor
can be ignored due to the working frequency of the VCII. Thermal noise, which represents with the parallel current
source, is defined as follows.25

  4kTγ  2 
I2n = 4kTγgm A2 =Hz , v2n = V =Hz , ð7Þ
gm

where k and T are Boltzmann constant and the absolute temperature, respectively. The coefficient γ is derived to be
equal to 2/3 for long-channel transistors and may need to be replaced by a larger value for submicron MOSFETs.5 As a

F I G U R E 3 Noise
equivalent circuit of the first
proposed VCII
YESIL AND MINAEI 5

rule of thumb, we assume γ ≈ 1. Assuming that gmro > > 1, IRN equations that belong to Y and X terminals are found
as
!
 ðgm1 + gm3 Þ2
I 2n,Y ffi 4kTγ gm1 + gm3 + , ð8Þ
ðgm2 + gm4 Þ

 
 ffi 4kTγ g
V 2n,in_X 1 + m5 : ð9Þ
gm6 gm6

Assuming that gm1 = gm2 and gm3 = gm4, it can be seen from Equation 8 that IRN of Y terminal decreases if trans-
conductance gains of the M1–M4 transistors are reduced. The IRN of X terminal can be reduced by increasing trans-
conductance gain of M6 transistor or by decreasing transconductance gain of M5 transistor. Furthermore, parasitic
output resistance and offset voltage of Z terminal decrease if transconductance gain of M6 transistor enhances. Consid-
ering Equations 4, 5, 6, 8, and 9 and assuming that gm1 = gm2 and gm3 = gm4, Table 1 is given, which summarizes main
parameters of the CMOS realization of the first proposed VCII. According to the application areas, width and length of
the transistors at CMOS realization of VCII can be selected properly for optimum conditions.
The CMOS realization and AC small-signal equivalent circuit of the second proposed VCII are given in Figure 4,
respectively. It is made up of only 11 transistors without using any current source. Further, it is clearly seen from
Figure 4 that there is no body effect of transistors, and hence, the VCII can be worked with low DC supply voltages.
The first stage called CF for both proposed VCIIs is same, while their second stages, which are voltage followers, have
different structures.
In the second proposed circuit, a simple differential pair is utilized as a voltage follower stage to provide low offset
voltage at port Z. Considering AC small-signal equivalent circuit of the second proposed circuit, the voltage gain of volt-
age follower (assuming fully matched M5, M6 and M7, M8) is found as follows:

TABLE 1 Transconductance gains and biasing current effects in the performance of the first proposed VCII

To decrease rY To increase rX To decrease rZ To decrease IRN of Y To decrease IRN of X

M1 gm1 * - - gm1 + -
M2 - IDS2 + - gm2 + -
M3 gm3 * - - gm3 + -
M4 - IDS4 + - gm4 + -
M5 - - IDS5 * - gm5 +
M6 - - gm6 * - gm6 *

Abbreviations: IRN, input referred noise; VCII, second-generation voltage conveyor.

FIGURE 4 (A) The second CMOS realization of VCII and (B) its AC small-signal equivalent circuit
6 YESIL AND MINAEI

gm5 gm9 r o5 r o7 r o911 ðr o10 ðgm5 r o5 + 1Þð2gm7 r o7 + 1Þ + r o5 ðgm7 r o7 + 1Þ + r o7 Þ

α= , ð10Þ
r o10 ðgm5 r o5 + 1Þðr o5 ð2gm7 r o7 ðgm5 gm9 r o7 r o911 + 1Þ + gm5 gm9 r o7 r o911 + 2Þ + 2r o7 ðgm7 r o7 + 1ÞÞ…
+ r 2o5 ðgm7 r o7 ðgm5 gm9 r o7 r o911 + 1Þ + 1Þ + r o5 r o7 ðgm7 r o7 + 2Þ + r 2o7

where ro911 = ro9//ro11.The following term is obtained with the condition of gmro > > 1:

1
α = 1− : ð11Þ
2gm7 r o7 + 1

It is clear from Equation 11 that voltage gain of voltage follower can be calculated as unity approximately. The current
gain, input, and output impedance of first stage (CF) are previously given in Equations 2, 4, and 5, respectively. The
output parasitic resistance of voltage follower of the second circuit given in Figure 4 is calculated with the condition of
gmro > > 1 as

1
rZ = : ð12Þ
gm5 gm9 ðr o5 ==r o7 Þ

It is observed from Equation 12 that output parasitic resistance of terminal Z diminishes if transconductance gain of M5
and M9 transistors increases. Comparing with the output resistance of voltage follower stage at both VCII, output resis-
tance at Z terminal of second proposed VCII is less than first one by factor of gmro.
Figure 5 shows the noise equivalent circuit of the second proposed VCII. In order to simplify the result, it is
assumed that M5 = M6, M7 = M8, and gmro > > 1. Thus, the noise equation at X terminal is calculated as follows:
  
 4kTγ 1 gm10 gm11 1
V 2n,in_X ffi 2 2gm6 + 2gm8 + 2 + + , ð13Þ
gm6 r o68 4g2m8 g2m9 gm9

where ro68 = ro6//ro8. It can be seen from Equation 13 that IRN voltage at X terminal can be reduced by increasing
transconductance gains of M5 = M6 and M9 transistors and/or by decreasing transconductance gains of M10 and M11
transistors. Considering Equations 4, 5, 8, 12, and 13 and assuming that gm1 = gm2 and gm3 = gm4, the main parameters
of the second proposed VCII are given in Table 2.

3 | V OLTAGE C ON T R OLLE D SEC O ND- GE NE R A T I O N V O L T A GE CO NV E YO R

As dual element of CCCII, VC-VCII can be considered as a VCII with a controllable resistance at its Y terminal. It can
be observed from Equation 4 that the parasitic resistance in the Y terminal of VCII can be electronically adjusted if the

F I G U R E 5 Noise
equivalent circuit of the second
proposed VCII
YESIL AND MINAEI 7

TABLE 2 Transconductance gains and biasing current effects in the performance of the second proposed VCII

To decrease rY To increase rX To decrease rZ To decrease IRN of Y To decrease IRN of X

M1 gm1 * - - gm1 + -
M2 - IDS2 + - gm2 + -
M3 gm3 * - - gm3 + -
M4 - IDS4 + - gm4 + -
Matched M5 and M6 - - gm5 = gm6 * - gm5 = gm6 *
M9 - - gm9 * - gm9 *
M10 - - - - gm10 +
M11 - - - - gm11 +

Abbreviations: IRN, input referred noise; VCII, second-generation voltage conveyor.

CF circuit is controlled by VA and −VA instead of constant DC voltages VDD and VSS. Equation 4 of parasitic resistance
in the Y terminal of the CF can be arranged as follows:

1 1
rY ffi W  k W  : ð14Þ
μp C OX L 1 ðV A −V Y − jV TH jÞ μn COX L 3
ðV Y + V A −V TH Þ

This new active element is referred to as VC-VCII, and the CMOS realization of VC-VCII, which is derived version of
the first proposed VCII, is shown in Figure 6A. Similarly, another CMOS realization of VC-VCII, which is reproduced a
version of the second proposed VCII, is illustrated in Figure 6B. Note that in practice, VA voltage can be buffered before
applying to the circuit. Thus, the voltage source VA is not affected by the internal resistance of the circuit and provides
perfect tuning.

4 | SIMULATION RESULTS

In order to illustrate the performances of first and second proposed VCII/VC-VCII circuits, their layouts are laid out
using the Cadence Analog environment using TSMC 0.18-μm process parameters. Their layouts are given in Figure 7.
The first and second proposed VCIIs occupy layout areas of 19 × 14.57 and 18.3 × 14.81 μm, respectively. The DC sup-
ply voltages and biasing voltage (VB) are chosen as ±0.9 and 0.2 V, respectively.
Unless specified for VC-VCII, VA is equal to 0.9 V; otherwise, VA is connected to VDD while −VA is connected to VSS.
The bulk terminals of PMOS transistors are connected to source terminals of the relevant transistors, while the bulk ter-
minals of NMOS transistors are connected to the most negative DC supply voltage. The power dissipations of the first
and second proposed VCII are calculated as 664 and 622 μW, respectively, whereas aspect ratios of transistors in CMOS
realization of them are given in Table 3. Note that the CF stage is the same in the first and second proposed VCIIs. As
expected, the parasitic resistance of Z terminal in the second proposed VCII is much lower than the one of the first

F I G U R E 6 The two different CMOS

realizations of VC-VCII derived from
(A) the first and (B) the second
proposed VCII
8 YESIL AND MINAEI

F I G U R E 7 Layout of
(A) first proposed VCII and
(B) second proposed VCII
[Colour figure can be viewed at
wileyonlinelibrary.com]

TABLE 3 Aspect ratios of transistors in both VCIIs

First proposed VCII Second proposed VCII

Transistors W/L Transistors W/L

M1, M2 16/0.72 μm M1, M2 16/0.72 μm
M3, M4 4/0.72 μm M3, M4 4/0.72 μm
M5 50/0.72 μm M5, M6, M9–M11 10/0.36 μm
M6 20/0.18 μm M7, M8 2.5/0.36 μm

Abbreviation: VCII, second-generation voltage conveyor.

proposed VCII. It can be seen from Equations 4 and 5 that the ratio of (W/L)M1–M4 can be increased in order to reduce
the parasitic resistance of Y terminal, whereas the lengths of M2 and M4 transistors can be increased to enhance the par-
asitic resistance of X terminal. Also, the parasitic resistance of the Z terminal of the first and second proposed VCII can
be diminished by increasing transconductance gain of M6 and M5, M9, respectively.
Moreover, some important parameters of transistors are shown in Table 4. Considering the values of gm and rO in
Table 4, it is observed that the gmro > > 1 condition is easily provided. Figure 8 depicts DC transfer characteristic of CF,
which is used at first and second proposed VCIIs. The DC current swing of the CF is between −1065 and 1065 μA with
less than ±10% deviation. For the voltage follower stage of the first proposed VCII, its DC voltage swing is given in
Figure 9A. The Vz voltage changes between −900 and 175 mV with less than ±10% deviation from its ideal value.

TABLE 4 Small-signal parameters of transistors in both VCII

First proposed VCII Second proposed VCII

gm (μA/V) ro (kΩ) Cgs (fF) gm (μA/V) ro (kΩ) Cgs (fF)
M1 543.8 152.7 76 543.8 152.7 76
M2 543.8 153.4 76 543.8 153.4 76
M3 537.6 140.8 19.3 537.6 140.8 19.3
M4 538.4 138.9 19.3 538.4 138.9 19.3
M5 1428 32.5 18 258.6 416.7 20
M6 909.7 61 220.7 258.9 404.9 20
M7 249.9 282.5 5.3
M8 251.2 307.7 5.3
M9 683.3 184.2 18.8
M10 378.8 96.8 22.2
M11 410.9 205.8 22.2

Abbreviation: VCII, second-generation voltage conveyor.

YESIL AND MINAEI 9

FIGURE 8 DC current swing of the current follower stage in both VCIIs

Similarly, the DC voltage swing of the voltage follower used in the second proposed VCII is shown in Figure 9B, which
exhibit a perfect performance. It can be observed from Figure 8 and Figure 9A that the CF has a wide DC current swing
while voltage follower stages of first proposed VCII have a limited DC voltage swing. DC voltage swing of first proposed
VCII can be increased by changing ratio (W/L) of M5 transistor. For the first proposed VCII, the offset voltage on port
Z is measured as 612 mV due to the gate to source voltage of M6 transistors. The offset voltage on port Z can be
decreased by increasing the ratio of (W/L)M6. Regarding with the second proposed VCII, the offset voltage on port Z is
calculated as only −0.9 mV. It should be noted that compared to the first circuit, offset voltage of the voltage follower is
considerably reduced in the second circuit.
The frequency responses of CF and voltage follower stages are illustrated in Figure 10 for both proposed circuits.
From AC transfer characteristic, current gain β for both circuits is found to be 0.988. The voltage gain α of first and sec-
ond proposed circuits is found as 0.968 and 1, respectively. Further, current transfer bandwidth of 794 MHz and voltage
transfer bandwidth of 2.57 GHz are calculated for the first proposed VCII, whereas voltage transfer bandwidth of

F I G U R E 9 DC voltage swing of
(A) first proposed VCII and (B) second
proposed VCII

F I G U R E 1 0 The AC transfer characteristics of current follower and

voltage follower in both VCII
10 YESIL AND MINAEI

1.92 GHz is found the for second proposed VCII. Figure 11 depicts change of the parasitic impedances with frequency
for both proposed VCIIs. From post-layout simulation results, parasitic resistances/capacitances of Y, X, and Z terminal
of first proposed circuit are calculated as 930 Ω/0.21 pF, 74.28 kΩ/38 fF, and 705 Ω/92 fF, while parasitic
resistance/inductance of Z terminal of second proposed circuit is found as 35 Ω/0.23 μH.
The noise performances of both proposed VCIIs are examined; IRN current at Y terminal and IRN voltages at
X terminal are given in Figure 12. The summaries of some important parameters of both proposed VCII and compari-
son with other works are given in Table 5. Table 5 shows that the proposed circuits have advantages such as wider
bandwidth and lower number of transistors with respect to the other previously published circuits.
As discussed in Section 3, the CMOS realizations of VC-VCII given in Figure 6A,B can be obtained with the slight
modifications of the CMOS realization VCII given in Figures 2 and 4, respectively. Considering Equation 14 and
Figure 6A, the parasitic resistances at the Y terminal can be set by the VA voltage source. However, the X terminal resis-
tance is also distributed by changing VA since the DC current flowing through transistors M2 and M4 is changed.
Figure 13A shows the change in parasitic resistance value with VA voltage in the Y terminal. As can be seen from
Figure 13A, the value of rY is electronically changed from 4 kΩ to 500 Ω.
As shown in Figure 13A, the parasitic resistances in the Y and X terminals decrease as the value of VA increases.
The effects of the VA on the power consumption and IRN current at Y terminal of the first VC-VCII structure are dem-
onstrated in Figure 13B. Similarly, the power consumption of the circuit in Figure 13B increases as the current passing
through the transistors increases as the value of VA increases. In view of this phenomenon, the IRN current at
Y terminal increases as illustrated from Figure 13B, when the transconductance gains of the transistors increase with
increasing VA voltage. Also, it can be easily seen from Figure 13C that bandwidth of current gain increases as the value
of VA increases. The designer should be careful in changing range of the VA, to ensure that the transistors work in satu-
ration region.
In order to examine the variation of the voltage gain and parasitic resistance of the voltage follower stage of both cir-
cuits with biasing voltage VB, the simulation results of these parameters are given in Figure 14. The output resistance of

F I G U R E 1 1 Parasitic impedances
of (A) first proposed VCII and
(B) second proposed VCII

FIGURE 12 Simulated input referred noise current and voltage

versus frequency and their values at 10 MHz
YESIL AND MINAEI 11

TABLE 5 Comparison results of important parameters of both VCII

Parameters Values

First Second
proposed proposed
Ref. circuit circuit Safari et al7 Barile et al8 Barile et al9 Safari et al10
VDD = −VSS 0.9 V 0.9 V 1.65 V 1.65 V 0.9 V 1.65 V
Numbers of 6 transistors 11 transistors 11 transistors, 7 16 transistors, 7 29 transistors, 5 10 transistors, 4
transistor and ideal current ideal current ideal current ideal current
current sources sources sources sources sources
Power 664 μW 622 μW 330 μW 320 μW 120 μW 700 μW
consumption
Current gain, β 0.988 0.988 0.988 0.987 0.996 0.996
Voltage gain, α 0.968 1 0.997 0.992 0.973 0.995
DC linearity of −1065/1065 μA −1065/1065 μA NA NA −500 μA/500 μA NA
current gain
DC linearity of −900/175 mV −900/900 mV NA NA −900/900 mV NA
voltage gain
Bandwidth of 794 MHz 794 MHz 200 MHz 22.4 MHz 165 MHz 14.6 MHz
current gain
Bandwidth of 2.57 GHz 1.92 GHz 217 MHz 220 MHz 55 MHz (1 pF 340 MHz
voltage gain load at Z)
rY 930 Ω 930 Ω 6.7 Ω 2 mΩ 23 Ω 49 Ω
rX 74.28 kΩ 74.28 kΩ 1.2 MΩ 370 kΩ 522 kΩ 802 kΩ
rZ 705 Ω 35 Ω 0.7 Ω 2 mΩ 160 Ω 79 Ω
Offset current 0.43 μA 0.43 μA NA NA NA NA
Offset voltage 612 mV −0.9 mV NA NA NA NA
IRN current at Y 7.16 pA√Hz @ 7.16 pA√Hz @ NA NA NA NA
terminal 10 MHz 10 MHz
IRN voltage at X 4.53 nV√Hz @ 20.16 nV√Hz NA NA NA NA
terminal 10 MHz @ 10 MHz

Abbreviations: DC, direct curent; IRN, input referred noise; NA, not available; VCII, second-generation voltage conveyor.

the voltage follower increases with VB because the current flowing from M6 transistor for Figure 2 (from M11 transistor
for Figure 4) decreases as the biasing voltage increases.
The performance of the first proposed VCII with temperature is also tested. The temperature has been changed from
−40 C to 80 C. Figure 15A shows the variation of the parasitic resistances of the CF stage of first proposed VCII with
temperature. From Figure 15A it can be realized that while the value of the rY parasitic resistance increases with tem-
perature, the value of the rX parasitic resistance increases to a certain point with the temperature and then it decreases.
As seen in Figure 15B, by increasing the temperature, the power consumption increases, and the value of the rZ para-
sitic resistance decreases. In Figure 16, variations of IRN voltage and current of the first proposed VCII are given with
the change of temperature. It can be observed from Figure 16 that the IRN current decreases with increasing the tem-
perature while the IRN voltage takes the minimum values between 30 C and 50 C.
In this part, the variations of the important parameters of the VC-VCII given in Figure 6A have been examined by
changing the VA voltage source and transistor dimensions. Detailed change of rY, IRN current, and power consumption
are depicted in Figure 17, where VA voltage source varies between 0.6 and 0.9 V and different transistor sizes are
selected according to (W/L)M1,M2 = 4 × (W/L)M3,M4 condition to provide a balance between NMOS and PMOS transis-
tors. It should be noted that the channel length of all transistors was chosen as 0.72 μm so that the transistors have high
output resistance. As clearly seen in Figure 16A, the formula for rY given in Equation 14 is confirmed. Moreover, it is
clearly seen that the parasitic resistance, rY, in Y terminal varies electronically with the change of VA. It is also observed
12 YESIL AND MINAEI

FIGURE 13 The dependence of (A) ry

and rx, (B) power consumption, and IRN
current (C) bandwidth of current gain
versus VA biasing voltage for current
follower of VC-VCII given Figure 6A

FIGURE 14 The dependence of rZ

and voltage gain (α) of (A) first
proposed VCII given in Figure 2 and
(B) second proposed VCII given
Figure 4

F I G U R E 1 5 The variation of
(A) rY and rX versus temperature and
(B) rZ and power consumption versus
temperature for first proposed VCII

that parasitic resistance rY is reduced by increasing the channel widths of M1–M4 transistors. Figure 17B,C clearly
shows that the power consumption and IRN current will increase if we use higher values for VA voltage source and
channel widths of the related transistors. Considering in Figure 17A–C, an optimum solution should be selected
according to the application area when determining the performance parameters of VC-VCII. In summary, as VA
YESIL AND MINAEI 13

F I G U R E 1 6 Investigation of IRN voltage and current variations with

temperature for the first proposed VCII

F I G U R E 1 7 Dependence of
(A) rY, (B) power consumption, and
(C) IRN current with regard to VA
voltage source and channel widths of
relevant transistors

F I G U R E 1 8 Voltage mode first-order low-

pass filter based on (A) VCII10 and (B) VC-VCII
14 YESIL AND MINAEI

F I G U R E 1 9 (A) Gain and phase-

frequency responses of voltage mode
first-order low-pass filter;
(B) dependence of gain of LPF on VA
voltage sources for Figure 6A

voltage source and the channel widths of the related transistors increase, rY decreases and power consumption and IRN
current increase.
As an application example, voltage-mode first-order low-pass filter based on VCII and VC-VCII are given in
Figure 18A,B. It is clear from Figure 18 that a resistor is reduced in the VC-VCII-based low-pass filter when its parasitic
resistance is utilized.
Transfer functions of voltage-mode first-order low-pass filter based on VCII and VC-VCII are, respectively, found as
the following:

V LP R2 1
= −βα × , ð15Þ
V in R1 1 + sCR2

V LP R2 1
= −βα × : ð16Þ
V in r Y 1 + sCR2

As seen in Equation 16, when the value of the resistor rY is changed electronically by VA, the gain of the voltage-mode
first-order low-pass filter will be electronically altered.
If the CMOS realization of VC-VCII given in Figure 6A uses, the AC characteristics of first-order voltage mode low-
pass filter are given in Figure 19A for different VA voltage source. Passive element values are chosen as C = 3 pF and
R2 = 1.5 kΩ resulting in approximately fo = 35 MHz. This application circuit can be utilized in WLAN 802.11n stan-
dard.26 In addition, since the gain of the low-pass filter changes electronically, it can be operated as a variable gain
amplifier (VGA). It can be observed from Figure 19B that depending on the change in VA, the gain of the filter varies
from 0.4 to 1.5.

5 | C ON C L US I ON

In this paper, two simple CMOS realizations of VCII are presented. First one is made of only six transistors that occupy
layout area of 276.8 μm2, while the second one consists of 11 transistors that occupy layout area of 271 μm2. Both cir-
cuits have no body effect; therefore, they can be operated low DC supply voltages. Also, both circuits contain no ideal
current source. Furthermore, by using proposed CMOS implementation of VCII, a new active element VC-VCII is
obtained by slight changing. Utilizing VC-VCII, both the use of external resistor can be reduced, and its resistance value
electronically can be controlled electronically. Both proposed VCIIs have high DC current linearity. In addition, the sec-
ond proposed VCII has also high DC voltage linearity. Furthermore, both CMOS realizations of VCII can be operated
high frequency application due to high current and voltage transfer bandwidths.
To demonstrate the main performance parameters of VCII, DC swings, AC characteristics, noise, and temperature
analyses are given. Moreover, the variations of the important parameters of the VC-VCII have been investigated by
altering control voltage and transistor dimensions. Lastly, voltage mode first-order low-pass filter is given to utilize in
WLAN application.
YESIL AND MINAEI 15

DATA AVAILABILITY STATEMENT

Research data are not shared.

ORCID
Abdullah Yesil https://orcid.org/0000-0002-0607-8226
Shahram Minaei https://orcid.org/0000-0002-6921-9348

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How to cite this article: Yesil A, Minaei S. New simple transistor realizations of second- generation voltage
conveyor. Int J Circ Theor Appl. 2020;1–16. https://doi.org/10.1002/cta.2879