HB28D032MM2 Renesas PDF

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HB28H016MM2/HB28D032MM2
HB28B064MM2/HB28B128MM2
MultiMediaCard
16 MByte/32 MByte/64 MByte/128 MByte
ADE-203-1294E (Z)
Rev. 5.0
Jan. 16, 2003
Description
These Hitachi MultiMediaCards, HB28H016MM2, HB28D032MM2, HB28B064MM2 and
HB28B128MM2, are highly integrated flash memories with serial and random access capability. It is
accessible via a dedicated serial interface optimized for fast and reliable data transmission. This interface
allows several cards to be stacked by through connecting their peripheral contacts. These Hitachi
MultiMediaCards are fully compatible to a new consumer standard, called the MultiMediaCard system
standard defined in the MultiMediaCard system specification [1]. The MultiMediaCard system is a new
mass-storage system based on innovations in semiconductor technology. It has been developed to provide
an inexpensive, mechanically robust storage medium in card form for multimedia consumer applications.
MultiMediaCard allows the design of inexpensive players and drives without moving parts. A low power
consumption and a wide supply voltage range favors mobile, battery-powered applications such as audio
players, organizers, palmtops, electronic books, encyclopedia and dictionaries. Using very effective data
compression schemes such as MPEG, the MultiMediaCard will deliver enough capacity for all kinds of
multimedia data: software/programs, text, music, speech, images, video etc.
Note: MultiMediaCard is a trademark of Infineon Technologies AG.

HB28H016/D032/B064/B128MM2
Features
• 16 MByte/32 MByte/64 MByte/128 MByte memory capacity
• On card error correction
• MultiMediaCard system standard compatibility
 System specification version 3.1 compliant
 SPI mode supports the single and multiple block read and write operations.
 Block and partial block read supported (Command classes 2)
 Stream read supported (Command class 1)
 Block write and erase supported (Command classes 4 and 5)
 Group write protection (Command classes 6)
 Stream write supported (Command classes 3)
 Password data access protection
 Small erase block size of 512 bytes, tagged erase supported
 Read block size programmable between 1 and 2048 bytes
 VCC = 2.7 V to 3.6 V operation voltage range (VCC = 2.0 V to 3.6 V for the interface)
 No external programming voltage required
 Damage free powered card insertion and removal (no operation)
 4kV ESD protection (Contact Pads)
• High speed serial interface with random access
 Up to 10 stacked card (at 20 MHz, VCC = 2.7 to 3.6V)
 Access time: 300 µs (typ) (at 20 MHz, VCC = 2.7 to 3.6V)
• Low power dissipation
 High speed: 216 mW (max) (at 20 MHz, VCC = 3.6 V): HB28H016/D032/B064MM2
 High speed: 288 mW (max) (at 20 MHz, VCC = 3.6 V): HB28B128MM2
Rev.5.0, Jan. 2003, page 2 of 88

HB28H016/D032/B064/B128MM2
Block Diagram
1 2 3 4 5 6 7
VCC
VPP CS CMD/DI CLK/SCLK DAT/DO
Generator Interface driver
Internal clock
CMD
DAT
Power on reset unit

OCR[31:0]
Register
CID[127:0]
set
Interface
CSD[127:0]
RCA[15:0]
Flash control Core control
Memory core
All units in these Hitachi MultiMediaCards are clocked by an internal clock generator. The Interface
driver unit synchronizes the DAT and CMD signals from external CLK to the internal used clock signal.
The card is controlled by the three line MultiMediaCard interface containing the signals: CMD, CLK,
DAT (refer to Chapter “Interfaces”). For the identification of the MultiMediaCard in a stack of
MultiMediaCards, a card identification register (CID) and a relative card address register (RCA) is
foreseen. An additional register contains different types of operation parameters. This register is called
card specific data register (CSD). The communication using the MultiMediaCard lines to access either the
memory field or the registers is defined by the MultiMediaCard standard (refer to Chapter
“Communication”). The card has its own power on detection unit. No additional master reset signal is
required to setup the card after power on. It is protected against short circuit during insertion and removal
while the MultiMediaCard system is powered up (refer to Chapter “Power Supply”). No external
programming voltage supply is required. The programming voltage is generated on card.
These Hitachi MultiMediaCards support a second interface operation mode the SPI interface mode. The
SPI mode is activated if the CS signal is asserted (negative) during the reception of the reset command
(CMD0) (refer to Chapter “SPI Communication”).
Rev.5.0, Jan. 2003, page 3 of 88

HB28H016/D032/B064/B128MM2
Interface
These Hitachi MultiMediaCards' interface can operate in two different modes:
• MultiMediaCard mode
• SPI mode
Both modes are using the same pins. The default mode is the MultiMediaCard mode. The SPI mode is
selected by activating (= 0) the CS signal (Pin1) and sending the CMD0.
MultiMediaCard Mode
In the MultiMediaCard mode, all data is transferred over a minimal number of lines:
• CLK: with each cycle of this signal a one-bit transfer on the command and data lines is done. The
frequency may vary between zero and the maximum clock frequency. The MultiMediaCard bus master
is free to generate these cycles without restrictions in the range of 0 to 20 MHz.
• CMD: is a bidirectional command channel used for card initialization and data transfer commands.
The CMD signal has two operation modes: open drain for initialization mode and push pull for fast
command transfer. Commands are sent from the MultiMediaCard bus master to the MultiMediaCard
and responses vice versa.
• DAT: is a bidirectional data channel with a width of one line. The DAT signal of the MultiMediaCard
operates in push pull mode.
• RSV: is pulled up with resistor (2 MΩ typ) in the MultiMediaCard. The external pull-up resistor
should be recommended if the system requires.
ROD RDAT RCMD

Interface driver
CMD
DAT
CLK
1234567
MultiMediaCard Host
MultiMediaCard
MultiMediaCard Mode Interface
All MultiMediaCards are connected directly to the lines of the MultiMediaCard bus. The following table
defines the card contacts.
Rev.5.0, Jan. 2003, page 4 of 88

HB28H016/D032/B064/B128MM2
MultiMediaCard Mode Pad Definition
1
Pin No. Name Type* Description
1 RSV NC No connection
2 CMD I/O/PP/OD Command/Response
3 VSS1 S Ground
4 VCC S Power supply
5 CLK I Clock
6 VSS2 S Ground
7 DAT I/O/PP Data
Note: 1. S: power supply; I: input; O: output; PP: push-pull; OD: open-drain; NC: No connection or VIH
DAT
7
enable
MultiMediaCard interface controller

VSS2
6
CLK
5
Memory core interface

VCC
4
VSS1
3
CMD
2
OD/PP
RSV enable
1
Interface driver
MultiMediaCard Mode I/O-drivers
SPI Mode
The Serial Peripheral Interface (SPI) is a general-purpose synchronous serial interface originally found on
certain Motorola microcontrollers. The MultiMediaCard SPI interface is compatible with SPI hosts
Rev.5.0, Jan. 2003, page 5 of 88

HB28H016/D032/B064/B128MM2
available on the market. As any other SPI device the MultiMediaCard SPI interface consists of the
following four signals:
CS: Host to card Chip Select signal.
CLK: Host to card clock signal
Data in: Host to card data signal.
Data out: Card to host data signal.
The MultiMediaCard card identification and addressing methods are replaced by a hardware Chip Select
(CS) signal. There are no broadcast commands. For every command, a card (slave) is selected by
asserting (active low) the CS signal (refer to Figure “SPI Bus System”). The CS signal must be
continuously active for the duration of the SPI transaction (command, response and data). The only
exception occurs during card programming, when the host can de-assert the CS signal without affecting the
programming process. The bidirectional CMD and DAT lines are replaced by unidirectional data in and
data out signals. This eliminates the ability of executing commands while data is being read or written and,
therefore, makes the sequential and multi block read/write operations obsolete. The single and multiple
block read/write commands are supported by the SPI channel. The SPI interface uses the same seven
signals of the standard MultiMediaCard bus (refer to Table “SPI Interface Pin Configuration”).
CS
Power
SPI bus master
supply CS
SPI bus (CLK, Datain, Dataout)
SPI card SPI card
SPI Bus System
Rev.5.0, Jan. 2003, page 6 of 88

HB28H016/D032/B064/B128MM2
SPI Interface Pin Configuration
MuitiMediaCard SPI
1
Pin No. Name Type* Description Name Type Description
1 RSV NC Reserved for future use CS I Chip select (neg true)
2 CMD I/O/PP/OD Command/Response DI I Data in
3 VSS1 S Ground VSS S Ground
4 VCC S Power supply VCC S Power supply
5 CLK I Clock SCLK I Clock
6 VSS2 S Ground VSS2 S Ground
7 DAT I/O/PP Data DO O/PP Data out
Note: 1. S: power supply; I: input; O: output; PP: push-pull; OD: open-drain; NC: No connection or VIH
Registers
These Hitachi MultiMediaCards contain the following information registers:
Name Width Type Description

OCR 32 Programmed by the Supported voltage range, card power up status bit
manufacturer.
Read only for user
CID 128 Programmed by the Card identification number, card individual number for
manufacturer. identification.
Read only for user
RCA 16 Programmed during Relative card address, local system address of a card,
initialization, not readable dynamically assigned by the host during initialization.
CSD 128 Programmed by the Card specific data, information about the card operation
manufacturer. Partially conditions.
programmable by the user.
The CID and RCA are used for identifying and addressing the MultiMediaCard. The CSD contains the
card specific data record. This record is a set of information fields to define the operation conditions of the
MultiMediaCard.
For the user, the CID is read only register. The CSD contains read only area and some of one time or
multiple programmable area by the customer or provider. They are read out by special commands (refer to
Chapter “Commands”). The RCA registers are write only registers. Unlike CID and CSD, RCA looses its
contents after powering down the card. Its value is reassigned in each initialization cycle. The
MultiMediaCard registers usage in SPI mode is summarized in Table “MultiMediaCard Registers in SPI
Mode”:
Rev.5.0, Jan. 2003, page 7 of 88

HB28H016/D032/B064/B128MM2
MultiMediaCard Registers in SPI Mode
Name Available in SPI mode Width (Bytes) Description

OCR Yes 4 Operation condition register.
CID Yes 16 Card identification data (serial number, manufacturer ID
etc.)
RCA No
CSD Yes 16 Card specific data, information about the card operation
conditions.
Rev.5.0, Jan. 2003, page 8 of 88

HB28H016/D032/B064/B128MM2
Operation Condition Register (OCR)
This register indicates supported voltage range of these Hitachi MultiMediaCards. It is a 32 bit wide
register and for read only.
OCR Fields
OCR slice Field Value Note

D31 Card power up status bit (Busy). 0 or 1
D[30-24] reserved 0
D23 3.5 – 3.6V 1
D22 3.4 – 3.5V 1
D21 3.3 – 3.4V 1
D20 3.2 – 3.3V 1
D19 3.1 – 3.2V 1
D18 3.0 – 3.1V 1
D17 2.9 – 3.0 V 1
D16 2.8 – 2.9V 1
D15 2.7 – 2.8V 1
D14 2.6 – 2.7V 0
D13 2.5 – 2.6 V 0
D12 2.4 – 2.5V 0
D11 2.3 – 2.4V 0
D10 2.2 – 2.3V 0
D9 2.1 – 2.2V 0
D8 2.0 – 2.1V 0
D7 1.9 – 2.0 V 0
D6 1.8 – 1.9V 0
D5 1.7 – 1.8V 0
D4 1.65 – 1.7V 0
D3 1.60 – 1.65 V 0
D2 1.55 – 1.60V 0
D1 1.50 – 1.55V 0
D0 1.45 – 1.50V 0
Rev.5.0, Jan. 2003, page 9 of 88

HB28H016/D032/B064/B128MM2
Card Identification (CID)
This register contains the card identification information used during the card identification procedure. It
is a 128 bit wide register, one-time programmable by the provider. It was programmed at the manufacture.
The CID is divided into eight slices:
CID Fields
Name Field Width CID-slice Note

Manufacturer ID MID 8 [127:120] 1
OEM/Application ID OID 16 [119:104]
Product name PNM 48 [103:56]
Product revision PRV 8 [55:48]
Product serial number PSN 32 [47:16]
Manufacturing date MDT 8 [15:8]
7-bit CRC checksum CRC7 7 [7:1]
not used, always 1 — 1 [0:0]
Note: 1. The value of MID is 0x06.
The CID has to be error free. To ensure the correctness of the CID, a 7-bit CRC checksum is added to the
end of the CID. The CRC7 is computed according to chapter “Cyclic Redundancy Check (CRC)”.
Relative Card Address (RCA)
The 16-bit relative card address register carries the card address assigned by the host during the card
identification. This address is used for the addressed host to card communication after the card
identification procedure. The default value of the RCA register is 0x0001. The value 0x0000 is reserved
to set all cards in Standby State with the command SELECT_DESELECT_CARD (CMD7). The RCA is
programmed with the command SET_RELATIVE_ADDRESS (CMD3) during the initialization procedure.
The content of this register is lost after power down. The default value is assigned when an internal reset is
applied by the power up detection unit of these Hitachi MultiMediaCards, or when the command
GO_IDLE_STATE (CMD0) is detected by these Hitachi MultiMediaCards.
Rev.5.0, Jan. 2003, page 10 of 88

HB28H016/D032/B064/B128MM2
Card Specific Data (CSD)
The card specific data register describes how to access the card content. The CSD defines card operating
parameters like maximum data access time, data transfer speed.
The CSD Fields
Name Field Width CSD-slice Value Type

CSD structure CSD_STRUCTURE 2 [127:126] “10” read only
Spec version SPEC_VERS 4 [125:122] “0011” read only
Reserved — 2 [121:120] 0 read only
Data read access-time-1 TAAC 8 [119:112] 0x0E (1 ms) read only
Data read access-time-2 in NSAC 8 [111:104] 0x01 (100 cycles) read only
CLK cycles (NSAC*100)
Max. data transfer rate TRAN_SPEED 8 [103:96] 0x2A (20 Mbit/s) read only
Card command classes CCC 12 [95:84] 0x0FF (class 0, 1, read only
2, 3, 4, 5, 6, 7)
Max. read data block length READ_BLK_LEN 4 [83:80] 0x9 (512 bytes) read only
Partial blocks for read READ_BLK_PARTIAL 1 [79:79] ‘1’ (Enabled) read only
allowed
Write block misalignment WRITE_BLK_MISALIG 1 [78:78] ‘0’ (Disabled) read only
N
Read block misalignment READ_BLK_MISALIGN 1 [77:77] ‘0’ (Disabled) read only
DSR implemented DSR_IMP 1 [76:76] ‘0’ (Disabled) read only
1
Device size C_SIZE 12 [73:62] * read only
2
Max. read current at VDD min VDD_R_CURR_MIN 3 [61:59] * read only
Max. read current at VDD max VDD_R_CURR_MAX 3 [58:56] *2 read only
2
Max. write current at VDD min VDD_W_CURR_MIN 3 [55:53] * read only
2
Max. write current at VDD max VDD_W_CURR_MAX 3 [52:50] * read only
3
Device size multiplier C_SIZE_MULT 3 [49:47] * read only
Erase group size ERASE_GRP_SIZE 5 [46:42] 0 read only
Erase group size multiplier ERASE_GRP_MULT 5 [41:37] 0x0F read only
Rev.5.0, Jan. 2003, page 11 of 88

HB28H016/D032/B064/B128MM2
Name Field Width CSD-slice Value Type
Write protect group size WP_GRP_SIZE 5 [36:32] 0x01 (16 kByte) read only
Write protect group enable WP_GRP_ENABLE 1 [31:31] ‘1’ read only
Manufacturer default ECC DEFAULT_ECC 2 [30:29] 0 read only
Write speed factor R2W_FACTOR 3 [28:26] 2 (4) read only
Max. write data block length WRITE_BLK_LEN 4 [25:22] 9 (512 Bytes) read only
Partial blocks for write WRITE_BLK_PARTIAL 1 [21:21] ‘0’ read only
allowed
×*
4
File format group FILE_FORMAT_GRP 1 [15:15] read/write
Copy flag (OTP) COPY 1 [14:14] × read/write
Permanent write protection PERM_WRITE_PROTE 1 [13:13] × read/write
CT
Temporary write protection TMP_WRITE_PROTEC 1 [12:12] × read/write/
T erase
File format FILE_FORMAT 2 [11:10] × read/write
ECC code ECC 2 [9:8] × read/write/
erase
7-bit CRC CRC7 7 [7:1] × read/write/
erase
Not used, always 1 — 1 [0:0] 1 read only
Notes: 1. This field is depended on the model. Refer to also C_SIZE
2. This field is depended on the model.
3. This field is depended on the model. Refer to also C_SIZE_MULT
4. × means user programmable
Some of the CSD fields are one-time or multiple programmable by the customer or provider. All other
field values are fixed. The following section describes the CSD fields and their values for these Hitachi
MultiMediaCards:
• CSD_STRUCTURE
CSD Register Structure
CSD_STRUCTURE CSD register structure

“10” CSD version No. 1.2
The CSD version of these Hitachi MultiMediaCards is related to the “MultiMediaCard system
specification, Version 3.1”. The parameter CSD_STRUCTURE has permanently the value “10”.
Rev.5.0, Jan. 2003, page 12 of 88

HB28H016/D032/B064/B128MM2
• SPEC_VERS
Defines the Spec version supported by the card. It includes the commands set definition and the definition
of the card responses. The card identification procedure is compatible for all spec versions!
SPEC Version
SPEC_VERS System specification version number

“0011” System specification version 3.1
The Spec version of these Hitachi MultiMediaCards is related to the “MultiMediaCard system
specification, Version 3.1”. The parameter SPEC_VERS has permanently the value “0011”.
• TAAC
Defines the asynchronous data access time:
TAAC Access Time Definition
TAAC bit Description Values

2:0 time exponent 0 = 1 ns, 1 = 10 ns, 2 = 100 ns, 3 = 1 µs, 4 = 10 µs,
5 = 100 µs, 6 = 1 ms, 7 = 10 ms
6:3 time mantissa 0 = reserved, 1 = 1.0, 2 = 1.2, 3 = 1.3, 4 = 1.5,
5 = 2.0, 6 = 2.5, 7 = 3.0, 8 = 3.5, 9 = 4.0, A = 4.5,
B = 5.0, C = 5.5, D = 6.0, E = 7.0, F = 8.0
7 reserved always ‘0’
The value for the asynchronous delay for these Hitachi MultiMediaCards is 1 ms. The coded TAAC value
is 0x0E (= 1 ms). For more details refer to Chapter “Operating Characteristics”.
• NSAC
Defines the worst case for the synchronous data access time. The unit for NSAC is 100-clock cycles.
Therefore, maximum value for the data access time is 25.6k clock cycles. The total access time NAC as
expressed in the Table “Timing Values” is the sum of both TAAC and NSAC. It has to be computed by
the host for the actual clock rate. The read access time should be interpreted as a typical delay for the first
data bit of a data block or stream. The value of NSAC for these Hitachi MultiMediaCards is 0x01 (100-
clock cycles). For more details refer to Chapter “Operating Characteristics”.
Rev.5.0, Jan. 2003, page 13 of 88

HB28H016/D032/B064/B128MM2
• TRAN_SPEED
The following table defines the maximum data transfer rate TRAN_SPEED:
Maximum Data Transfer Rate Definition
TRAN_SPEED bit Description Values

2:0 transfer rate exponent 0 = 100 kbit/s, 1 = 1 Mbit/s, 2 = 10
Mbit/s, 3 = 100 Mbit/s, 4...7 =
reserved
6:3 time mantissa 0x0 = reserved, 0x1 = 1.0, 0x2 =
1.2, 0x3 = 1.3, 0x4 = 1.5, 0x5 = 2.0,
0x6 = 2.5, 0x7 = 3.0, 0x8 = 3.5, 0x9
= 4.0, 0xA = 4.5, 0xB = 5.0, 0xC =
5.5, 0xD = 6.0, 0xE = 7.0, 0xF = 8.0
7 reserved always ’0’
These Hitachi MultiMediaCards support a transfer rate between 0 and 20 Mbit/s. The parameter
TRAN_SPEED is 0x2A.
• CCC
The MultiMediaCard command set is divided into subsets (command classes). The card command class
register CCC defines which command classes are supported by this card. A set CCC bit means that the
corresponding command class is supported. For command class definition refer to Table “Command
Classes”.
Supported Card Command Classes
CCC bit Supported card command classes

0 class0
1 class1
...... ......
11 class11
These Hitachi MultiMediaCards support the command classes 0, 1, 2, 3, 4, 5, 6 and 7. The parameter CCC
is permanently assigned to the value 0x0FF.
Rev.5.0, Jan. 2003, page 14 of 88

HB28H016/D032/B064/B128MM2
• READ_BLK_LEN
READ_BLK_LEN
The data block length is computed as 2 .
Data Block Length
READ_BLK_LEN Block length Remark

0
0 2 = 1 byte
1
1 2 = 2 bytes
...... ......
11
11 2 = 2048 bytes
12–15 reserved
The block length might therefore be in the range 1, 2, 4...2048 bytes. This parameter defines the block
length if READ_BLK_PARTIAL is not set. If READ_BLK_PARTIAL is set this parameter contains the
maximum allowed value of the block length in bytes. All block lengths between one and this value are
permitted. The actual block size is programmed by the command SET_BLOCKLEN (CMD16). These
Hitachi MultiMediaCards support block lengths from 1 byte up to 2048 bytes. The default value of the
parameter READ_BLK_LEN is 0x9 (512 bytes).
• READ_BLK_PARTIAL
READ_BLK_PARTIAL defines whether partial block sizes can be used in block read command.
READ_BLK_PARTIAL = 0 means that only the block size defined by READ_BLK_LEN can be used for
block-oriented data transfers. READ_BLK_PARTIAL = 1 means that smaller blocks can be used as well.
The minimum block size will be equal to minimum addressable unit (one byte). These Hitachi
MultiMediaCards support partial block read. The parameter READ_BLK_PARTIAL is permanently
assigned to the value ‘1’.
• WRITE_BLK_MISALIGN
Defines if the data block to be written by one command can be spread over more than one physical blocks
of the memory device. The size of the memory block is defined in WRITE_BLK_LEN.
WRITE_BLK_MISALIGN is permanently assigned to the value ‘0’, signaling that crossing physical block
boundaries is not allowed.
• READ_BLK_MISALIGN
Defines if the data block to be read by one command can be spread over more than one physical block of
the memory device. The size of the data block is defined in READ_BLK_LEN.
READ_BLK_MISALIGN = 0 signals that crossing physical block boundaries is not allowed.
READ_BLK_MISALIGN = 1 signals that crossing physical block boundaries is allowed. These Hitachi
MultiMediaCards do not support read block operations with boundary crossing. The parameter
READ_BLK_MISALIGN is permanently assigned to the value ‘0’.
Rev.5.0, Jan. 2003, page 15 of 88

HB28H016/D032/B064/B128MM2
• DSR_IMP
Defines if the configurable driver stage option is integrated on the card or not. If implemented a driver
stage register (DSR) must be implemented also.
DSR Implementation
DSR_IMP DSR type

0 no DSR implemented
1 DSR implemented
These Hitachi MultiMediaCards' output drivers are not configurable. The parameter DSR_IMP is
permanently assigned to the value ‘0’.
• C_SIZE
This parameter is used to compute the card capacity. The card capacity is computed from the entries
C_SIZE, C_SIZE_MULT and READ_BLK_LEN as follows:
memory capacity = BLOCKNR*BLOCK_LEN
Where
BLOCKNR = (C_SIZE+1)*MULT
(C_SIZE_MULT < 8)
C_SIZE_MULT+2
MULT = 2
, (READ_BLK_LEN < 12)

READ_BLK_LEN
BLOCK_LEN = 2
Therefore, the maximal capacity which can be coded is 4096*512*2048 = 4 GBytes.
The following table shows the card capacity for each model.
Model C_SIZE C_SIZE_MULT READ_BLK_LEN Card Capacity

HB28H016MM2 0x7A7 2 9 16 MByte
HB28D032MM2 0x7A7 3 9 32 MByte
HB28B064MM2 0x7A7 4 9 64 MByte
HB28B128MM2 0x7A7 5 9 128 MByte
Rev.5.0, Jan. 2003, page 16 of 88

HB28H016/D032/B064/B128MM2
• VDD_R_CURR_MIN, VDD_W_CURR_MIN
The maximum supply current at the minimum supply voltage VCC (2.7 V) is coded as follows:
Maximum Supply Current Consumption at VCC = 2.7 V
VDD_R_CURR_MIN
VDD_W_CURR_MIN Code for current consumption at 2.7 V
2:0 0 = 0.5 mA; 1 = 1 mA; 2 = 5 mA; 3 = 10 mA; 4 = 25 mA; 5 = 35 mA; 6
= 60 mA; 7 = 100 mA
The parameter VDD_R_CURR_MIN and VDD_W_CURR_MIN are permanently assigned. The value of
VDD_R_CURR_MIN and VDD_W_CURR_MIN for each model is following:
Model Value
HB28H016MM2 6 (60 mA)
HB28D032MM2 6 (60 mA)
HB28B064MM2 6 (60 mA)
HB28B128MM2 6 (60 mA)
• VDD_R_CURR_MAX, VDD_W_CURR_MAX
The maximum supply current at the maximum supply voltage VCC (3.6 V) is coded as follows:
Maximum Supply Current Consumption at VCC = 3.6 V
VDD_R_CURR_MAX
VDD_W_CURR_MAX Code for current consumption at 3.6 V
2:0 0 = 1 mA; 1 = 5 mA; 2 = 10 mA; 3 = 25 mA; 4 = 35 mA; 5 = 45 mA; 6 =
80 mA; 7 = 200 mA
The parameter VDD_R_CURR_MAX and VDD_W_CURR_MAX are permanently assigned. The value
of VDD_R_CURR_MAX and VDD_W_CURR_MAX for each model is following:
Model Value
HB28H016MM2 6 (80 mA)
HB28D032MM2 6 (80 mA)
HB28B064MM2 6 (80 mA)
HB28B128MM2 6 (80 mA)
For more details refer to Chapter “Characteristics”.
Rev.5.0, Jan. 2003, page 17 of 88

HB28H016/D032/B064/B128MM2
• C_SIZE_MULT
This parameter is used for coding a factor MULT for computing the total device size (refer to “C_SIZE”).
C_SIZE_MULT+2
The factor MULT is defined as 2 .
Multiply Factor for the Device Size
C_SIZE_MULT MULT Remark

2
0 2 =4
3
1 2 =8
4
2 2 = 16
5
3 2 = 32
6
4 2 = 64
7
5 2 = 128
8
6 2 = 256
9
7 2 = 512
The card capacity is shown at “C_SIZE”.
• ERASE_GRP_SIZE
The contents of this register is a 5 bit binary coded value, used to calculate the size of the erasable unit of
these Hitachi MultiMediaCards. The size of the erase unit (also referred to as erase group in chapter
“Memory Array Partitioning”) is determined by the ERASE_GRP_SIZE and the ERASE_GRP_MULT
entries of the CSD, using the following equation:
size of erasable unit = (ERASE_GRP_SIZE + 1) * (ERASE_GRP_MULT + 1)
The parameter ERASE_GRP_SIZE is permanently assigned to the value ‘0’. The size of erasable unit for
these Hitachi MultiMediaCards is (0+1) * (15+1) = 16, which means that the 8 kByte area can be erased in
a single erase group command (CMD35 to CMD38).
• ERASE_GRP_MULT
A 5 bit binary coded value is used for calculating the size of the erasable unit of these Hitachi
MultiMediaCards. The parameter ERASE_GRP_MULT is permanently assigned to the value 0x0F. See
ERASE_GRP_SIZE section for detailed description.
• WP_GRP_SIZE
The size of a write protection group. The content of this register is a binary coded value defining the
number of erase group. This parameter's value is 1, which means that a write protect group size is 16
kByte.
• WP_GRP_ENABLE
The value is set to ‘1’, meaning group write protection is enabled.
Rev.5.0, Jan. 2003, page 18 of 88

HB28H016/D032/B064/B128MM2
• DEFAULT_ECC
Set by the card manufacturer and defines the ECC code which is recommended to use (e.g. the device is
tested for). The value is set to ‘0’, indicating that no designated ECC is recommended.
• R2W_FACTOR
Defines the typical block program time as a multiple of the read access time. The following table defines
the field format.
R2W_FACTOR
R2W_FACTOR Multiples of read access time

0 1
1 2 (write half as fast as read)
2 4
3 8
4 16
5 32
6, 7 reserved
This parameter value is 2 for these Hitachi MultiMediaCards.
• WRITE_BLK_LEN
WRITE_BLK_LEN
The data block length is computed as 2 .
Data Block Length
WRITE_BLK_LEN Block length Remark

0
0 2 = 1 byte
1
1 2 = 2 bytes
...... ......
11
11 2 = 2048 bytes
12–15 reserved
The block length might therefore be in the range 1, 2, 4...2048 bytes. This parameter defines the block
length if WRITE_BLK_PARTIAL is not set. If WRITE_BLK_PARTIAL is set this parameter contains the
maximum allowed value of the block length in bytes. All block lengths between one and this value are
permitted. The actual block size is programmed by the command SET_BLOCKLEN (CMD16). These
Hitachi MultiMediaCards support blocks with the length 512 bytes. The parameter WRITE_BLK_LEN is
permanently assigned to the value 0x9 (512 bytes).
Rev.5.0, Jan. 2003, page 19 of 88

HB28H016/D032/B064/B128MM2
• WRITE_BLK_PARTIAL
WRITE_BLK_PARTIAL defines whether partial block sizes can be used in block read and block write
commands. WRITE_BLK_PARTIAL = 0 means that only the block size defined by WRITE_BLK_LEN
can be used for block-oriented data transfers. WRITE_BLK_PARTIAL = 1 means that smaller blocks can
be used as well. The minimum block size will be equal to minimum addressable unit (one byte). These
Hitachi MultiMediaCards support no partial block write. The parameter WRITE_BLK_PARTIAL is
permanently assigned to the value ‘0’.
• FILE_FORMAT_GRP
Indicates the selected group of file formats. The default value is ‘0’. This field is read-only for ROM. The
usage of this field is shown in table “File_Formats”.
• COPY
Defines if the contents are an original (COPY = ‘0’) or a copy (= ‘1’). The COPY bit is a one time
programmable bit, being set by the customer. The default value is ‘0’.
• PERM_WRITE_PROTECT
Permanently protects the whole card content against overwriting or erasing (all write and erase commands
for this card is a permanently disabled). This parameter is one-time programmable by the customer. The
default value is ‘0’ (not protected).
• TMP_WRITE_PROTECT
Temporarily protects the whole card content from being overwritten or erased (all write and erase
commands for this card are temporarily disabled). This parameter is programmable by the customer. The
default value is ‘0’ (not protected).
• FILE_FORMAT
Indicates the file format on the card. The default value is ‘0’. This field is read-only for ROM. The
following formats are defined:
File_Formats
FILE_FORMAT_GRP FILE_FORMAT Type

0 0 Hard disk-like file system with partition table
0 1 DOS FAT (floppy-like) with boot sector only (no partition table)
0 2 Universal File Format
0 3 Others/Unknown
1 0, 1, 2, 3 Reserved
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HB28H016/D032/B064/B128MM2
• ECC
Defines the ECC code that was used for storing data on the card. This field is used by the host (or
application) to decode the user data. The following table defines the field format.
ECC
ECC ECC type Maximum number of correctable bits

0 none (default) none
1 BCH (542,512) 3
2–3 reserved —
The content provider or customer defines which kind of error correction may be used to protect the
contents of the MultiMediaCard. This value is programmable.
• CRC7
The CRC7 contains the check sum for the CSD content. The check sum is computed according to chapter
“Cyclic Redundancy Check (CRC)”.
The user has to recalculate a new CRC7 after defining a new CSD.
Rev.5.0, Jan. 2003, page 21 of 88

HB28H016/D032/B064/B128MM2
MultiMediaCard Communication
All communication between host and cards is controlled by the host (master). The host sends commands
and, depending on the command, receives a corresponding response from the selected card. In this chapter
the commands to control these Hitachi MultiMediaCards, the card responses and the contents of the status
and error field included in the responses, are defined.
Memory Array Partitioning
The basic unit of data transfer to/from the MultiMediaCard is one byte. All data transfer operations which
require a block size always define block lengths as integer multiples of bytes. Some special functions need
other partition granularity. For block-oriented commands, the following definition is used:
• Block: is the unit which is related to the block-oriented read and write commands. Its size is the
number of bytes which will be transferred when one block command is sent by the host. The size of a
block is either programmable or fixed. The information about allowed block sizes and the
programmability is stored in the CSD.
For devices which have erasable memory cells, special erase commands are defined. The granularity of the
erasable units is:
• Sector: is the unit which is related to the tagged sector commands (CMD32 to CMD34). In these
Hitachi MultiMediaCards, this size is same as the WRITE_BLK_LEN in CSD.
• Erase Group: is the smallest number of consecutive write blocks, which can be addressed for erased.
The size of the Erase Group is card specific and stored in the CSD.
For devices which include a write protection:
• WP-Group: is the minimal unit which may have individual write protection. Its size is the number of
erase groups which will be write protected by one bit. The size of a WP-group is fixed for each device.
The information about the size is stored in the CSD.
Each erasable unit (erase group and sector) has a special “tag” bit. This bit may be set or cleared by special
commands to tag the unit. All tagged units will be erased in parallel by one erase command following a
number of tag commands. All tag bits are cleared by each command except a tag or untag command.
Therefore, immediately after a sequence of tag commands an erase command has to be sent by the host.
Commands others than tagging or erasing abort a tag-erase cycle irregularly.
Rev.5.0, Jan. 2003, page 22 of 88

HB28H016/D032/B064/B128MM2
MultiMediaCard
ERASE
GROUP 0
Block 0 Block 1 Block 2 Block 3 Block n
Sector 0.0
Sector tagging
Sector 0.1
Group tagging
Sector 0.2
Sector 0.3
Sector 0.n
ERASE
GROUP 1
ERASE
GROUP n
Erase Tagging Hierarchy
Each WP-group may have an additional write protection bit. The write protection bits are programmable
via special commands (refer to Chapter “Commands”). The information about the availability is stored in
the CSD.
Group write protection
WP-GROUP 0
WP-GROUP 1
WP-GROUP n
Write Protection
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HB28H016/D032/B064/B128MM2
Commands
The command set of the MultiMediaCard system is divided into classes corresponding to the type of card
(see also [1]). These Hitachi MultiMediaCards support the following command classes:
Command Classes (Class 0 to Class 2)
Supported commands
Card command 0 1 2 3 4 7 9 10 11 12 13 15 16 17 18
class (CCC) Class description
Class 0 basic + + + + + + + + + + +
Class 1 stream read +
Class 2 block read + + +
Command Classes (Class 2 to Class 7)
Supported commands
Card command 20 23 24 25 26 27 28 29 30 32 33 34 35 36 37 38 42
class (CCC) Class description
Class 2 block read +
Class 3 stream write +
Class 4 block write + + + + +
Class 5 erase + + + + + + +
Class 6 write protection + + +
Class 7 lock card +
Class 0 is mandatory and supported by all cards. It represents the card identification and initialization
commands, which are intended to handle different cards and card types on the same bus lines. The Card
Command Class (CCC) is coded in the card specific data register of each card, so that the host knows how
to access the card. There are four kinds of commands defined on the MultiMediaCard bus:
• broadcast commands (bc) sent on CMD line, no response

• broadcast commands with response (bcr) sent on CMD line, response (all cards simultaneously) on
CMD line
• addressed (point-to-point) commands (ac) sent on CMD line, response on CMD line
• addressed (point-to-point) data transfer commands (adtc) sent on CMD line, response on CMD line,
data transfer on DAT line
Rev.5.0, Jan. 2003, page 24 of 88

HB28H016/D032/B064/B128MM2
The command transmission always starts with the MSB. Each command starts with a start bit and ends with
a 7-bit CRC command protection field followed by an end bit. The length of each command frame is fixed
to 48 bits (2.4 µs at 20 MHz):
0 1 bit5...bit0 bit31...bit0 bit6...bit0 1

start bit host command argument CRC*1 end bit
Note: 1. (Cyclic Redundancy Check)
The start bit is always ‘0’ in command frames (sent from host to MultiMediaCard). The host bit is always
‘1’ for commands. The command field contains the binary coded command number. The argument
depends on the command (refer to Table “Basic Commands (class 0) and Table “Block-Oriented Read
Commands (class 2)”). The CRC field is defined in Chapter “Cyclic Redundancy Check (CRC)”.
Rev.5.0, Jan. 2003, page 25 of 88

HB28H016/D032/B064/B128MM2
Read, Write and Erase Time-out Conditions

The times after which a time-out condition for read/write/erase operations occurs are (card independent) 10
times longer than the access/program times for these operations given below. A card shall complete the
command within this time period, or give up and return an error message. If the host does not get a
response within the defined time-out it should assume the card is not going to respond anymore and try to
recover (e.g. reset the card, power cycle, reject, etc.). The typical access and program times are defined as
follows:
Read
The read access time is defined as the sum of the two times given by the CSD parameters TAAC and
NSAC (refer to Table “Card Specific Data (CSD)”). These card parameters define the typical delay
between the end bit of the read command and the start bit of the data block. This number is card dependent
and should be used by the host to calculate throughput and the maximal frequency for stream read.
Write
The R2W_FACTOR field in the CSD is used to calculate the typical block program time obtained by
multiplying the read access time by this factor. It applies to all write/erase commands (e.g.
SET(CLEAR)_WRITE_PROTECT, PROGRAM_CSD(CID) and the block write commands). It should be
used by the host to calculate throughput and the maximal frequency for stream write.
Erase
The duration of an erase command will be (order of magnitude) the number of sectors to be erased
multiplied by the block write delay.
Rev.5.0, Jan. 2003, page 26 of 88

HB28H016/D032/B064/B128MM2
Basic Commands (class 0) and Read Stream Command (class 1)
CMD
index Type Argument Resp Abbreviation Command description
CMD0 bc [31:0] stuff bits — GO_IDLE_STATE resets all cards to Idle State
CMD1 bcr [31:0] OCR R3 SEND_OP_COND checks for cards not supporting the full
without busy range of 2.0 V to 3.6 V. After receiving
CMD1 the card sends an R3 response
(refer to Chapter “Responses”).
CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID asks all cards in ready state to send
1
their CID* numbers on CMD-line
CMD3 ac [31:16] RCA R1 SET_RELATIVE_A assigns relative address to the card in
[15:0] stuff bits DDR identification state.
CMD4 bc [31:16] DSR — SET_DSR programs the DSR of all cards in
[15:0] stuff bits stand-by state.
CMD7 ac [31:16] RCA R1b (only SELECT/ command toggles a card between the
[15:0] stuff bits the DESELECT_CARD standby and transfer states or between
selected the programming and disconnect state.
card) In both cases the card is selected by
its own relative address while
deselecting the prior selected card.
Address 0 deselects all.
CMD9 ac [31:16] RCA R2 SEND_CSD asks the addressed card to send its
2
[15:0] stuff bits card-specific data (CSD)* on CMD-
line.
CMD10 ac [31:16] RCA R2 SEND_CID asks the addressed card to send its
[15:0] stuff bits card identification (CID) on CMD- line.
CMD11 adtc [31:0] data R1 READ_DAT_UNTIL reads data stream from the card,
address _STOP starting at the given address, until a
STOP_TRANSMISSION follows.
3
CMD12 ac [31:0] stuff bits R1b* STOP_TRANSMISS forces the card to stop transmission
ION
CMD13 ac [31:16] RCA R1 SEND_STATUS Asks the addressed card to send its
[15:0] stuff bits status register.
CMD15 ac [31:16] RCA — GO_INACTIVE_ST Sets the card to inactive state in order
[15:0] stuff bits ATE to protect the card stack against
communications breakdowns.
Notes: 1. CID register consists of 128 bits (starting with MSB, it is preceded by an additional start bit, ends
with an end bit)
2. CSD register consists of 128 bits (starting with MSB, it is preceded by an additional start bit,
ends with an end bit)
3. This command is indicating the busy status of the MultiMediaCard via the data channel.
Rev.5.0, Jan. 2003, page 27 of 88

HB28H016/D032/B064/B128MM2
Block-Oriented Read Commands (class 2)
CMD
CMD16 ac [31:0] block R1 SET_BLOCKLEN Selects a block length (in bytes) for all
length following block-oriented read
1
commands and lock card command.*
CMD17 adtc [31:0] data R1 READ_SINGLE_BL Reads a block of the size selected by
2
address OCK the SET_BLOCKLEN command.*
CMD18 adtc [31:0] data R1 READ_MULTIPLE_ Continuously send blocks of data until
address BLOCK interrupted by a stop.
Notes: 1. The default block length is as specified in the CSD. These Hitachi MultiMediaCards do not
support partial block write, so the write block size defined by WRITE_BLK_LEN is parmanently
assigned to the value 512 bytes.
2. The data transferred must not cross a physical block boundary unless READ_BLK_MISALIGN is
set in the CSD. These Hitachi MultiMediaCards do not support read block operations with
boundary crossing (READ_BLK_MISALIGN = ‘0’), so the data transferred must not cross a
physical block boundary.
Stream Write Command (class 3)
CMD
CMD20 adtc [31:0] data R1 WRITE_DAT_ Writes data stream from the host,
address UNTIL_STOP starting at the given address, until a
STOP_TRANSMISSION follows.
Block-Oriented Read/Write Command (class 2/4)
CMD
CMD23 ac [31:16] set to 0 R1 SET_BLOCK_COU Defines the number of blocks which
[15:0] number of NT are going to be transferred in the
blocks immediately succeeding multiple block
read or write command.
Rev.5.0, Jan. 2003, page 28 of 88

HB28H016/D032/B064/B128MM2
Block-Oriented Write Commands (class 4)
CMD
CMD24 adtc [31:0] data R1 WRITE_BLOCK Write a block. The write-block-length
address of the Hitachi MultiMediaCard is
permanently assigned to the value 512
1
bytes.*
CMD25 adtc [31:0] data R1 WRITE_MULTIPLE Continuously writes blocks of data until
address _ BLOCK a STOP_TRANSMISSION follows.
CMD26 adtc [31:0] stuff bits R1 PROGRAM_CID Programming of the card identification
register. This command is only done
once per MultiMediaCard card. The
card has some hardware to prevent
this operation after the first
programming. Normally this command
is reserved for the manufacturer. The
CID register is programmed at the
manufacture.
CMD27 adtc [31:0] stuff bits R1 PROGRAM_CSD Programming of the programmable bits
of the CSD.
Note: 1. The data transferred must not cross a physical block boundary unless WRITE_BLK_MISALIGN
is set in the CSD. These Hitachi MultiMediaCards do not support write block operations with
bondary crossing (WRITE_BLK_MISALIGN = ‘0’), so the data transferred must not cross a
Rev.5.0, Jan. 2003, page 29 of 88

HB28H016/D032/B064/B128MM2
Erase Commands (class 5)
CMD
CMD32 ac [31:0] data R1 TAG_SECTOR_ST Sets the address of the first sector of
1
address ART the erase group.*
CMD33 ac [31:0] data R1 TAG_SECTOR_EN Sets the address of the last sector in a
address D continuous range within the selected
erase group to be selected for erase,
or the address of a single sector to be
1
selected.*
CMD34 ac [31:0] data R1 UNTAG_SECTOR Removes one previously selected
address sector from the erase selection.*1
CMD35 ac [31:0] data R1 TAG_ERASE_GRO Sets the address of the first erase
address UP_START group within a range to be selected for
erase
CMD36 ac [31:0] data R1 TAG_ERASE_GRO Sets the address of the last erase
address UP_END group within a continuous range to be
selected for erase
CMD37 ac [31:0] data R1 UNTAG_ERASE_G Removes one previously selected
1
address ROUP erase group from the erase selection*
CMD38 ac [31:0] stuff bits R1b ERASE Erases all previously selected sectors
Note: 1. “MultiMediaCard system specification Version 3.1” does not support these commands, but these
Hitachi MultiMediaCards support them to keep backward compatibility with former
MultiMediaCard series.
Rev.5.0, Jan. 2003, page 30 of 88

HB28H016/D032/B064/B128MM2
Write Protection Commands (class 6)
CMD
CMD28 ac [31:0] data R1b SET_WRITE_PROT if the card has write protection
address features, this command sets the write
protection bit of the addressed group.
The properties of write protection are
coded in the card specific data
(WP_GRP_SIZE).
CMD29 ac [31:0] data R1b CLR_WRITE_PROT if the card provides write protection
address features, this command clears the
write protection bit of the addressed
group.
CMD30 adtc [31:0] write R1 SEND_WRITE_PR if the card provides write protection
protect data OT features, this command asks the card
address to send the status of the write
1
protection bits.*
Note: 1. 32 write protection bits (representing 32 write protect groups starting at the specified address)
followed by 16 CRC bits are transferred in a payload format via the data line. The last (least
significant) bit of the protection bits corresponds to the first addressed group. If the addresses
of the last groups are outside the valid range, then the corresponding write protection bits shall
be set to zero.
Lock Card Command (class 7)
CMD
CMD42 adtc [31:0] stuff bits R1b LOCK_UNLOCK used to set/reset the password or
lock/unlock the card. The size of the
data block is set by the
SET_BLOCK_LEN command.
Rev.5.0, Jan. 2003, page 31 of 88

HB28H016/D032/B064/B128MM2
Other Command
CMD index Type Argument Resp Abbreviation Command description

CMD5 reserved
CMD6 reserved
CMD8 reserved
CMD14 reserved
CMD19 reserved
CMD21 … reserved
CMD22
CMD31 reserved
CMD39 Not
supported
CMD40 Not
supported
CMD41 reserved
CMD43 … reserved
CMD54
CMD55 ac [31:16] RCA R1 APP_CMD Indicates to the card that the next
[15:0] stuff bits command is an application specific
command rather than a standard
command
These Hitachi MultiMediaCards do
not support this command.
CMD56 adtc [31:1] RCA R1b GEN_CMD Used either to transfer a data block to
1
[0] RD/WR* the card or to get a data block from
the card for general purpose /
application specific commands. The
size of the data block shall be set by
the SET_BLOCK_LEN command.
CMD57 … reserved
CMD63
Note: 1. ‘1’ the host gets a block of data from the card.
‘0’ the host sends block of data to the card.
Rev.5.0, Jan. 2003, page 32 of 88

HB28H016/D032/B064/B128MM2
Card identification mode
All the data communication in the card identification mode uses only the command line (CMD).
Power on
Idle state CMD0

(idle) from all states except (ina)
card is busy or
host omitted
voltage range
CMD1 Inactive state CMD15
(ina)
cards with non-compatible voltage range
card looses bus Ready state
(ready)
card wins bus
CMD2
Identification state
(ident)
CMD3 card-identification mode
Stand-by state data-transfer mode from all states in data-transfer mode

(stby)
MultiMediaCard State Diagram (Card Identification Mode)
The host starts the card identification process in open drain mode with the identification clock rate fOD
(generated by a push pull driver stage). The open drain driver stages on the CMD line allow the parallel
card operation during card identification. After the bus is activated the host will request the cards to send
their valid operation conditions with the command SEND_OP_COND (CMD1). Since the bus is in open
drain mode, as long as there is more than one card with operating conditions restrictions, the host gets in
the response to the CMD1 a “wired or” operation condition restrictions of those cards. The host then must
pick a common denominator for operation and notify the application that cards with out of range
parameters (from the host perspective) are connected to the bus. Incompatible cards go into Inactive State
(refer to also Chapter “Operating Voltage Range Validation”). The busy bit in the CMD1 response can be
used by a card to tell the host that it is still working on its power-up/reset procedure (e.g. downloading the
register information from memory field) and is not ready yet for communication. In this case the host must
repeat CMD1 until the busy bit is cleared. After an operating mode is established, the host asks all cards
for their unique card identification (CID) number with the broadcast command ALL_SEND_CID (CMD2).
All not already identified cards (i.e. those which are in Ready State) simultaneously start sending their CID
numbers serially, while bit-wise monitoring their outgoing bitstream. Those cards, whose outgoing CID
bits do not match the corresponding bits on the command line in any one of the bit periods, stop sending
Rev.5.0, Jan. 2003, page 33 of 88

HB28H016/D032/B064/B128MM2
their CID immediately and must wait for the next identification cycle (cards stay in the Ready State).
There should be only one card which successfully sends its full CID-number to the host. This card then
goes into the Identification State. The host assigns to this card (using CMD3, SET_RELATIVE_ADDR) a
relative card address (RCA, shorter than CID), which will be used to address the card in future
communication (faster than with the CID). Once the RCA is received the card transfers to the Standby
State and does not react to further identification cycles. The card also switches the output drivers from the
open-drain to the push-pull mode in this state. The host repeats the identification process as long as it
receives a response (CID) to its identification command (CMD2). When no card responds to this
command, all cards have been identified. The time-out condition to recognize this, is waiting for the start
bit for more than 5 clock periods after sending CMD2.
Operating Voltage Range Validation
The MultiMediaCard standards operating range validation is intended to support reduced voltage range
MultiMediaCards. These Hitachi MultiMediaCards support the range of 2.7 V to 3.6V supply voltage. So
these Hitachi MultiMediaCards send a R3 response to CMD1 which contains an OCR value of
0x80FF8000 if the busy flag is set to “ready” or 0x00FF8000 if the busy flag is active (refer to Chapter
“Responses”). By omitting the voltage range in the command, the host can query the card stack and
determine the common voltage range before sending out-of-range cards into the Inactive State. This bus
query should be used if the host is able to select a common voltage range or if a notification to the
application of non usable cards in the stack is desired. Afterwards, the host must choose a voltage for
operation and reissue CMD1 with this condition, sending incompatible cards into the Inactive State.
Rev.5.0, Jan. 2003, page 34 of 88

HB28H016/D032/B064/B128MM2
Data Transfer Mode
When in Standby State, both CMD and DAT lines are in the push-pull mode. As long as the content of all
CSD registers is not known, the fPP clock rate is equal to the slow fOD clock rate. SEND_CSD (CMD9)
allows the host to get the Card Specific Data (CSD register), e.g. ECC type, block length, card storage
capacity, maximum clock rate etc..
card-identification mode CMD3 CMD15 CMD0

Sending-data state
(data)
data-transfer mode from all states in
data-transfer mode
CMD12, CMD11, 17, 18, 30
CMD13 ''operation
complete''
no state transition CMD7
in data-transfer mode
Stand-by state CMD7 Transfer state
(stby) (tran) CMD16, 23, 32...37
CMD9, 10
CMD20, 24, 25, 26, 27, 42
''operation
''operation complete''
complete''
CMD24, 25 Receive-data state

(rcv)
CMD28, 29, 38
CMD7 CMD12 or
Disconnect state Programming state
(dis) (prg) ''transfer end''
CMD7
MultiMediaCard State Diagram (Data Transfer Mode)
The command SELECT_DESELECT_CARD (CMD7) is used to select one card and place it in the
Transfer State. If a previously selected card is in the Transfer State its connection with the host is released
and it will move back to the Stand-by State. Only one card can be, at any time, in the Transfer State. A
selected card is responding the CMD7, the deselected one does not respond to this command. When
CMD7 is sent including the reserved relative card address 0x0000, all cards transfer back to Stand-by State.
This command is used to identify new cards without resetting other already acquired cards. Cards to which
an RCA has already been assigned, do not respond to the identification command flow in this state. All the
data communication in the Data Transfer Mode is consequently a point-to point communication between
the host and the selected card (using addressed commands). All addressed commands are acknowledged
by a response on the CMD line. All read commands (data is sent from the card via data lines) can be
interrupted at any time, by a stop command. The data transfer will terminate and the card will stop or start
working on the next command. The DAT bus line signal level is high when no data is transmitted. A
transmitted data block consists of a start bit (LOW), followed by a continuous data stream. The data
stream contains the net payload data (and error correction bits if an off-card ECC is used). The data stream
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HB28H016/D032/B064/B128MM2
ends with an end bit (HIGH). The data transmission is synchronous to the clock signal. The payload for
block-oriented data transfer is preserved by a 16-bit CRC check sum (refer to Chapter “Cyclic Redundancy
Check (CRC)”).
• Stream read
There is a stream oriented data transfer controlled by READ_DAT_UNTIL_STOP (CMD11). This
command instructs the card to send its payload, starting at a specified address, until the host sends a
STOP_TRANSMISSION command (CMD12). The stop command has an execution delay due to the serial
command transmission. The data transfer stops after the end bit of the stop command. If the end of the
memory range is reached while sending data and no stop command has been sent yet by the host, the
contents of the further transferred payload is undefined. The maximum clock frequency for stream read
operation is given by the following formula:
READ_BL_LEN
max. speed = min (TRAN_SPEED, (8*2 -NSAC)/TAAC),
= min (20, (8*2 ) − 100 [cycles])/1000 [µs]) [MHz]

9
= min (20, 3.996) 3.996 [MHz]
these parameters being defined in Chapter “Registers”. If the host attempts to use a higher frequency, the
card may not be able to sustain data transfer. If this happens, the card will set the UNDERRUN error bit in
the status register, abort the transmission and wait in the data state for a stop command.
• Block read
The basic unit of data transfer is a block whose maximum size is defined in the CSD (READ_BLK_LEN).
READ_BLK_PARTIAL is set, thus smaller blocks whose starting and ending address are wholly contained
within one physical block (as defined by READ_BLK_LEN) may also be transmitted. A 16-bit CRC is
appended to the end of each block ensuring data transfer integrity. READ_SINGLE_BLOCK (CMD17)
starts a block read and after a complete transfer the card goes back to Transfer State.
READ_MULTIPLE_BLOCK (CMD18) starts a transfer of several consecutive blocks. Two types of

multiple block read transactions are defined (the host can use either one at any time):
• Open-ended Multiple block read

The number of blocks for the read multiple block operation is not defined. The card will
continuously transfer data blocks until a stop transmission command is received.
• Multiple block read with pre-defined block count
The card will transfer the requested number of data blocks, terminate the transaction and return to
transfer state. Stop command is not required at the end of this type of multiple block read, unless
terminated with an error. In order to start a multiple block read with pre-defined block count, the
host must use the SET_BLOCK_COUNT command (CMD23) immediately preceding the
READ_MULTIPLE_BLOCK (CMD18) command. Otherwise the card will start an open-ended
multiple block read which can be stopped using the STOP_TRANSMISSION command.
The host can abort reading at any time, within a multiple block operation, regardless of the its type.
Transaction abort is done by sending the stop transmission command.
If the card detects an error (e.g. out of range, address misalignment, internal error, etc.) during a multiple
block read operation (both types) it will stop data transmission and remain in the Data State. The host must
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HB28H016/D032/B064/B128MM2
than abort the operation by sending the stop transmission command. The read error is reported in the
response to the stop transmission command.
If the host sends a stop transmission command after the card transmits the last block of a multiple block
operation with a pre-defined number of blocks, it will be responded to as an illegal command, since the
card is no longer in data state.
If the host uses partial blocks whose accumulated length is not block aligned and block misalignment is not
allowed, the card shall detect a block misalignment error condition at the beginning of the first misaligned
block (ADDRESS_ERROR error bit will be set in the status register).
• Stream write
Stream write (CMD20) starts the data transfer from the host to the card beginning from the starting address
until the host issues a stop command. If partial blocks are allowed (if CSD parameter
WRITE_BL_PARTIAL is set) the data stream can start and stop at any address within the card address
space, otherwise it shall start and stop only at block boundaries. Since the amount of data to be transferred
is not determined in advance, CRC can not be used. If the end of the memory range is reached while
sending data and no stop command has been sent by the host, all further transferred data is discarded. The
maximum clock frequency for stream write operation is given by the following formula:
WRITE_BL_LEN
max. speed = min ( TRAN_SPEED, (8*2 -NSAC)/(TAAC*R2W_FACTOR)),
9
= min (20, (8*2 – 100 [cycles])/1000 [µs]*4)[MHz] = min (20, 0.999) 0.999 [MHz]
these parameters being defined in Chapter “Registers”. If the host attempts to use a higher frequency, the
card may not be able to process the data and will stop programming, set the OVERRUN error bit in the
status register, and while ignoring all further data transfer, wait (in the Receive-data-State) for a stop
command. The write operation shall also be aborted if the host tries to write over a write-protected area.
In this case, however, the card shall set the WP_VIOLATION bit.
• Block write
Block write (CMD24 - 27) means that one or more blocks of data are transferred from the host to the card
with a 16-bit CRC appended to the end of each block by the host. A card supporting block write must
always be able to accept a block of data defined by WRITE_BLK_LEN. If the CRC fails, the card will
indicate the failure on the DAT line; the transferred data will be discarded and not written and all further
transmitted blocks (in multiple block write mode) will be ignored.
WRITE_MULTIPLE_BLOCK (CMD25) starts a transfer of several consecutive blocks. Two types of

multiple block write transactions, identical to the multiple block read, are defined (the host can use either
one at any time):
• Open-ended Multiple block write

The number of blocks for the write multiple block operation is not defined. The card will
continuously accept and program data blocks until a stop transmission command is received.
• Multiple block write with pre-defined block count
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transfer state. Stop command is not required at the end of this type of multiple block write, unless
terminated with an error. In order to start a multiple block write with pre-defined block count, the
WRITE_MULTIPLE_BLOCK (CMD25) command. Otherwise the card will start an open-ended
multiple block write which can be stopped using the STOP_TRANSMISSION command.
The host can abort writing at any time, within a multiple block operation, regardless of the its type.
Transaction abort is done by sending the stop transmission command. If a multiple block write with
predefined block count is aborted, the data in the remaining blocks is not defined.
If the card detects an error (e.g. write protect violation, out of range, address misalignment, internal error,
etc.) during a multiple block write operation (both types) it will ignore any further incoming data blocks
and remain in the Receive State. The host must than abort the operation by sending the stop transmission
command. The write error is reported in the response to the stop transmission command.
If the host sends a stop transmission command after the card received the last block of a multiple block
write with a pre-defined number of blocks, it will be responded to as an illegal command, since the card is
no longer in rcv state.
allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card will detect the block misalignment
error and abort programming before the beginning of the first misaligned block. The card will set the
ADDRESS_ERROR error bit in the status register, and wait (in the Receive-data-State) for a stop
command while ignoring all further data transfer. The write operation will also be aborted if the host tries
to write over a write-protected area. In this case, however, the card will set the WP_VIOLATION bit.
Programming of the CID and CSD register does not require a previous block length setting. The
transferred data is also CRC protected.
• Erase
It is desirable to erase as many sectors at a time as possible in order to enhance the data throughput.
Identification of these sectors is accomplished with the TAG_* commands. Either an arbitrary set of
sectors within a single erase group, or an arbitrary selection of erase groups may be erased at one time, but
not both together. That is, the unit of measure for determining an erase is either a sector or an erase group,
but if a sector, all selected sectors must lie within the same erase group. To facilitate selection, a first
command with the starting address is followed by a second command with the final address, and all sectors
within this range will be selected for erase. After a range is selected, an individual sector (or group) within
that range can be removed using the UNTAG command. The host must adhere to the following command
sequence; TAG_SECTOR_START, TAG_SECTOR_END, UNTAG_SECTOR (up to 16 untag sector
commands can be sent for one erase cycle) and ERASE (or the same sequence for group tagging). The
following exception conditions are detected by the card: An erase or tag/untag command is received out of
sequence. The card will set the ERASE_SEQUENCE error bit in the status register and reset the whole
sequence. An out of sequence command (except SEND_STATUS) is received. The card will set the
ERASE_RESET status bit in the status register, reset the erase sequence and execute the last command. If
the erase range includes write protected sectors, they will be left intact and only the non-protected sectors
will be erased. The WP_ERASE_SKIP status bit in the status register will be set. The address field in the
tag commands is a sector or a group address in byte units. The card will ignore all LSB’s below the group
or sector size. The number of untags commands (CMD34 and CMD37) which are used in a sequence is
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limited up to 16. As described above for block write, the card will indicate that an erase is in progress by
holding DAT low. The actual erase time may be quite long, and the host may choose to deselect the card
using CMD7.
• Write protect management

Card data may be protected against either erase or write. The entire card may be permanently write
protected by the manufacturer or content provider by setting the permanent or temporary write protect bits
in the CSD. Portions of the data may be protected (in units of WP_GRP_SIZE sectors as specified in the
CSD), and the write protection may be changed by the application. The SET_WRITE_PROT command
sets the write protection of the addressed write-protect group, and the CLR_WRITE_PROT command
clears the write protection of the addressed write-protect group. The SEND_WRITE_PROT command is
similar to a single block read command. The card shall send a data block containing 32 write protection
bits (representing 32 write protect groups starting at the specified address) followed by 16 CRC bits. The
address field in the write protect commands is a group address in byte units. The card will ignore all LSB’s
below the group size.
• Card lock/unlock operation

The password protection feature enables the host to lock a card while providing a password, which later
will be used for unlocking the card. The password and its size are kept in a 128-bit PWD and 8-bit
PWD_LEN registers, respectively. These registers are non-volatile so that a power cycle will not erase
them. Locked cards respond to (and execute) all commands in the "basic" command class (class 0) and
“lock card” command class. Thus the host is allowed to reset, initialize, select, query for status, etc., but
not to access data on the card. If the password was previously set (the value of PWD_LEN is not‘0’) will
be locked automatically after power on. Similar to the existing CSD and CID register write commands the
lock/unlock command is available in "transfer state" only. This means that it does not include an address
argument and the card has to be selected before using it. The card lock/unlock command has the structure
and bus transaction type of a regular single block write command. The transferred data block includes all
the required information of the command (password setting mode, PWD itself, card lock/unlock etc.). The
following table describes the structure of the command data block.
Lock Card Data Structure
Byte# Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

0 Reserved ERASE LOCK_ CLR_ SET_
UNLOCK PWD PWD
1 PWD_LEN
2 Password data
...
PWD_LEN + 1
• ERASE: 1 Defines Forced Erase Operation (all other bits shall be ‘0’) and only the cmd byte is
sent.
• LOCK/UNLOCK: 1 = Locks the card. 0 = Unlock the card (note that it is valid to set this bit
together with SET_PWD but it is not allowed to set it together with CLR_PWD).
• CLR_PWD: 1 = Clears PWD.
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HB28H016/D032/B064/B128MM2
• SET_PWD: 1 = Set new password to PWD
• PWD_LEN: Defines the following password length (in bytes).
• PWD: The password (new or currently used depending on the command).
The data block size shall be defined by the host before it sends the card lock/unlock command. This will
allow different password sizes. The following paragraphs define the various lock/unlock command
sequences:
• Setting the Password

—Select a card (CMD7), if not previously selected already
—Define the block length (CMD16), given by the 8bit card lock/unlock mode, the 8-bit password
size (in bytes), and the number of bytes of the new password. In case that a password replacement
is done, then the block size shall consider that both passwords, the old and the new one, are sent
with the command.
—Send Card Lock/Unlock command with the appropriate data block size on the data line
including 16-bit CRC. The data block shall indicate the mode (SET_PWD), the length
(PWD_LEN) and the password itself. In case that a password replacement is done, then the length
value (PWD_LEN) shall include both passwords, the old and the new one, and the PWD field
shall include the old password (currently used) followed by the new password.
—In case that the sent old password is not correct (not equal in size and content) then
LOCK_UNLOCK_FAILED error bit will be set in the status register and the old password
does not change. In case that PWD matches the sent old password then the given new password
and its size will be saved in the PWD and PWD_LEN fields, respectively.
Note that the password length register (PWD_LEN) indicates if a password is currently set. When it equals
‘0’ there is no password set. If the value of PWD_LEN is not equal to zero the card will lock itself after
power up. It is possible to lock the card immediately in the current power session by set-ting the
LOCK/UNLOCK bit (while setting the password) or sending additional command for card lock.
• Reset the Password:

—Define the block length (CMD16), given by the 8 bit card lock/unlock mode, the 8 bit password
size (in bytes), and the number of bytes of the currently used password.
—Send the card lock/unlock command with the appropriate data block size on the data line
including 16-bit CRC. The data block shall indicate the mode CLR_PWD, the length
(PWD_LEN) and the password (PWD) itself (LOCK/UNLOCK bit is don’t care). If the PWD
and PWD_LEN content match the sent password and its size, then the content of the PWD
register is cleared and PWD_LEN is set to 0. If the password is not correct then the
LOCK_UNLOCK_FAILED error bit will be set in the status register.
• Locking a card:
—Define the block length (CMD16), given by the 8 bit card lock/unlock mode, the 8 bit
password size (in bytes), and the number of bytes of the currently used password.
—Send the card lock/unlock command with the appropriate data block size on the data
line including 16-bit CRC. The data block shall indicate the mode LOCK, the length
(PWD_LEN) and the password (PWD) itself.
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If the PWD content equals to the sent password then the card will be locked and the card-locked status bit
will be set in the status register. If the password is not correct then LOCK_UNLOCK_FAILED error bit
will be set in the status register. Note that it is possible to set the password and to lock the card in the same
sequence. In such case the host shall perform all the required steps for setting the password (as described
above) including the bit LOCK set while the new password command is sent. If the password was
previously set (PWD_LEN is not ‘0’), then the card will be locked automatically after power on reset. An
attempt to lock a locked card or to lock a card that does not have a password will fail and the
• Unlocking the card:

—Select a card (CMD7), if not previously selected already.
—Define the block length (CMD16), given by the 8 bit card lock/unlock mode, the 8 bit
password size (in bytes), and the number of bytes of the currently used password.
—Send the card lock/unlock command with the appropriate data block size on the data
line including 16-bit CRC. The data block shall indicate the mode UNLOCK, the length
(PWD_LEN) and the password (PWD) itself.
If the PWD content equals to the sent password then the card will be unlocked and the card-locked status
bit will be cleared in the status register. If the password is not correct then the LOCK_UNLOCK_FAILED
error bit will be set in the status register. Note that the unlocking is done only for the current power
session. As long as the PWD is not cleared the card will be locked automatically on the next power up.
The only way to unlock the card is by clearing the password. An attempt to unlock an unlocked card will
fail and LOCK_UNLOCK_FAILED error bit will be set in the status register.
• Forcing Erase:
In case that the user forgot the password (the PWD content) it is possible to erase all the card data content
along with the PWD content. This operation is called Forced Erase.
—Select a card (CMD7), if not previously selected already.

—Define the block length (CMD16) to 1 byte (8bit card lock/unlock command). Send
the card lock/unlock command with the appropriate data block of one byte on the data
line including 16-bit CRC. The data block shall indicate the mode ERASE (the ERASE
bit shall be the only bit set).
If the ERASE bit is not the only bit in the data field then the LOCK_UNLOCK_FAILED error bit will be
set in the status register and the erase request is rejected. If the command was accepted then ALL THE
CARD CONTENT WILL BE ERASED including the PWD and PWD_LEN register content and the
locked card will get unlocked. An attempt to force erase on an unlocked card will fail and
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HB28H016/D032/B064/B128MM2
• State transition summary
Table “Card State Transition Table” defines the card state transitions as a function of received command
Card State Transition Table
Current state
Command idle ready ident stby tran data rcv prg dis ina
1
CRC fail —* — — — — — — — — —
Commands out of the — — — — — — — — — —
supported class(es)
Class0 CMD0 idle idle idle idle idle idle idle idle idle —
CMD1, card VCC ready — — — — — — — — —
range compatible
CMD1, card is idle — — — — — — — — —
busy
CMD1, card VCC ina — — — — — — — — —
range not
compatible
CMD2, card wins — ident — — — — — — — —
bus
CMD2, card loses — ready — — — — — — — —
bus
CMD3 — — stby — — — — — — —
CMD4 — — — stby — — — — — —
CMD7, card is — — — tran — — — — prg —
addressed
CMD7, card is not — — — — stby stby — dis — —
addressed
CMD9 — — — stby — — — — — —
CMD10 — — — stby — — — — — —
CMD12 — — — — — tran prg — — —
CMD13 — — — stby tran data rcv prg dis —
CMD15 — — — ina ina ina ina ina ina —
Class1 CMD11 — — — — data — — — — —
Class2 CMD16 — — — — tran — — — — —
CMD17 — — — — data — — — — —
CMD18 — — — — data — — — — —
CMD 23 — — — — tran — — — — —
Class3 CMD20 — — — — rcv — — — — —
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Current state
Command idle ready ident stby tran data rcv prg dis ina
Class4 CMD16 see class 2
CMD23 see class 2
CMD24 — — — — rcv — — rcv — —
CMD25 — — — — rcv — — rcv — —
CMD26 — — — — rcv — — — — —
CMD27 — — — — rcv — — — — —
Class5 CMD32 — — — — tran — — — — —
CMD33 — — — — tran — — — — —
CMD34 — — — — tran — — — — —
CMD35 — — — — tran — — — — —
CMD36 — — — — tran — — — — —
CMD37 — — — — tran — — — — —
CMD38 — — — — prg — — — — —
Class6 CMD28 — — — — prg — — — — —
CMD29 — — — — prg — — — — —
CMD30 — — — — data — — — — —
Class7 CMD42 — — — — rcv — — — — —
Notes: 1. “—” means command is ignored, no state change and no response.
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Responses
All responses are sent via command line (CMD), all data starts with the MSB.
Format R1 (response command): response length 48 bit.

start bit card command status CRC end bit
The contents of the status field are described in Chapter “Status”
Format R1b (response command with busy signal):
R1b is identical to R1 with an optional busy signal transmitted on the data line. The card may become
busy after receiving these commands based on its state prior to the command reception.
Format R2 (CID, CSD register): response length 136 bits.
Note: Bit 127 down to bit 1 of CID and CSD are transferred, the reserved bit [0] is replaced by the end bit.
0 0 bit5...bit0 bit127...bit1 1
start bit card reserved CID or CSD register end bit
including internal CRC
CID register is sent as a response to commands CMD2 and CMD10.
CSD register is sent as a response to the CMD9.
Format R3 (OCR): response length 48 bits.

start bit card reserved OCR field reserved end bit
The OCR is sent as a response to the CMD1 to signalize the supported voltage range. These Hitachi
MultiMediaCards support the range from 2.7 V to 3.6 V. Respectively the value of all bits of the OCR
field of these Hitachi MultiMediaCards is set to 0x80FF8000. So the R3 frame contains the value
0x3F80FF8000FF if the card is ready and 0x3F00FF8000FF if the card is busy.
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Status
The response format R1 contains a 32-bit field with the name card status. This field is intended to transmit
status information which is stored in a local status register of each card to the host. The following table
defines the status register structure. The Type and Clear-Condition fields in the table are coded as follows:
• Type:
• E: Error bit.
• S: Status bit.
• R: Detected and set for the actual command response.
• X: Detected and set during command execution. The host must poll the card by sending status
command in order to read these bits.
• Clear Condition:
• A: According to the card state.
• B: Always related to the previous command. Reception of a valid command will clear it (with a
delay of one command).
• C: Clear by read.
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Status
Bits Identifier Type Value Description Clear condition

31 OUT_OF_RANGE ER ’0’= no error The commands argument was out C
’1’= error of allowed range for this card.
30 ADDRESS_ERROR E R X ’0’= no error A misaligned address, which did C
’1’= error not match the block length was
used in the command.
29 BLOCK_LEN_ERRO E R ’0’= no error The transferred block length is not C
R ’1’= error allowed for this card or the
number of transferred bytes does
not match the block length
28 ERASE_SEQ_ERR ER ’0’= no error An error in the sequence of erase C
OR ’1’= error commands occurred.
27 ERASE_PARAM EX ’0’= no error An invalid selection, sectors or C
’1’= error groups, for erase.
26 WP_VIOLATION E R X ’0’= not protected The command tried to write a C
’1’= protected write protected block.
25 CARD_IS_LOCKED S X ’0’= card When set, signals that the card is A
unlocked locked by the host.
’1’= card locked
24 LOCK_UNLOCK_ E R X ’0’= no error Set when a sequence or C
FAILED ’1’= error password error has been
detected in lock/unlock card
command or it there was an
attempt to access a locked card.
23 COM_CRC_ERROR E R ’0’= no error The CRC check of the previous B
’1’= error command failed.
22 ILLEGAL_COMMAN E R ’0’= no error Command not legal for the B
D ’1’= error current state
21 CARD_ECC_FAILE E X ’0’= success Card internal ECC was applied C
D ’1’= failure but the correction of data is failed.
20 CC_ERROR E R X ’0’= no error Internal card controller error C
’1’= error
19 ERROR E R X ’0’= no error A general or an unknown error C
’1’= error occurred during the operation.
18 UNDERRUN EX ’0’= no error The card could not sustain data C
’1’= error transfer in stream read mode.
17 OVERRUN EX ’0’= no error The card could not sustain data C
’1’= error programming in stream write
mode.
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Bits Identifier Type Value Description Clear Condition
16 CID_OVERWRITE/ E R X ’0’= no error can be either one of the following C
CSD_OVERWRITE ’1’= error errors:
• The CID register is already
written and can not be
overwritten.
• The read only section of the
CSD does not match the card
content.
• An attempt to reverse the
copy (set as original) or
permanent WP (unprotected)
bits was done.
15 WP_ERASE_SKIP SX ’0’= not protected Only partial address space was C
’1’= protected erased due to existing WP blocks.
14 CARD_ECC_ SX ’0’= enabled The command has been executed A
DISABLED ’1’= disabled without using the internal ECC.
13 ERASE_RESET SR ’0’= cleared An erase sequence was cleared C
’1’= set before executing because an out
of erase sequence command was
received
12:9 CURRENT_STATE SX 0 = idle Current state of the card. B
1 = ready
2 = ident
3 = stby
4 = tran
5 = data
6 = rcv
7 = prg
8 = dis
9-15 = reserved
8 BUFFER_EMPTY SX ’0’= not empty corresponds to buffer empty A
’1’= empty signaling on the bus
7:6 reserved Permanently 0
5 APP_CMD SR ’0’= disabled The card will expect APP_CMD or C
’1’= enabled indication that the command has
been interpreted as APP_CMD.
4 reserved Permanently 0
3:2 reserved for application specific commands
1:0 reserved for manufacturer test mode
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Command Response Timings
All timing diagrams use the following schematics and abbreviations:
S: Start bit (= 0)
T: Transmitter bit (Host = 1, Card = 0)
P: One-cycle pull-up (= 1)
E: End bit (= 1)
Z: high impedance state (-> = 1)
D: Data bits
*: repeater
CRC: Cyclic redundancy check bits (7 bits for command or response, 16 bits for block data)
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while the Z-bit is driven to (respectively kept) HIGH by the pull-up
resistors RCMD respectively RDAT. Actively driven P-bits are less sensitive to noise superposition. For the
timing of these Hitachi MultiMediaCards, the following values are defined:
Timing Values
Value [clock cycles]

Symbol Min Max Description
NCR 2 64 Number of cycles between command and
response
NID 5 5 Number of cycles between card identification
or card operation conditions command and the
corresponding response
1 2
NAC 2* TAAC + NSAC* Number of cycles between a command and
the start of a related data block
NRC 8 — Number of cycles between the last response
and a new command
NCC 8 — Number of cycles between two commands, if
no response will be sent after the first
command (e.g. broadcast)
NWR 2 — Number of cycles between a write command
and the start of a related data block
NST 2 2 Number of cycles between stop command and
valid read / write data end
Notes: 1. Refer to Chapter “Electrical Characteristics” for more details about the access time.
2. Refer to Chapter “Time-out Condition”.
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HB28H016/D032/B064/B128MM2
The host command and the card response are clocked out with the rising edge of the host clock. The delay
between host command and card response is NCR clock cycles. The following timing diagram is relevant
for host command CMD3:
Host command NCR cycles Response

CMD S T content CRC E Z ****** ZS T content CRC E Z Z Z
Host active Card active
Command Response Timing (Identification Mode)
There is just one Z bit period followed by P bits pushed up by the responding card. The following timing
diagram is relevant for all host commands followed by a response, except CMD1, CMD2 and CMD3:

CMD S T content CRC E Z Z P *** P S T content CRC E Z Z Z
Command Response Timing (Data Transfer Mode)
• Card identification and card operation conditions timing

The card identification (CMD2) and card operation condition (CMD1) timing are processed in the open-
drain mode. The card response to the host command starts after exactly NID clock cycles.
Host command NID cycles CID or OCR

CMD S T content CRC E Z *** Z S T content Z Z Z
Identification Timing (Card Identification Mode)
• Last card response - next host command timing

After receiving the last card response, the host can start the next command transmission after at least NRC
clock cycles. This timing is relevant for any host command.
Response NRC cycles Host command

CMD S T content CRC E Z ****** ZS T content CRC E
Card active Host active
Timing Response End to Next CMD Start (Data Transfer Mode)
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HB28H016/D032/B064/B128MM2
• Last host command - next host command timing diagram
After the last command, which does not force a response, has been sent, the host can continue sending the
next command after at least NCC clock periods.
Host command NCC cycles Host command

CMD S T content CRC E Z ****** ZS T content CRC E
Host active Host active
Timing CMDn End to CMDn+1 Start (All Modes)
In the case the CMDn command was a last identification command (no more response sent by a card), then
the next CMDn+1 command is allowed to follow after at least NCC +136 (the length of the R2 response) clock
periods.
• Data access timing

Data transmission starts with the access time delay tAC (which corresponds to NAC), beginning from the end
bit of the data address command. The data transfer stops automatically in case of a data block transfer or
by a transfer stop command.

CMD S T content CRC E Z Z P *** P S T content CRC E

NAC cycles Read data
DAT Z Z Z **** Z Z Z Z Z Z P *********** P S D D D ***
Card active
Data Read Timing (Data Transfer Mode)
• Data transfer stop command timing

The card data transmission can be stopped using the stop command. The data transmission stops
immediately with the end bit of the stop command.

CMD S T content CRC E Z Z P *** P S T content CRC E
Host active NST Card active
DAT D D D ******** D D D E Z Z **********************
Card active
Timing of Stop Command (CMD12, Data Transfer Mode)
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HB28H016/D032/B064/B128MM2
• Stream read
The data transfer starts NAC clock cycles after the end bit of the host command. The bus transaction is
identical to that of a read block command (refer to Figure “Data Read Timing”). As the data transfer is not
block-oriented, the data stream does not include the CRC checksum. Consequently the host can not check
for data validity. The data stream is terminated by a stop command. The corresponding bus transaction is
identical to the stop command for the multiple read block (refer to Figure “Timing of Stop Command”).
• Single or multiple block write

The host selects one card for data write operation by CMD7. The host sets the valid block length for
block-oriented data transfer by CMD16 (The write-block-length of the Hitachi MultiMediaCard is
permanently assigned to the value 512 bytes). The host transfers the data with CMD24. The address of the
data block is determined by the argument of this command. This command is responded by the card on the
CMD line as usual. The data transfer from the host starts NWR clock cycles after the card response was
received. The write data have CRC check bits to allow the card to check the transferred data for
transmission errors. The card sends the CRC check information as a CRC status to the host (on the data
line). The CRC status contains the information if the write data transfer was non-erroneous (the CRC
check did not fail) or not. In the case of transmission error the card sends a negative CRC status (“101”
bin) which forces the host to retransmit command and the data. In the case of non-erroneous transmission
the card sends a positive CRC status (“010” bin) and starts the data programming procedure.
NCR
Host command Card response
CMD S T content CRC E S T content CRC E
NWR
Host active Card active Write data
DAT Z Z Z **** Z Z Z Z Z Z Z Z Z **** Z Z Z Z Z P S content
Host active
CMD
Write data CRC status Card busy

DAT content CRC E Z Z S status E S busy = 'L' E Z
L ... pull down to LOW bit
Timing of The Block Write Command
If the card does not have any more free data receive buffer, the card indicates it by pulling down the data
line to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the
defined data transfer block length becomes free. This signaling does not give any information about the
data write status. This information has to be polled by the status polling command (SEND_STATUS).
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HB28H016/D032/B064/B128MM2
• Stream write
The data transfer starts NWR clock cycles after the card response to the sequential write command was
received. The bus transaction is identical to that of a write block command (see Figure “Timing of The
Block Write Command”). As the data transfer is not block-oriented, the data stream does not include the
CRC checksum. Consequently the host can not receive any CRC status information from the card. The
data stream is terminated by a stop command. The bus transaction is identical to the write block option
when a data block is interrupted by the stop command (see Figure “Stop Transmission During Data
Transfer From The Host”).
Host command NCR cycles Card response Host command

CMD S T content CRC E Z Z P *** P S T content CRC E S T content
NST
Card is programming
DAT D D D D D D D D D D E Z Z S L *** *** *** *** *** *** E Z Z Z Z Z Z Z Z
Valid write data
Stop Transmission During Data Transfer From The Host
• Erase block timing

The host must first tag the sector to erase. The tagged sector(s) are erased in parallel by using the CMD32-
CMD38. The card busy signaling is also used for the indication of the card erase procedure duration. In
this case the end of the card busy signaling also does mean that the erase of all tagged sectors has been
finished. The host can (also) request the card to send the actual card state using the CMD13.
NCR Card response

CMD T content CRC E S T content CRC E
card is erasing
Host active card busy
DAT Z Z *********** Z Z Z S L L ******************** L E
Card active
Host command
CMD S T content CRC E

Host active
DAT L ***** L E Z ********

Card active
L ... pull down to LOW bit
Timing of Erase Operation
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HB28H016/D032/B064/B128MM2
Reset
GO_IDLE_STATE (CMD0) is the software reset command, which sets the MultiMediaCard into the Idle
State independently of the current state. In the Inactive State the MultiMediaCard is not affected by this
command. After power-on the MultiMediaCard is always in the Idle State. After power-on or command
GO_IDLE_STATE (CMD0) all output bus drivers of the MultiMediaCard is in a high-impedance state and
the card will be initialized with a default relative card address (0x0001). The host runs the bus at the
identification clock rate fOD generated by a push-pull driver stage (refer to also Chapter “Power on” for
more details).
CMD0 is valid in all states with the exception of the Inactive State. While in Inactive state the card will not
accept CMD0 unless it is used to switch the card into SPI mode.
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SPI Communication
The SPI mode consists of a secondary communication protocol. This mode is a subset of the
MultiMediaCard protocol, designed to communicate with a SPI channel, commonly found in Motorola’s
(and lately a few other vendors’) microcontrollers. The interface is selected during the first reset command
after power up (CMD0) and cannot be changed once the part is powered on. The SPI standard defines the
physical link only, and not the complete data transfer protocol. The MultiMediaCard SPI implementation
uses a subset of the MultiMediaCard protocol and command set. It is intended to be used by systems
which require a small number of card (typically one) and have lower data transfer rates (compared to
MultiMediaCard protocol based systems). From the application point of view, the advantage of the SPI
mode is the capability of using an off-the-shelf host, hence reducing the design-in effort to minimum. The
disadvantage is the loss of performance of the SPI system versus MultiMediaCard (lower data transfer rate,
fewer cards, hardware CS per card etc.). While the MultiMediaCard channel is based on command and
data bitstreams which are initiated by a start bit and terminated by a stop bit, the SPI channel is byte
oriented. Every command or data block is built of 8-bit bytes and is byte aligned to the CS signal (i.e. the
length is a multiple of 8 clock cycles). Similar to the MultiMediaCard protocol, the SPI messages consist
of command, response and data-block tokens (refer to Chapter “Commands” and Chapter “Responses” for
a detailed description). All communication between host and cards is controlled by the host (master). The
host starts every bus transaction by asserting the CS signal low. The response behavior in the SPI mode
differs from the MultiMediaCard mode in the following three aspects:
• The selected card always responds to the command.

• An additional (8 bit) response structure is used
• When the card encounters a data retrieval problem, it will respond with an error response (which
replaces the expected data block) rather than by a time-out as in the MultiMediaCard mode.
Single block and multiple read and write operations are supported in SPI mode. In addition to the
command response, every data block sent to the card during write operations will be responded with a
special data response token. A data block may be as big as one card sector and as small as a single byte.
Partial block read/write operations are enabled by card options specified in the CSD register.
Mode Selection
The MultiMediaCard wakes up in the MultiMediaCard mode. It will enter SPI mode if the reset command
(CMD0) is received during the CS signal is asserted (negative). Selecting SPI mode is not restricted to Idle
state (the state the card enters after power up) only. Every time the card receives CMD0, including while
in Inactive state, CS signal is sampled.
If the card recognizes that the MultiMediaCard mode is required it will not respond to the command and
remain in the MultiMediaCard mode. If SPI mode is required the card will switch to SPI and respond with
the SPI mode R1 response.
The only way to return to the MultiMediaCard mode is by entering the power cycle. In SPI mode the
MultiMediaCard protocol state machine is not observed. All the MultiMediaCard commands supported in
SPI mode are always available.
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HB28H016/D032/B064/B128MM2
Bus Transfer Protection
Every MultiMediaCard token transferred on the bus is protected by CRC bits. In SPI mode, the
MultiMediaCard offers a non-protected mode which enables systems built with reliable data links to
exclude the hardware or firmware required for implementing the CRC generation and verification
functions. In the non-protected mode the CRC bits of the command, response and data tokens are still
required in the tokens. However, they are defined as “don’t care” for the transmitter and ignored by the
receiver. The SPI interface is initialized in the non protected mode. However, the RESET command
(CMD0), which is used to switch the card to SPI mode, is received by the card while in MultiMediaCard
mode and, therefore, must have a valid CRC field.
The host can turn this option on and off using the CRC_ON_OFF command (CMD59).
Data Read Overview
The SPI mode supports single and multiple block read operations (CMD17 and CMD18 in the
MultiMediaCard protocol). The main difference between SPI and MultiMediaCard modes is that the data
and the response are both transmitted to the host on the DataOut signal (refer to Figure 43 and Figure 45).
Therefore the card response to the STOP_COMMAND may cut-short and replace the last data block (refer
to Figure “Read Operation”).
from from data from card Next

host card to host command
to card to host
Data in command command
Data out response data block CRC
Single Block Read Operation
from from data from card Stop

host card to host command
to card to host
Data out response data block CRC data block CRC data B. response
Multiple Block Read Operation
The basic unit of data transfer is a block whose maximum size is defined in the CSD (READ_BL_LEN). If
READ_BL_PARTIAL is set, smaller blocks whose starting and ending addresses are entirely contained
within one physical block (as defined by READ_BL_LEN) may also be transmitted. A 16-bit CRC is
appended to the end of each block ensuring data transfer integrity (also refer to chapter “Cyclic
Redundancy Check (CRC)”). CMD17 (READ_SINGLE_BLOCK) initiates a single block read. CMD18
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HB28H016/D032/B064/B128MM2
(READ_MULTIPLE_BLOCK) starts a transfer of several consecutive blocks. Two types of multiple
block read transactions are defined (the host can use either one at any time):
• Open-ended Multiple block read

The number of blocks for the read multiple block operation is not defined. The card will
continuously transfer data blocks until a stop transmission command is received.
• Multiple block read with pre-defined block count
transfer state. Stop command is not required at the end of this type of multiple block read, unless
terminated with an error. In order to start a multiple block read with pre-defined block count, the
READ_MULTIPLE_BLOCK (CMD18) command. Otherwise the card will start an open-ended
multiple block read which can be stopped using the STOP_TRANSMISSION command.
The host can abort reading at any time, within a multiple block operation, regardless of the its type.
Transaction abort is done by sending the stop transmission command.
In case of a data retrieval error, the card will not transmit any data. Instead, a special data error token will
be sent to the host. Figure “Read Operation-Data Error” shows a data read operation which terminated
with an error token rather than a data block.
from from data error token Next

host card from card to host command
to card to host
Data out response data error
Read Operation-Data Error
Data Write Overview
As for the read operation, while in SPI mode the MultiMediaCard supports single and multiple block write
commands. Upon reception of a valid write command (CMD24 and CMD25 in the MultiMediaCard
protocol), the card will respond with a response token and will wait for a data block to be sent from the
host. CRC suffix, block length and start address restrictions are (with the exception of the CSD parameter
WRITE_BL_PARTIAL controlling the partial block write option) identical to the read operation (refer to
Figure “Single Block Write Operation”). If a CRC error is detected it will be reported in the data-response
token and the data block will not be programmed.
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HB28H016/D032/B064/B128MM2
from from data from data new command
host card host response and from host
to card to host to card busy from
card
Data in command data block command
Data out response data_response busy
Single Block Write Operation
After a data block has been received, the card will respond with a data-response token. If the data block
has been received without errors, it will be programmed. As long as the card is busy programming, a
continuous stream of busy tokens will be sent to the host (effectively holding the DataOut line low).
In Multiple Block write operation the stop transmission will be done by sending ‘Stop Tran’ token instead
of ‘Start Block’ token at the beginning of the next block.
data
from from Start data from response and Stop
data from
host card Block host busy from Tran
host
to card to host Token to card card Token
to card
Data in command data block data block
Data out response data data busy

response busy response busy
Multiple Block Write Operation
Two types of multiple block write transactions, identical to the multiple block read, are defined (the host
can use either one at any time):
• Open-ended Multiple block write

The number of blocks for the write multiple block operation is not defined. The card will
continuously accept and program data blocks until a ‘Stop Tran’ token is received.
• Multiple block write with pre-defined block count
The card will accept the requested number of data blocks and terminate the transaction. ‘Stop Tran’
token is not required at the end of this type of multiple block write, unless terminated with an error.
In order to start a multiple block write with pre-defined block count, the host must use the
SET_BLOCK_COUNT command (CMD23) immediately preceding the
WRITE_MULTIPLE_BLOCK (CMD25) command. Otherwise the card will start an open-ended
multiple block write which can be stopped using the ‘Stop Tran’ token.
The host can abort writing at any time, within a multiple block operation, regardless of the its type.
Transaction abort is done by sending the ‘Stop Tran’ token. If a multiple block write with predefined
block count is aborted, the data in the remaining blocks is not defined.
If the card detects a CRC error or a programming error (e.g. write protect violation, out of range, address
misalignment, internal error, etc.) during a multiple block write operation (both types) it will report the
Rev.5.0, Jan. 2003, page 57 of 88

HB28H016/D032/B064/B128MM2
failure in the data-response token and ignore any further incoming data blocks. The host must than abort
the operation by sending the ‘Stop Tran’ token.
allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card shall detect the block
misalignment error before the beginning of the first misaligned block and respond with an error indication
in the dataresponse token and ignore any further incoming data blocks. The host must than abort the
operation by sending the ‘Stop Tran’ token.
Once the programming operation is completed, the host must check the results of the programming using
the SEND_STATUS command (CMD13). Some errors (e.g. address out of range, write protect violation
etc.) are detected during programming only. The only validation check performed on the data block and
communicated to the host via the data-response token is the CRC.
If the host sends a ‘Stop Tran’ token after the card received the last block of a multiple block operation
with pre-defined number of blocks, it will be responded to as the beginning of an illegal command and
responded accordingly.
While the card is busy, resetting the CS signal will not terminate the programming process. The card will
release the DataOut line (tri-state) and continue with programming. If the card is reselected before the
programming is finished, the DataOut line will be forced back to low and all commands will be rejected.
Resetting a card (using CMD0) will terminate any pending or active programming operation. This may
destroy the data formats on the card. It is in the responsibility of the host to prevent it.
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HB28H016/D032/B064/B128MM2
Erase and Write Protect Management
The erase and write protect management procedures in the SPI mode are identical to those of the
MultiMediaCard mode. While the card is erasing or changing the write protection bits of the predefined
sector list, it will be in a busy state and hold the DataOut line low. Figure “No Data Operations” illustrates
a ‘no data’ bus transaction with and without busy signaling.
from from from from

host card host card
to card to host to card to host
Data out response response busy
‘No Data’ Operations
Reading CID/CSD Registers
Unlike the MultiMediaCard protocol (where the register contents are sent as a command response), reading
the contents of the CSD and CID registers in SPI mode is a simple read-block transaction. The card will
respond with a standard response token (refer to Figure “Read Operation”) followed by a data block of 16
bytes suffixed with a 16-bit CRC. The data timeout for the CSD command cannot be set to the card TAAC
since this value is stored in the CSD. Therefore the standard response timeout value (NCR) is used for read
latency of the CSD register.
Reset Sequence
The MultiMediaCard requires a defined reset sequence. After power on reset or CMD0 (software reset) the
card enters an idle state. At this state the only legal host command is CMD1 (SEND_OP_COND) and
CMD58 (READ_OCR). In SPI mode, as opposed to MultiMediaCard mode, CMD1 has no operands and
does not return the contents of the OCR register. Instead, the host may use CMD58 (available in SPI mode
only) to read the OCR register. Furthermore, it is in the responsibility of the host to refrain from accessing
cards that do not support its voltage range. The usage of CMD58 is not restricted to the initializing phase
only, but can be issued at any time. The host must poll the card (by repeatedly sending CMD1) until the
‘in-idle-state’ bit in the card response indicates (by being set to 0) that the card completed its initialization
processes and is ready for the next command. The host must poll the card (by repeatedly sending CMD1)
until the ‘in-idle-state’ bit in the card response indicates (by being set to 0) that the card completed its
initialization processes and is ready for the next command.
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HB28H016/D032/B064/B128MM2
Error Conditions
Unlike the MultiMediaCard protocol, in the SPI mode the card will always respond to a command. The
response indicates acceptance or rejection of the command. A command may be rejected if it is not
supported (illegal opcode), if the CRC check failed, if it contained an illegal operand, or if it was out of
sequence during an erase sequence.
Memory Array Partitioning
Same as for MultiMediaCard mode.
Card Lock/Unlock
Usage of card lock and unlock commands in SPI mode is identical to MultiMediaCard mode. In both cases
the command response is of type R1b. After the busy signal clears, the host should obtain the result of the
operation by issuing a GET_STATUS command. Please refer to Chapter “Card lock/unlock operation” for
details.
Commands
All the MultiMediaCard commands are 6 bytes long. The command transmission always starts with the
left bit of the bitstring corresponding to the command codeword. All commands are protected by a CRC7.
The commands and arguments are listed in Table
Bit position [47] [46] [45:40] [39:8] [7:1] [0]

Width (bits) 1 1 6 32 7 1
Value ‘0’ ‘1’ × × × ‘1’
Description start bit transmission bit command index argument CRC7 end bit
The following table provides a detailed description of the SPI bus commands. The responses are defined in
Chapter “Responses”. The Table “Commands and Arguments” lists all MultiMediaCard commands. A
“yes” in the SPI mode colon indicates that the command is supported in SPI mode. With these restrictions,
the command class description in the CSD is still valid. If a command does not require an argument, the
value of this field should be set to zero. The reserved commands are reserved in MultiMediaCard mode as
well. The binary code of a command is defined by the mnemonic symbol. As an example, the content of
the command index field is (binary) ‘000000’ for CMD0 and ‘100111’ for CMD39.
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HB28H016/D032/B064/B128MM2
Commands and Arguments
CMD index SPI mode Argument Resp Abbreviation Command description

CMD0 Yes None R1 GO_IDLE_STATE resets the MultiMediaCard
CMD1 Yes None R1 SEND_OP_COND Activates the card’s initialization
process.
CMD2 No
CMD3 No
CMD4 No
CMD5 reversed
CMD6 reversed
CMD7 No
CMD8 reversed
CMD9 Yes None R1 SEND_CSD asks the selected card to send its
card-specific data (CSD)
CMD10 Yes None R1 SEND_CID asks the selected card to send its
card identification (CID)
CMD11 No
CMD12 Yes None R1 STOP_TRANSMIS stop transmission on multiple read
SION
CMD13 Yes None R2 SEND_STATUS asks the selected card to send its
status register.
CMD14 reversed
CMD15 No
CMD16 Yes [31:0] block length R1 SET_BLOCKLEN selects a block length (in bytes) for
all following block-oriented read
1
commands and lock card comand.*
CMD17 Yes [31:0] data R1 READ_SINGLE_ reads a block of the size selected by
2
address BLOCK the SET_BLOCKLEN command.*
CMD18 Yes [31:0] data R1 READ_MULTIPLE continuously transfers data block
address _BLOCK from card to host until interrupted by
a stop command or the requested
number of data blocks transmitted.
CMD19 reversed
CMD20 No
CMD21... reversed
CMD22
CMD23 Yes [31:16] set to 0 R1 SET_BLOCK_CO defines the number of blocks which
[15:0] number of UNT are going to be transferred in the
blocks immediately succeeding multiple
block read or write command.
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HB28H016/D032/B064/B128MM2
CMD24 Yes [31:0] data R1 WRITE_BLOCK Writes a block. The write-block-length of
address the Hitachi MultiMediaCard is permanently
4
assigned to the value 512 bytes.*
CMD25 Yes [31:0] data R1 WRITE_MULTIPL continuously writes blocks of data until a
address E_BLOCK “Stop Tran” token or the requested
number of block received.
CMD26 No
CMD27 Yes None R1 PROGRAM_CSD programming of the programmable bits of
the CSD.
3
CMD28 Yes [31:0] data R1b* SET_WRITE_ if the card has write protection features,
address PROT this command sets the write protection bit
of the addressed group. The properties of
write protection are coded in the card
specific data (WP_GRP_SIZE).
CMD29 Yes [31:0] data R1b CLR_WRITE_ if the card has write protection features,
address PROT this command clears the write protection
bit of the addressed group.
CMD30 Yes [31:0] write R1 SEND_WRITE_ if the card has write protection features,
protect data PROT this command asks the card to send the
5
address status of the write protection bits.*
CMD31 reserved
CMD32 Yes [31:0] data R1 TAG_SECTOR_ sets the address of the first sector of the
6
address START erase group.*
CMD33 Yes [31:0] data R1 TAG_SECTOR_ sets the address of the last sector in a
address END continuous range within the selected
erase group, or the address of a single
6
sector to be selected for erase.*
CMD34 Yes [31:0] data R1 UNTAG_SECTOR removes one previously selected sector
6
address from the erase selection.*
CMD35 Yes [31:0] data R1 TAG_ERASE_ sets the address of the first erase group
address GROUP_START within a range to be selected for erase
CMD36 Yes [31:0] data R1 TAG_ERASE_ sets the address of the last erase group
address GROUP_END within a continuous range to be selected
for erase
CMD37 Yes [31:0] data R1 UNTAG_ERASE_ removes one previously selected erase
6
address GROUP group from the erase selection*
CMD38 Yes [31:0] stuff R1b ERASE erases all previously selected sectors
bits
CMD39 No
CMD40 No
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HB28H016/D032/B064/B128MM2
CMD41 reserved
CMD42 Yes [31:0] stuff bits R1 LOCK/UNLOCK Used to set/reset the password or
lock/unlock the card. The structure
of the data block is described in
chapter “Card lock/unlock
operation”. The size of the Data
Block is defined by the
SET_BLOCK_LEN command.
CMD43... reserved
CMD54
CMD55 (Yes) [31:16] RCA R1 APP_CMD Indicates to the card that the next
[15:0] stuff bits command is an application specific
command rather than a standard
command.
CMD56 (Yes) [31:1] stuff bits R1b GEN_CND Used either to transfer a data block
7
[0:0] RD/WR* to the card or to get a data block
from the card for general purpose /
application specific commands. The
size of the data block shall be set by
the SET_GLOCK_LEN command.
CMD57 reserved
CMD58 Yes None R3 READ_OCR Reads the OCR register of a card.
CMD59 Yes [31:1] stuff bits R1 CRC_ON_OFF Turns the CRC option on or off. A
[0:0] CRC option ‘1’ in the CRC option bit will turn the
option on, a ‘0’ will turn it off
CMD60 No
Notes: 1. The default block length is as specified in the CSD. These Hitachi MultiMediaCards do not
support partial block write, so the write block size defined by WRITE_BLK_LEN is permanentry
assigned to the value 512 bytes.
2. The data transferred must not cross a physical block boundary unless READ_BLK_MISALIGN is
set in the CSD. These Hitachi MultiMediaCards do not support read block operations with
bondary crossing (READ_BLK_MISALIGN = ‘0’), so the data transferred must not cross a
3. R1b: R1 response with an optional trailing busy signal.
4. The data transferred must not cross a physical block boundary unless WRITE_BLK_MISALIGN
is set in the CSD. These Hitachi MultiMediaCards do not support write block operations with
boundary crossing (WRITE_BLK_MISALIGN = ‘0’), so the data transferred must not cross a
5. 32 write protection bits (representing 32 write protect groups starting at the specified address)
followed by 16 CRC bits are transferred in a payload format via the data line. The last (least
significant) bit of the protection bits corresponds to the first addressed group. If the addresses of
the last groups are outside the valid range, then the corresponding write protection bits shall be
set to zero.
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HB28H016/D032/B064/B128MM2
6. “MultiMediaCard system specification Version 3.1” does not support these commands, but these
Hitachi MultiMediaCards support them to keep backward compatibility with former
MultiMediaCard series.
7. ‘1’ the host gets a block of data from the card.
‘0’ the host sends block of data to the card.
Responses
There are several types of response tokens. As in the MultiMediaCard mode, all are transmitted MSB first:
• Format R1
This response token is sent by the card after every command with the exception of SEND_STATUS
commands. It is one byte long, and the MSB is always set to zero. The other bits are error indications, an
error being signaled by a ‘1’. The structure of the R1 format is given in Figure “R1 Response Format”.
The meaning of the flags is defined as following:
• In idle state: The card is in idle state and running the initializing process.
• Erase reset: An erase sequence was cleared before executing because an out of erase sequence
command was received.
• Illegal command: An illegal command code was detected.
• Communication CRC error: The CRC check of the last command failed.
• Erase sequence error: An error in the sequence of erase commands occurred.
• Address error: A misaligned address, which did not match the block length, was used in the
command.
• Parameter error: The command’s argument (e.g. address, block length) was out of the
allowed range for this card.
7 0
0
in idle state
erase reset
illegal command
com crc error
erase sequence error
address error
parameter error
R1 Response Format
• Format R1b
This response token is identical to the R1 format with the optional addition of the busy signal. The busy
signal token can be any number of bytes. A zero value indicates card is busy. A non-zero value indicates
the card is ready for the next command.
Rev.5.0, Jan. 2003, page 64 of 88

HB28H016/D032/B064/B128MM2
• Format R2
This response token is two bytes long and sent as a response to the SEND_STATUS command. The
format is given in Figure “R2 Response Format”.
1. Byte 2. Byte
7 0 7 0
0
card is locked
wp erase skip | lock/unlock command failed
error
CC error
card ecc failed
wp violation
erase param
out of range | csd_overwrite
in idle state
erase reset
illegal command
com crc error
erase sequence error
address error
parameter error
R2 Response Format
The first byte is identical to the response R1. The content of the second byte is described in the following:
• Out of range  csd_overwrite: This status bit has two functions. It is set if the command
argument was out of its valid range or if the host is trying to change the ROM section or reverse
the copy bit (set as original) or permanent WP bit (un-protect) of the CSD register.
• Erase param: An invalid selection, sectors or groups, for erase.
• Write protect violation: The command tried to write a write protected block.
• Card ECC failed: Card internal ECC was applied but failed to correct the data.
• CC error: Internal card controller error
• Error: A general or an unknown error occurred during the operation.
• Write protect erase skip | lock/unlock command failed: This status bit has two functions
overloaded. It is set when the host attempts to erase a write protected sector or if a sequence or
password error occurred during card lock/unlock operation.
• Card is locked: Set when the card is locked by the user. Reset when it is unlocked.
Rev.5.0, Jan. 2003, page 65 of 88

HB28H016/D032/B064/B128MM2
• Format R3
This response token is sent by the card when a READ_OCR command is received. The response length is
5 bytes (refer to Figure “R3 Response Format”). The structure of the first (MSB) byte is identical to
response type R1. The other four bytes contain the OCR register.
39 32 31 0
0 0
R1 OCR
R3 Response Format
• Data Response
Every data block written to the card will be acknowledged by a data response token. It is one byte long
and has the following format:
7 0
× × × 0 status 1
Data Response
The meaning of the status bits is defined as follows:
“010” - Data accepted.

“101” - Data rejected due to a CRC error.
“110” - Data rejected due to a Write error.
Data Tokens
Read and write commands have data transfers associated with them. Data is being transmitted or received
via data tokens. All data bytes are transmitted MSB first. Data tokens are 4 to 2051 bytes long and have
the following format:
• First byte: Start Byte

Token Type Transaction Type 7 Bit Position 0
Start Block Single Block Read 1 1 1 1 1 1 1 0
Start Block Multiple Block Read 1 1 1 1 1 1 1 0
Start Block Single Block Write 1 1 1 1 1 1 1 0
Start Block Multiple Block Write 1 1 1 1 1 1 0 0
Stop Tran Multiple Block Write 1 1 1 1 1 1 0 1
Format of the Start Data Block Tokens
• Bytes 2-2049 (depends on the data block length): User data

• Last two bytes: 16-bit CRC.
Rev.5.0, Jan. 2003, page 66 of 88

HB28H016/D032/B064/B128MM2
Data Error Token
If a read operation fails and the card cannot provide the required data, it will send a data error token
instead. This token is one byte long and has the following format:
7 0
0 0 0
Error
CC Error
Card ECC failed
out of range
Card is locked
Data Error Token
The 4 least significant bits (LSB) are the same error bits as in the response format R2.
Rev.5.0, Jan. 2003, page 67 of 88

HB28H016/D032/B064/B128MM2
Clearing Status Bits
As described in the previous paragraphs, in SPI mode, status bits are reported to the host in three different
formats: response R1, response R2 and data error token (the same bits may exist in multiple response
types— e.g Card ECC failed).
As in the MultiMediaCard mode, error bits are cleared when read by the host, regardless of the response
format. State indicators are either cleared by reading or in accordance with the card state. All Error/Status
bits defined in MultiMediaCard mode, with the exception of underrun and overrun, have the same meaning
and usage in SPI mode. The following table summarizes the set and clear conditions for the various status
bits:
• Type:
• E: Error bit.
• S: Status bit.
• R: Detected and set for the actual command response.
• X: Detected and set during command execution. The host must poll the card by sending status
command in order to read these bits.
• Clear Condition:
• A: According to the card state.
• C: Clear by read.
SPI mode Status bits
Included Clear
Identifier in resp Type Value Description condition
Out of range R2 ERX ’0’= no error The command argument was out of C
DataErr ’1’= error allowed range for these Hitachi
MultiMediaCards.
Address error R1 R2 ERX ’0’= no error An address which did not match the C
’1’= error block length was used in the
command.
Erase sequence R1 R2 ER ’0’= no error An error in the sequence of erase C
error ’1’= error command sequence.
Error param R2 EX ’0’= no error An error in the parameters of the C
’1’= error erase command sequence.
Parameter error R1 R2 ERX ’0’= no error An error in the parameters of the C
’1’= error command.
WP violation R2 ERX ’0’= not protected Attempt to program a write protected C
’1’= protected block.
Com CRC error R1 R2 ER ’0’= no error The CRC check of the previous C
’1’= error command failed.
Rev.5.0, Jan. 2003, page 68 of 88

HB28H016/D032/B064/B128MM2
Included Clear
Identifier in resp Type Value Description condition
Illegal command R1 R2 ER ’0’= no error Command not legal for the card state C
’1’= error
Card ECC failed R2 EX ’0’= success Card internal ECC was applied but C
DataErr ’1’= failure failed to correct the data.
CC error R2 ERX ’0’= no error Internal card controller error C
DataErr ’1’= error
Error R2 ERX ’0’= no error A general or an unknown error C
DataErr ’1’= error occurred during the operation.
WP erase skip R2 SX ’0’= not protected Only partial address space was C
’1’= protected erased due to existing write protect
blocks.
Lock/Unlock R2 EX ’0’= no error Sequence or password error during C
command failed ’1’= error card lock/unlock operation
Card is locked R2 SX ’0’= card is not Card is locked by password. A
DataErr locked
’1’= card is locked
Erase reset R1 R2 SR ’0’= cleared An erase sequence was cleared C
’1’= set before executing because an output
of erase sequence command was
received.
In Idle state R1 R2 SR ’0’= Card is ready The card enters the Idle state after A
’1’= Card is in Idle power up or reset command. It will
state exit this state and become ready upon
completion of this initialization
procedures.
CSD overwrite R2 EX ’0’= no error The host is trying to change the ROM C
’1’= error section, or is trying to reverse the
copy bit (set as original) or permanent
WP bit (unprotected) or he CSD
register.
Rev.5.0, Jan. 2003, page 69 of 88

HB28H016/D032/B064/B128MM2
SPI Bus Timing
All timing diagrams use the following schematics and abbreviations:
H: Signal is high (logical ‘1’)
L: Signal is low (logical ‘0’)
X: Don’t care
Z: High impedance state (-> = 1)
*: Repeater
Busy: Busy Token
Command: Command token
Response: Response token
Data block: Data token
All timing values are defined in Table “Timing Values”. The host must keep the clock running for at least
NCR clock cycles after receiving the card response. This restriction applies to both command and data
response tokens.
Command/Response
• Host Command to Card Response - Card is ready
CS H H L L L ****************** L L L L H H H
NCS NEC
Datain X X H H H H 6 bytes command H H H H H ******* H H H H X X X
NCR
Dataout Z Z Z H H H H ******* H H H H H 1 or 2 bytes response H H H H H Z Z
• Host Command to Card Response - Card is busy
CS H L L L ****************** L L L L H H H L L L L L L H H
NCS NEC NDS NEC
Datain X H H H H 6 bytes command H H H H H H H H H H H H H X X X H H H H H H X X
NCR
Dataout Z Z H H H H ******* H H H H card response busy L Z Z Z busy H H H H Z
Rev.5.0, Jan. 2003, page 70 of 88

HB28H016/D032/B064/B128MM2
• Card Response to Host Command
CS L L L L L ****************** L L H H H
Datain H H H H H H ********* H H H H 6 Bytes command H H H H X X X
NRC
Dataout H H H H H 1 or 2 bytes response H H H H ************* H H H H H Z Z
• Single Block Read
CS H L L L ****************** L L L L H H H
NCS NEC
Datain X H H H H Read command H H H H H ********** H H H X X X
NCR NAC
Dataout Z Z H H H H ******* H H H H Card response H H H H Data block H H Z Z
• Multiple Block Read – Stop Transmission is sent between blocks
CS H L L ****************** L L L L L
NCS
Datain X H * * H Read Cmd H H H H ********** H H Stop Cmd H H H H H H H
NCR NAC NAC NCR
Dataout Z Z H H H **** H * * H Card Resp H * * H Data block H * * H Data block H H * * H Card Resp
• Multiple Block Read – Stop Transmission is sent within a block
CS H L L ****************** L L L L L
NCS
Datain X H * * H Read Cmd H H H H ********** H H H Stop Cmd H H H H H H H H H H
NCR NAC NAC NCR
Dataout Z Z H H H **** H * * H Card Resp H * * H Data block H * * H Data X X H * * H Card Resp
• Reading The CSD Register
CS H L L L ****************** L L L H H H H
NCS NEC
Datain X H H H H read command H H H H H ******* H H H X X X X
NCR NCX
Dataout Z Z H H H H ******* H H H H card response H H H H data block H H H H Z Z Z
Rev.5.0, Jan. 2003, page 71 of 88

HB28H016/D032/B064/B128MM2
• Single Block Write
CS H L ****************** L L L L L L L L H H H L L L L
NCS NWR NEC NDS
Datain X H ** H Write command H H H H H H H H ** H Data block H H H H ** H X ** X H H H H
NCR
Dataout Card Data
Z Z H H H ******* H ** H response H H H H H H H resp Busy L Z Z Z Busy H
• Multiple Block Write
CS L ****************** L L L L L L L L L L L L L L L L L L L L
NWR NWR
Datain H Data Block H H H H H H H H * * H Data Block H H H H H H H H * * H Stop Tran H H H H H

NBR
Dataout
H H H H H Data Resp Busy H H H H H H H Data Resp Busy H H H H H H X * * X Busy
Timing Values
Symbol Min Max Unit

NCS 0 — 8 clock cycles
NCR 1 8 8 clock cycles
NCx 0 8 8 clock cycles
NRC 1 — 8 clock cycles
1
NAC 1 spec. in the CSD* 8 clock cycles
NWR 1 — 8 clock cycles
NEC 0 — 8 clock cycles
NDS 0 — 8 clock cycles
NBR 1 1 8 clock cycles
Note: 1. Refer to Chapter “Time-out Condition”.
Rev.5.0, Jan. 2003, page 72 of 88

HB28H016/D032/B064/B128MM2
Error Handling
MultiMediaCards are defined as error free devices or as devices with a defined maximum bit error rate
(with external error correction circuitry). To correct defects in the memory field of the cards the system
may include error correction codes in the payload data (ECC). This correction is intended to correct static
errors. Additionally two methods of detecting errors generated during the data transfer (dynamic errors)
via a cyclic redundancy check (CRC) are implemented.
On Card Error Correction Code (ECC)
These Hitachi MultiMediaCards is free of static errors. All errors are covered inside the card, even errors
occurring during the lifetime of these Hitachi MultiMediaCards are covered for the user. The only effect
which may be notified by the end user is, that the overall memory capacity may be reduced by small
number of blocks. All flash handling is done on card, so that no external error correction is needed.
Rev.5.0, Jan. 2003, page 73 of 88

HB28H016/D032/B064/B128MM2
Cyclic Redundancy Check (CRC)
The CRC is intended for protecting MultiMediaCard commands, responses and data transfer against
transmission errors on the MultiMediaCard bus. One CRC is generated for every command and checked
for every response on the CMD line. For data blocks one CRC per transferred block is generated. The
CRC is generated and checked as described in the following.
• CRC7
The CRC7 check is used for all commands, for all responses except type R3, and for the CSD and CID
registers. The CRC7 is a 7-bit value and is computed as follows:
7 3
generator polynomial: G(x) = x + x + 1
n n-1 0
M(x) = (first bit) * x + (second bit) * x +...+ (last bit) * x
7
CRC[6...0] = Remainder [(M(x) * x )/G(x)]
All CRC registers are initialized to zero. The first bit is the most left bit of the corresponding bitstring (of
the command, response, CID or CSD). The degree n of the polynomial is the number of CRC protected
bits decreased by one. The number of bits to be protected is 40 for commands and responses (n = 39), and
120 for the CSD and CID (n = 119).
• CRC16
The CRC16 is used for payload protection in block transfer mode. The CRC check sum is a 16-bit value
and is computed as follows:
16 12 5
generator polynomial: G(x) = x + x +x + 1,
n n-1 0
M(x) = (first bit) * x + (second bit) * x +...+ (last bit) * x
16
CRC[15...0] = Remainder [(M(x) * x ) / G(x)]
All CRC registers are initialized to zero. The first bit is the first data bit of the corresponding block. The
degree n of the polynomial denotes the number of bits of the data block decreased by one (e.g. n = 4095 for
a block length of 512 bytes). The generator polynomial G(x) is a standard CCITT polynomial. The code
has a minimal distance d=4 and is used for a payload length of up to 2048 Bytes (n <= 16383).
Rev.5.0, Jan. 2003, page 74 of 88

HB28H016/D032/B064/B128MM2
Power Supply
Power Supply Decoupling
The VSS1, VSS2 and VCC lines supply the card with operating voltage. For this, decoupling capacitors for
buffering current peak are used. These capacitors are placed on the bus side corresponding to Figure
“Power Supply Decoupling”.
Lmax = 13 mm single card slot
VSS1
C MultiMediaCard
VCC
VSS2
single card slot
C = 0.1 µF
Power Supply Decoupling
The host controller includes a central buffer capacitor for VCC. Its value is Cbuf = 1µF/slot
Rev.5.0, Jan. 2003, page 75 of 88

HB28H016/D032/B064/B128MM2
Power on
Each card has its own power on detection circuitry which puts the card into a defined state after the power-
on. No explicit reset signal is necessary. The cards can also be reset by a special software command:
GO_IDLE_STATE (CMD0). In case of emergency the host may also reset the cards by switching the
power supply off and on again.
CLK CMD DAT
VCC
Power up ASYNC.RESET command ENABLE core memory
detection parser controller core
VSS
MultiMediaCard controller
Power on Detection
A power on reset is generated on chip as long as VCC is below a certain limit. After this reset the command
parser of these Hitachi MultiMediaCards works properly but the access to the memory core is not
guaranteed. So in the power up phase (or when these Hitachi MultiMediaCards are inserted during power
up) the host has to wait after sending SEND_OP_COND (CMD1) for the identification delay before the
ALL_SEND_CID (CMD2) can be interpreted by the card:
Rev.5.0, Jan. 2003, page 76 of 88

HB28H016/D032/B064/B128MM2
3.6 V
Bus master supply voltage Memory field

working voltage
Card logic working
range
2.7 V voltage range
2.0 V
Time
Power up time Supply ramp up time
NCC NCC NCC

Initialization sequence CMD1 CMD1 CMD1 CMD2
Optional repetitions of CMD1

Initialization delay: The maximum of until no cards are responding
1 msec, 74 clock cycles and supply with busy bit set.
ramp up time
Power-up Diagram
• After power up (including hot insertion, i.e. inserting a card when the bus is operating) the
MultiMediaCard enters the idle state. During this state the MultiMediaCard ignores all bus transactions
until CMD1 is received.
• CMD1 is a special synchronization command used to negotiate the operation voltage range and to poll
the cards until they are out of their power-up sequence. Besides the operation voltage pro-file of the
cards, the response to CMD1 contains a busy flag, indicating that the card is still working on its power-
up procedure and is not ready for identification. This bit informs the host that at least one card is not
ready. The host has to wait (and continue to poll the cards) until this bit is cleared.
• Getting individual cards, as well as the whole MultiMediaCard system, out of idle state is up to the
responsibility of the bus master. Since the power up time and the supply ramp up time depend on
application parameters such as the maximum number of MultiMediaCards, the bus length and the
power supply unit, the host must ensure that the power is built up to the operating level (the same level
which will be specified in CMD1) before CMD1 is transmitted.
• After power up the host starts the clock and sends the initializing sequence on the CMD line. This
sequence is a contiguous stream of logical ‘1’s. The sequence length is the maximum of 1 msec, 74
clocks or the supply-ramp-up-time; The additional 10 clocks (over the 64 clocks after what the card
should be ready for communication) are provided to eliminate power-up synchronization problems.
Rev.5.0, Jan. 2003, page 77 of 88

HB28H016/D032/B064/B128MM2
Short Cut Protection
The MultiMediaCards can be inserted/removed into/from the bus without damage. If the card
insertion/removal is occured during card operation (read/write), the data in the MultiMediaCard would be
broken. If one of the supply pins (VCC or VSS) is not connected properly, then the current is drawn through
a data line to supply the card. Naturally the card can not operate properly under this conditions.
VCC
VCC not connected

card
CMD, DAT controller
VSS not connected
VSS
Improper Power Supply
Every MultiMediaCard output withstands shortcuts to either supply.
VCC
Ishort
worst case shortcut
card
CMD, DAT controller
Ishort
VSS
connector
Short Cut Protection
Rev.5.0, Jan. 2003, page 78 of 88

HB28H016/D032/B064/B128MM2
Characteristics
This chapter defines following characteristics:
• Temperature characteristics
• Electrical characteristics
Temperature Characteristics
Parameter Symbol Min Max Unit

Storage temperature Tstg –40 85 ºC
Operating temperature Topr –25 85 ºC
Junction temperature Tj –20 95 ºC
Electrical Characteristics
In this chapter the electrical characteristics for these Hitachi MultiMediaCards are defined in three steps:
• Pad characteristics: properties of the external connectors

• Absolute maximum ratings: if exceeded the card may be damaged
• Recommended operating conditions: characterization model of the environment of these Hitachi
MultiMediaCards, requirements for the operating characteristics
• Operating characteristics: properties of these Hitachi MultiMediaCards measurable if the
recommended operating conditions are considered
Pad Characteristics
Parameter Symbol Min Typ Max Unit

Input capacitance CCARD 7 pF
Rev.5.0, Jan. 2003, page 79 of 88

HB28H016/D032/B064/B128MM2
Absolute Maximum Ratings

Absolute maximum ratings are those values beyond which damage to the device may occur. Functional
operation under these conditions or at any other condition beyond those indicated in the operational
sections of this specification is not implied:
Parameter Symbol Min Max Unit Remark

Supply voltage VCC –0.5 4.6 V
Total power dissipation Pd 288 mW
ESD Contact Pads –4 4 kV Human body model
protection according to ANSI/EOS
ESD-S5.1-1998
Non Contact Pads –8 8 kV Human body model
coupling plane discharge according to IEC61000-4-
2
Non Contact Pads –15 15 kV
air discharge
Inputs Input voltage VImax –0.5 VCC + 0.5 V • max (VCC)
Outputs Output voltage VOmax –0.5 VCC + 0.5 V • max (VCC)
High-level output current IOHmax –100 mA short cut protected
Low-level output current IOLmax 150 mA short cut protected
Bus Signal Line Load
The total capacitance CL of each line of the MultiMediaCard bus is the sum of the bus master capacitance
CHOST, the bus capacitance CBUS itself and the capacitance CCARD of each card connected to this line:
CL = CHOST + CBUS + N*CCARD
where N is the number of connected cards. Requiring the sum of the host and bus capacitance’s not to
exceed 30 pF for up to 10 cards, and 40 pF for up to 30 cards, the following values must not be exceeded:
Parameter Symbol Min Max Unit Remark

Pull-up resistance for CMD RCMD 4.7 100 kΩ to prevent bus floating
Pull-up resistance for DAT RDAT 50 100 kΩ to prevent bus floating
Bus signal line capacitance CL — 250 pF fPP ≤ 5 MHz,
30 cards
Bus signal line capacitance CL — 100 pF fPP ≤ 20 MHz,
10 cards
Maximum signal line inductance — 16 nH fPP ≤ 20 MHz
Note: 1. The value of pull-up resistance should be optimized according to the host system.
Rev.5.0, Jan. 2003, page 80 of 88

HB28H016/D032/B064/B128MM2
Recommended Operating Conditions
The recommended operating conditions define the parameter ranges for optimal performance and
durability of these Hitachi MultiMediaCards.
Parameter Symbol Min Typ Max Unit Remark

Supply voltage VCC 2.7 3.0 3.6 V
Inputs Low-level input voltage VIL VSS – 0.3 0.25VCC V
High-level input voltage VIH 0.625VCC VCC + 0.3 V
Outputs High-level output IOH –2 mA
current
Low-level output IOL 6 mA
current
Clock Clock frequency data fPP 0 20 MHz CL < 100 pF
1
input clk* transfer mode (pp) (10 cards)
Clock frequency ident. fOD 0 400 kHz
mode (od)
Clock cycle time data tPP = 1/fPP 50 ns
transfer mode (pp)
Clock cycle time ident. tOD = 1/fOD 2.5 µs
mode (od)
Clock low time tWL 10 ns CL < 100 pF
(10 cards)
Clock high time tWH 10 ns CL < 100 pF
(10 cards)
Clock input rise time tLH 10 ns CL < 100 pF
(10 cards)
Clock input fall time tHL 10 ns CL < 100 pF
(10 cards)
Clock low time tWL 50 ns CL < 250 pF
(30 cards)
Clock high time tWH 50 ns CL < 250 pF
(30 cards)
Clock input rise time tLH 50 ns CL < 250 pF
(30 cards)
Clock input fall time tHL 50 ns CL < 250 pF
(30 cards)
Note: 1. All values are referred to min (VIH) and max (VIL).
Rev.5.0, Jan. 2003, page 81 of 88

HB28H016/D032/B064/B128MM2
Operating Characteristics
The operating characteristics are parameters measured in a MultiMediaCard system assuming the
recommended operating conditions (refer to Chapter “Recommended Operating Conditions”).
Parameter Symbol Min Typ Max Unit Remark

High speed supply HB28H016MM2 60 mA at 20 MHz, 3.6 V
current
HB28D032MM2 60 mA
HB28B064MM2 60 mA
HB28B128MM2 80 mA
Minimal supply HB28H016MM2 100 µA at 0 Hz, 3.6 V stby
current state
HB28D032MM2 100 µA
HB28B064MM2 100 µA
HB28B128MM2 150 µA
Typical supply Single Block Read 20 mA at 20 MHz, 3.0 V
current 25ºC
Single Block Write 35 mA at 20 MHz, 3.0 V
25ºC
All digital inputs Input leakage current –10 10 µA
(Including I/O
current)
All outputs High-level output VOH 0.75VCC V at min IOH
voltage
Low-level output VOL 0.125 V at max IOL
voltage VCC
Inputs: CMD, DAT Input set-up time tISU 3 ns
(Referred to CLK),
DI (Referred to
SCLK), CS
Input hold time tIH 3 ns
Outputs: CMD, Output set-up time tOSU 5 ns
DAT (Referred to
CLK), DO
(Referred to
SCLK)
Output hold time tOH 5 ns at tLH = 10 ns
Rev.5.0, Jan. 2003, page 82 of 88

;;
CMD
DAT
Clock
Input
Output
; ;; Valid data
: Invalid
command frame
tIH
tOH
tWH
tPP
HB28H016/D032/B064/B128MM2
tHL
Timing Diagram of Data Input and Output
The access time (tAT) is divided into two parts:

tWL
• TAAD: The asynchronous access time to read a byte out of the memory field.
with TSAD = NSAD/fPP
TSAD
tAT
Access Time
TAAD
tISU
Valid data
tOSU
tLH
Valid data
• TSAD: The synchronous access time. This time defines the time of the maximum number of cycles
which are required to access a byte of the memory field.
The synchronous part of the access time is sum of the command frame length and some additional internal
cycles (NSAD = 16 cycles). At 20 MHz one cycle is 50 ns (1/fPP), multiplied with NSAD the resulting frame
time is TSAD = 0.8 µs. The asynchronous access delay of these Hitachi MultiMediaCards is TAAD = 300 µs
maximum. The resulting memory access time tAT is the sum of both parts:
tAT = TAAD + TSAD
response frame
data
VIH
VIL
VIH
VIL
VOH
VOL
Rev.5.0, Jan. 2003, page 83 of 88

HB28H016/D032/B064/B128MM2
Access Time
Parameter Symbol Typ Max Unit Remark

Synchronous access delay cycles NSAD — 16 cycles
Synchronous access delay TSAD — 0.8 µs at 20 MHz clock frequency
Asynchronous access delay TAAD 300 — µs
1
Memory access time tAT 300.8 —* µs at 20 MHz clock frequency
Note: 1. Refer to Chapter “Time-out Condition”.
In the CSD are two fields to code the asynchronous and the synchronous access delay time:
• TAAC, asynchronous access delay

• NSAC, maximum number of cycles for receiving and interpreting of a command frame
The value for the CSD field NSAC is calculated from NSAD (maximum: 16 cycles) by division with 100
and rounding up to the next integer:
NSAC = [NSAD/100] = [16/100]
• NSAC = 0x01
The value for the CSD field TAAC is 1 ms:
TAAC = [TAAD] = 1 ms
• TAAC = 0x0E
For more details on NSAC and TAAC CSD-entries refer to Chapter “Card Specific Data (CSD)”.
References
[1] The MultiMediaCard, System Specification 3.1, MultiMediaCard Association
Number Representations
• decimal numbers: 1234, no special characters
• hexadecimal numbers: 0xAB, leading 0x, each digit represents 4 bits.
• binary numbers (single bit): ‘0’.
• binary number (unsigned bit vector): “100100”.
• 1k is equal to 1024.
• 1M is equal to 1k * 1k, except the card capacity. In the card capacity, 1M is equal to 10 (“Features”
6
and “Card Specific Data”).

• 1G is equal to 1M * 1k
Rev.5.0, Jan. 2003, page 84 of 88

HB28H016/D032/B064/B128MM2
Abbreviations and Terms
Abbreviations Terms
<n> Argument of a command or data field.
CMD<n> MultiMediaCard bus command <n>. See Command.
PP Push Pull, output driver type with low impedance driver capability for 0 and 1.
OD Open Drain, output driver type with low impedance driver capability for 0 and high
impedance driver capability for 1.
CSD Card specific data, MultiMediaCard register to store operating parameters.
CID Card identification data, MultiMediaCard register for the card initialization procedure.
RCA Relative card address, MultiMediaCard register which contains the current card
address of an initialized MultiMediaCard.
OCR Operation condition register, MultiMediaCard register that contains the voltage window
which is supported by the MultiMediaCard.
DSR Driver stage register, control register for the programmable driver stage driver (PDS).
PDS Programmable driver stage driver, is a tri-state output driver which has is
programmable to adapt the driver capabilities to the bus design.
Command A command send from the MultiMediaCard host to one or more MultiMediaCard cards
Response A response is always sent from the card to the host. It is always initiated by a
command (Remark: not all commands enforce responses).
Broadcast Com. A command may send as broadcast or as an addressed command. A broadcast
command is sent to all cards connected to the MultiMediaCard bus simultaneous.
Addressed Com. An addressed command is sent to exactly one selected MultiMediaCard. Normally an
addressed command forces a response of the card.
Point to point C. Same as addressed command
DAT The data (input)/output signal of the MultiMediaCard.
CLK The clk input signal of the MultiMediaCard.
CMD The command/response input/output of the MultiMediaCard.
VSS1,2 Ground contacts/lines of the MultiMediaCard.
VCC Supply voltage contact/line of the MultiMediaCard.
Memory core Array of memory cells in the core of the MultiMediaCard.
MultiMediaCard MultiMediaCard command interpreter module.
interface
MID Manufacturer Identifier.
Rev.5.0, Jan. 2003, page 85 of 88

HB28H016/D032/B064/B128MM2
Abbreviations Terms
CIN Card individual number.
CRC Cyclic redundancy check.
ECC Error correction code.
G(x) Generator polynomial of error correction/check code.
TAC Asynchronous access delay
NSAC Number of synchronous access cycles to be added to the access delay
fOD Open drain mode operating frequency (maximum 400kHz).
fPP Push pull mode operating frequency (maximum 20MHz).
MSB Most significant bit.
LSB Least significant bit.
Human Body Model Standard model to simulate electrical conditions induced by handling and touching of
electrical devices by humans.
Rev.5.0, Jan. 2003, page 86 of 88

HB28H016/D032/B064/B128MM2
Physical Outline
As of January, 2002
Unit: mm
Tolerance: 0.1 mm
Front
27.3
25.9
4.0 2.1
21.8
R02 Min. all around
Back
1.4
19.65 Min/20.60 Max
3.10 Max/2.75 Min
0.2
18.10 Max
15.60 Max
13.10 Max
10.60 Max
17.15 Min
14.65 Min
12.15 Min
8.10 Max
5.60 Max
9.65 Min
7.15 Min
4.65 Min
4.5 Min 3 × R1.0

1.2 Max
C7
24.00 ± 0.08
C6
C5
C4
C3
C2
C1
2 × R0.5
4.0
4.0
32.0
Rev.5.0, Jan. 2003, page 87 of 88

HB28H016/D032/B064/B128MM2
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL http://www.hitachisemiconductor.com/
For further information write to:

Hitachi Semiconductor Hitachi Europe Ltd. Hitachi Asia Ltd. Hitachi Asia (Hong Kong) Ltd.
(America) Inc. Electronic Components Group Hitachi Tower Group III (Electronic Components)
179 East Tasman Drive Whitebrook Park 16 Collyer Quay #20-00 7/F., North Tower
San Jose,CA 95134 Lower Cookham Road Singapore 049318 World Finance Centre,
Tel: <1> (408) 433-1990 Maidenhead Tel : <65>-6538-6533/6538-8577 Harbour City, Canton Road
Fax: <1>(408) 433-0223 Berkshire SL6 8YA, United Kingdom Fax : <65>-6538-6933/6538-3877 Tsim Sha Tsui, Kowloon Hong Kong
Tel: <44> (1628) 585000 URL : http://semiconductor.hitachi.com.sg Tel : <852>-2735-9218
Fax: <44> (1628) 585200 Fax : <852>-2730-0281
URL : http://semiconductor.hitachi.com.hk
Hitachi Europe GmbH Hitachi Asia Ltd.
Electronic Components Group (Taipei Branch Office)
Dornacher Straße 3 4/F, No. 167, Tun Hwa North Road
D-85622 Feldkirchen Hung-Kuo Building
Postfach 201, D-85619 Feldkirchen Taipei (105), Taiwan
Germany Tel : <886>-(2)-2718-3666
Tel: <49> (89) 9 9180-0 Fax : <886>-(2)-2718-8180
Fax: <49> (89) 9 29 30 00 Telex : 23222 HAS-TP
URL : http://www.hitachi.com.tw
Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 6.0
Rev.5.0, Jan. 2003, page 88 of 88

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Notes regarding these materials

Note: MultiMediaCard is a trademark of Infineon Technologies AG.

Rev.5.0, Jan. 2003, page 2 of 88

Power on reset unit

Flash control Core control

Rev.5.0, Jan. 2003, page 3 of 88

ROD RDAT RCMD

MultiMediaCard Mode Interface

Rev.5.0, Jan. 2003, page 4 of 88

MultiMediaCard interface controller

Memory core interface

MultiMediaCard Mode I/O-drivers

Rev.5.0, Jan. 2003, page 5 of 88

CS: Host to card Chip Select signal.

CLK: Host to card clock signal

Data in: Host to card data signal.

Data out: Card to host data signal.

SPI bus (CLK, Datain, Dataout)

SPI card SPI card

SPI Bus System

Rev.5.0, Jan. 2003, page 6 of 88

Name Width Type Description

Rev.5.0, Jan. 2003, page 7 of 88

Name Available in SPI mode Width (Bytes) Description

Rev.5.0, Jan. 2003, page 8 of 88

Operation Condition Register (OCR)

OCR slice Field Value Note

Rev.5.0, Jan. 2003, page 9 of 88

Card Identification (CID)

Name Field Width CID-slice Note

Relative Card Address (RCA)

Rev.5.0, Jan. 2003, page 10 of 88

Card Specific Data (CSD)

The CSD Fields

Name Field Width CSD-slice Value Type

Rev.5.0, Jan. 2003, page 11 of 88

CSD Register Structure

CSD_STRUCTURE CSD register structure

Rev.5.0, Jan. 2003, page 12 of 88

SPEC_VERS System specification version number

TAAC Access Time Definition

TAAC bit Description Values

Rev.5.0, Jan. 2003, page 13 of 88

Maximum Data Transfer Rate Definition

TRAN_SPEED bit Description Values

Supported Card Command Classes

CCC bit Supported card command classes

Rev.5.0, Jan. 2003, page 14 of 88

Data Block Length

READ_BLK_LEN Block length Remark

Rev.5.0, Jan. 2003, page 15 of 88

DSR_IMP DSR type

memory capacity = BLOCKNR*BLOCK_LEN

, (READ_BLK_LEN < 12)

Therefore, the maximal capacity which can be coded is 40965122048 = 4 GBytes.