Professional Documents
Culture Documents
Compal Confidential: Mobile Yonah uFCPGA With Intel Calistoga - P/GM+ATI M52-T + ICH7-M Core Logic Schematics Document
Compal Confidential: Mobile Yonah uFCPGA With Intel Calistoga - P/GM+ATI M52-T + ICH7-M Core Logic Schematics Document
Compal Confidential: Mobile Yonah uFCPGA With Intel Calistoga - P/GM+ATI M52-T + ICH7-M Core Logic Schematics Document
1 1
Compal confidential 2
Schematics Document
Mobile Yonah uFCPGA with Intel
Calistoga_P/GM+ATI M52-T + ICH7-M core logic
3
2006-04-28 3
REV:1.0
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 1 of 54
A B C D E
A B C D E
Compal confidential
File Name : LA-2951P
Caymus
1 64/128 MB VRAM Accelerometer
1
Fan Control
page 4
DDR1 Mobile Yonah/Merom Thermal Sensor Clock Generator LIS3LV02DQ
page 22
uFCPGA-478 CPU ADM1032AR ICS954306
page 30
page 4,5,6 page 4 page 15
FSB
H_A#(3..31) 533/667MHz H_D#(0..63)
ATI M52-T DDR2 -400/533/667 DDR2-SO-DIMM X2
BANK 0, 1, 2, 3 page 13,14
PCI-E x 16
page 19,20,21,22,23
Intel Calistoga MCH Dual Channel
945PM PCBGA 1466 USB conn x2
CRT / TV-OUT/DVI (Docking) page 38
page 7,8,9,10,11,12
page 16
FingerPrinter AES2501
2
USBx1 page 35 2
page 39
Page 41,42,43,44,45,46,47,48,49,50 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 2 of 54
A B C D E
5 4 3 2 1
Symbol Note :
Voltage Rails
Power Plane Description S0-S1 S3 S5
: means Digital Ground
D
B+ AC or battery power rail for power circuit N/A N/A N/A : means Analog Ground D
+1.5VS 1.5V switched power rail for PCI-E interface ON OFF OFF
@ : means just reserve , no build
+1.8V 1.8V power rail for DDRII ON ON OFF
M52@ : means build discrete sku with ATI VGA M52 .
+1.8VS 1.8V switched power rail ON OFF OFF
UMA@ : means build UMA sku with Intel 945GM .
SPI@ : means just build when SPI I/F BIOS function reserve.
+2.5VS 2.5V switched power rail for MCH video PLL ON OFF OFF FWH@ : means just build when FWH I/F BIOS function reserve.
+3VALW 3.3V always on power rail ON ON ON* NOXDP@ : means just build when XDP function disable.
+3VS 3.3V switched power rail ON OFF OFF XDP@ : means just build when XDP function enable. When this time, docking PCI express will not work.
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
1021@ : means just build when SMsC KBC1021 chip selected.
+RTC_VCC RTC power ON ON ON
LP@ : means just build when Low power clock gen. install
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
NOLP@ : means just build when Low power clock gen. NO install
C C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 3 of 54
5 4 3 2 1
5 4 3 2 1
ITPFLEX700 Connector
+3VS
<7> H_A#[3..31] H_D#[0..63] <7> +VCCP
JP12A
JP19
H_A#3 J4 E22 H_D#0 XDP_TDI 1 27 0.1U_0402_16V4Z XDP_DBRESET# 2 1
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2
XDP_TMS
XDP_TCK
2
TDI
TMS
VTT0
VTT1 28 1
C948
2 R243 @ 200_0402_1%
+VCCP
M3 A5# D2# E26 5 TCK VTAP 26
H_A#6 K5 H22 H_D#3 XDP_TDO_R 7
H_A#7 A6# D3# H_D#4 XDP_TRST# TDO XDP_DBRESET#
M1 A7# D4# F23 3 TRST# DBR# 25
H_A#8 N2 G25 H_D#5 24 XDP_TDI R143 1 2 150_0402_1%
H_A#9 A8# D5# H_D#6 H_RESET#_R DBA#
J1 A9# D6# E25 12 RESET#
D H_A#10 H_D#7 XDP_BPM#0 XDP_TMS R236 D
N3 A10# D7# E23 BPM#0 23 1 2 39.2_0603_1%
H_A#11 P5 K24 H_D#8 XDP_TCK 11 21 XDP_BPM#1
H_A#12 A11# D8# H_D#9 FBO BPM#1 XDP_BPM#2 XDP_BPM#5 R241 56_0402_5%
P2 A12# D9# G24 BPM#2 19 1 2
H_A#13 L1 J24 H_D#10 CLK_CPU_XDP# 8 17 XDP_BPM#3
H_A#14 A13# D10# H_D#11 <15> CLK_CPU_XDP# CLK_CPU_XDP BCLK# BPM#3 XDP_BPM#4 XDP_TRST# R237 680_0402_5%
P4 A14# D11# J23 9 BCLK BPM#4 15 1 2
H_A#15 P1 H26 H_D#12 <15> CLK_CPU_XDP 13 XDP_BPM#5
H_A#16 A15# D12# H_D#13 BPM#5 XDP_TCK R239 27.4_0402_1%
R1 A16# D13# F26 10 GND0 1 2
H_A#17 Y2 K22 H_D#14 14
H_A#18 A17# D14# H_D#15 GND1
U5 A18# D15# H25 16 GND2 NC1 4
H_A#19 R3 N22 H_D#16 18 6
H_A#20 A19# D16# H_D#17 GND3 NC2
W6 A20# D17# K25 20 GND4
H_A#21 U4 P26 H_D#18 22
H_A#22 A21# D18# H_D#19 GND5
Y5 A22# D19# R23
H_A#23 U2 L25 H_D#20
H_A#24 A23# D20# H_D#21 ITP700-FLEXCON
R4 A24# D21# L22
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22
H_A#26 A25# D22# H_D#23
T3 A26# D23# M23
H_A#27 W3 P25 H_D#24
H_A#28 A27# D24# H_D#25
W5 A28# D25# P22
H_A#29 Y4 P23 H_D#26 +VCCP
H_A#30 A29# D26# H_D#27 +VCCP
W2 A30# D27# T24
H_A#31 Y1 R24 H_D#28
<7> H_REQ#[0..4] A31# D28#
2
L26 H_D#29
D29#
2
H_REQ#0 K3 T25 H_D#30 R171
H_REQ#1 REQ0# D30# H_D#31 R104
H2 REQ1# D31# N24 54.9_0402_1%
H_REQ#2 K2 AA23 H_D#32 54.9_0402_1%
H_REQ#3 REQ2# D32# H_D#33
J3 AB24
1
H_REQ#4 REQ3# D33# H_D#34 R142
L5 V24
1
REQ4# D34# H_D#35 H_RESET# H_RESET#_R XDP_TDO XDP_TDO_R
D35# V26 2 1 2 1
H_ADSTB#0 L2 W25 H_D#36 22.6_0402_1%
<7> H_ADSTB#0 ADSTB0# D36#
H_ADSTB#1 V4 U23 H_D#37 R170 22.6_0402_1%
<7> H_ADSTB#1 ADSTB1# D37#
U25 H_D#38
C D38# H_D#39 C
D39# U22
AB25 H_D#40
D40# H_D#41
D41# W22
Y23 H_D#42
CLK_CPU_BCLK D42# H_D#43
<15> CLK_CPU_BCLK A22 BCLK0 D43# AA26
CLK_CPU_BCLK# A21 HOST CLK Y26 H_D#44
<15> CLK_CPU_BCLK# BCLK1 D44# H_D#45
Y22
D45#
D46# AC26
AA24
H_D#46
H_D#47
Thermal Sensor ADM1032AR-2
H_ADS# D47# H_D#48
<7> H_ADS# H1 ADS# D48# AC22
H_BNR# E2 AC23 H_D#49 +3VS
<7> H_BNR# BNR# D49#
H_BPRI# G5 AB22 H_D#50
<7> H_BPRI# BPRI# D50#
H_BR0# F1 AA21 H_D#51
<7> H_BR0# BR0# D51#
H_DEFER# H5 AB21 H_D#52 2
<7> H_DEFER# DEFER# D52#
H_DRDY# F21 AC25 H_D#53 C273
<7> H_DRDY# DRDY# D53#
R172 H_HIT# G6 AD20 H_D#54
<7> H_HIT# HIT# D54#
1
56_0402_5% H_HITM# E4 CONTROL AE22 H_D#55 0.1U_0402_16V4Z
<7> H_HITM# HITM# D55# 1
1 2 H_IERR# D20 AF23 H_D#56 R227
+VCCP H_LOCK# IERR# D56# H_D#57 U16
<7> H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58 1 8 ICH_SMBCLK 10K_0402_5%
<7> H_RESET# RESET# D58# VDD SCLK
AD21 H_D#59
2
D59# H_D#60 H_THERMDA ICH_SMBDATA
<7> H_RS#[0..2] D60# AE25 2 D+ SDATA 7
H_RS#0 F3 AF25 H_D#61 C264
H_RS#1 RS0# D61# H_D#62 H_THERMDC THERM_SCI#
F4 RS1# D62# AF22 1 2 3 D- ALERT# 6 THERM_SCI# <23,26>
H_RS#2 G3 AF26 H_D#63
H_TRDY# RS2# D63# 2200P_0402_50V7K THERM#
<7> H_TRDY# G2 TRDY# 4 THERM# GND 5
1
XDP_TCK AC5 1 1
XDP_TDI TCK H_A20M# D11 C122 C125 1
AA6 TDI A20M# A6 H_A20M# <25> 2
XDP_TDO AB3 A5 H_FERR#
TDO FERR# H_FERR# <25>
R1264 1 2 @ 1K_0402_5% TEST1 C26 C4 H_IGNNE# CH751H-40_SC76 4.7U_0805_10V4Z 0.1U_0402_16V4Z ACES_85205-0200
TEST1 IGNNE# H_IGNNE# <25> 2 2
R1265 2 1 51_0402_5% TEST2 D25 B3 H_INIT#
H_INIT# <25>
2
XDP_TMS TEST2 INIT# H_INTR
AB5 TMS LINT0 C6 H_INTR <25>
XDP_TRST# AB6 B4 H_NMI
TRST# LINT1 H_NMI <25> +3VS
LEGACY CPU FAN
THERMAL
H_THERMDA A24 D5 H_STPCLK#
THERMDA DIODE STPCLK# H_STPCLK# <25>
1
2
5
6
H_THERMDC A25 A3 H_SMI#
THERMDC SMI# H_SMI# <25>
1
H_THERMTRIP# C7 U24 D
<7,25> H_THERMTRIP# THERMTRIP# G
1 Q33 @ ZD1
P
<36> FAN_PWM INB
H_THERMDA, H_THERMDC routing together. O 4 3
S
AO6402_TSOP6
FOX_PZ47903-2741-42_YONAH THERM# 2 RLZ5.1B_LL34
Trace width / Spacing = 10 / 10 mil INA
2
TC7SH00FU_SSOP5
3
A +VCCP A
1
R1266
R1255 H_DPSLP# 1 2
@ 56_0402_5% @ 56_0402_5%
R1267 Security Classification Compal Secret Data Compal Electronics, Inc.
2 2
@ 56_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
E
H_PROCHOT# 3 1 OCP# AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
OCP# <26,50>
C
Q85 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
@ MMBT3904_SOT23 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 4 of 54
5 4 3 2 1
5 4 3 2 1
+VCCP
Length match within 25 mils JP12B
+VCC_CORE
JP12C
D
The trace width 18 mils space D
1
<49> VCCSENSE VCCSENSE AF7 AB26 AE18 K1
+VCC_CORE 7 mils <49> VSSSENSE VSSSENSE AE7
VCCSENSE
VSSSENSE
VSS
VSS AA25 AE17
VCC
VCC
VSS
VSS J2
R1268 R1269 AD25 AB15 M2
V_CPU_GTLREF 1K_0402_1% 100_0402_1% VSS VCC VSS
VSS AE26 AA15 VCC VSS N1
1 2 VCCSENSE B26 AB23 AD15 T1
2
+1.5VS VCCA VSS VCC VSS
0.01U_0402_16V7K
VSS AC24 AC15 VCC VSS R2
10U_0805_10V4Z
R1270 K6 AF24 AF15 V2
100_0402_1% +VCCP VCCP VSS VCC VSS
J6 VCCP VSS AE23 AE15 VCC VSS W1
1
C520
C531
N6 AD22 AA13 D26
R1271
2K_0402_1%
T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
2 2
K21 AB19 AF14 B24
2
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
R245
R355
FOX_PZ47903-2741-42_YONAH FOX_PZ47903-2741-42_YONAH
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah CPU in mFCPGA479
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 5 of 54
5 4 3 2 1
5 4 3 2 1
D +VCC_CORE D
1 1 1 1 1 1 1 1
C899 C900 C901 C902 C903 C904 C905 C906
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2
+VCC_CORE
1 1 1 1 1 1 1 1
C907 C908 C909 C910 C911 C912 C913 C914
Place these capacitors on L8
(North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2
+VCC_CORE
1 1 1 1 1 1 1 1
C915 C916 C917 C918 C919 C920 C921 C922
Place these capacitors on L8
(Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2
C C
+VCC_CORE
1 1 1 1 1 1 1 1
C923 C924 C925 C926 C927 C928 C929 C930
Place these capacitors on L8
(Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
2 2 2 2 2 2 2 2
+VCC_CORE
330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7
+VCCP
1
1 1 1 1 1 1
C983 + C940 C941 C942 C943 C944 C945
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU Bypass capacitors
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 6 of 54
5 4 3 2 1
5 4 3 2 1
DMI
H_D#10 K7 D9 H_A#13 DMI_TXP3 AG39 G16 CFG9
HD10# HA13# <26> DMI_TXP3 DMIRXP3 CFG9 CFG9 <11>
H_D#11 J8 J14 H_A#14 E16 CFG10 PAD T76
H_D#12 HD11# HA14# H_A#15 CFG10 CFG11
H4 HD12# HA15# H13 CFG11 D15 CFG11 <11>
H_D#13 J3 J15 H_A#16 DMI_RXN0 AE37 G15 CFG12
HD13# HA16# <26> DMI_RXN0 DMITXN0 CFG12 CFG12 <11>
H_D#14 K11 F14 H_A#17 DMI_RXN1 AF41 K15 CFG13
HD14# HA17# <26> DMI_RXN1 DMITXN1 CFG13 CFG13 <11>
CFG
H_D#15 G4 D12 H_A#18 DMI_RXN2 AG37 C15 CFG14 PAD T77
HD15# HA18# <26> DMI_RXN2 DMITXN2 CFG14
H_D#16 T10 A11 H_A#19 DMI_RXN3 AH41 H16 CFG15 PAD T78
HD16# HA19# <26> DMI_RXN3 DMITXN3 CFG15
H_D#17 W11 C11 H_A#20 G18 CFG16
HD17# HA20# CFG16 CFG16 <11>
H_D#18 T3 A12 H_A#21 H15 CFG17 PAD T79
H_D#19 HD18# HA21# H_A#22 DMI_RXP0 CFG17 CFG18
U7 HD19# HA22# A13 <26> DMI_RXP0 AC37 DMITXP0 CFG18 J25 CFG18 <11>
H_D#20 U9 E13 H_A#23 DMI_RXP1 AE41 K27 CFG19
HD20# HA23# <26> DMI_RXP1 DMITXP1 CFG19 CFG19 <11>
H_D#21 U11 G13 H_A#24 DMI_RXP2 AF37 J26 CFG20
HD21# HA24# <26> DMI_RXP2 DMITXP2 CFG20 CFG20 <11>
H_D#22 T11 F12 H_A#25 DMI_RXP3 AG41
HD22# HA25# <26> DMI_RXP3 DMITXP3
H_D#23 W9 B12 H_A#26
H_D#24 HD23# HA26# H_A#27
T1 HD24# HA27# B14 G_CLKP AG33 CLK_MCH_3GPLL CLK_MCH_3GPLL <15>
H_D#25 T8 C12 H_A#28 M_CLK_DDR0 AY35 AF33 CLK_MCH_3GPLL#
HD25# HA28# <13> M_CLK_DDR0 SM_CK0 G_CLKN CLK_MCH_3GPLL# <15>
H_D#26 T4 A14 H_A#29 M_CLK_DDR1 AR1
HD26# HA29# <13> M_CLK_DDR1 SM_CK1
H_D#27 W7 C14 H_A#30 M_CLK_DDR2 AW7 A27 R103 1 2 10K_0402_5%
CLK
HD27# HA30# <14> M_CLK_DDR2 SM_CK2 D_REF_CLKN
H_D#28 U5 D14 H_A#31 M_CLK_DDR3 AW40 A26 R105 1 2 10K_0402_5%
HD28# HA31# <14> M_CLK_DDR3 SM_CK3 D_REF_CLKP
H_D#29 T9
H_D#30 HD29# M_CLK_DDR#0 R107 1
W6 HD30# <13> M_CLK_DDR#0 AW35 SM_CK0# D_REF_SSCLKN C40 2 10K_0402_5%
H_D#31 T5 M_CLK_DDR#1 AT1 D41 R110 1 2 10K_0402_5%
H_D#32 AB7
HD31#
HD32#
HOST HREQ#0 D8 H_REQ#0
H_REQ#[0..4] <4> <13>
<14>
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#2 AY7
SM_CK1#
SM_CK2#
D_REF_SSCLKP
H_D#33 AA9 G8 H_REQ#1 M_CLK_DDR#3 AY40 H32 GMCH_H32
HD33# HREQ#1 <14> M_CLK_DDR#3 SM_CK3# CLK_REQ#
H_D#34 W4 B8 H_REQ#2
H_D#35 HD34# HREQ#2 H_REQ#3 DDR_CKE0_DIMMA
W3 HD35# HREQ#3 F8 <13> DDR_CKE0_DIMMA AU20 SM_CKE0
DDR MUXING
H_D#36 Y3 A8 H_REQ#4 DDR_CKE1_DIMMA AT20
HD36# HREQ#4 <13> DDR_CKE1_DIMMA SM_CKE1
H_D#37 Y7 DDR_CKE2_DIMMB BA29 A3
C HD37# <14> DDR_CKE2_DIMMB SM_CKE2 NC0 C
H_D#38 W5 DDR_CKE3_DIMMB AY29 A39
HD38# <14> DDR_CKE3_DIMMB SM_CKE3 NC1
H_D#39 Y10 B9 H_ADSTB#0 A4
HD39# HADSTB#0 H_ADSTB#0 <4> NC2
H_D#40 AB8 C13 H_ADSTB#1 DDR_CS0_DIMMA# AW13 A40
HD40# HADSTB#1 H_ADSTB#1 <4> <13> DDR_CS0_DIMMA# SM_CS0# NC3
H_D#41 W2 DDR_CS1_DIMMA# AW12 AW1
HD41# <13> DDR_CS1_DIMMA# SM_CS1# NC4
H_D#42 AA4 AG1 CLK_MCH_BCLK# DDR_CS2_DIMMB# AY21 AW41
HD42# HCLKN CLK_MCH_BCLK# <15> <14> DDR_CS2_DIMMB# SM_CS2# NC5
H_D#43 AA7 AG2 CLK_MCH_BCLK DDR_CS3_DIMMB# AW21 AY1
HD43# HCLKP CLK_MCH_BCLK <15> <14> DDR_CS3_DIMMB# SM_CS3# NC6
H_D#44 AA2 BA1
NC
HD44# H_DSTBN#[0..3] <4> NC7
H_D#45 AA6 K4 H_DSTBN#0 M_OCDOCMP0 AL20 BA2
H_D#46 HD45# HDSTBN#0 H_DSTBN#1 M_OCDOCMP1 SM_OCDCOMP0 NC8
AA10 HD46# HDSTBN#1 T7 AF10 SM_OCDCOMP1 NC9 BA3
H_D#47 Y8 Y5 H_DSTBN#2 BA39
L H_D#48 AA1
HD47#
HD48#
HDSTBN#2
HDSTBN#3 AC4 H_DSTBN#3
H_DSTBP#[0..3] <4> +1.8V <13> M_ODT0
M_ODT0 BA13 SM_ODT0
NC10
NC11 BA40
H_D#49 AB4 K3 H_DSTBP#0 M_ODT1 BA12 BA41
HD49# HDSTBP#0 <13> M_ODT1 SM_ODT1 NC12
H_XSCOMP/H_YSCOMP trace H_D#50 AC9 T6 H_DSTBP#1 M_ODT2 AY20 C1
HD50# HDSTBP#1 <14> M_ODT2 SM_ODT2 NC13
H_D#51 AB11 AA5 H_DSTBP#2 M_ODT3 AU21 AY41
width and spacing is 5/20. HD51# HDSTBP#2 <14> M_ODT3 SM_ODT3 NC14
H_D#52 AC11 AC5 H_DSTBP#3 B2
H_D#53 HD52# HDSTBP#3 R1194 1 SMRCOMPN NC15
AB3 HD53# 2 80.6_0402_1% AV9 SM_RCOMPN NC16 B41
+VCCP H_D#54 AC2 1 2 SMRCOMPP AT9 C41
H_D#55 HD54# H_DINV#0 R1195 80.6_0402_1% SM_RCOMPP NC17
AD1 HD55# HDINV#0 J7 H_DINV#0 <4> NC18 D1
H_D#56 AD9 W8 H_DINV#1 AK1
HD56# HDINV#1 H_DINV#1 <4> SM_VREF0
H_D#57 AC1 U3 H_DINV#2 V_DDR_MCH_REF AK41
HD57# HDINV#2 H_DINV#2 <4> SM_VREF1
54.9_0402_1%
54.9_0402_1%
R1197
PM
RESERVED
H_D#62 AD4 E8 H_ADS# <26,49> DPRSLPVR R1309 1 2 0_0402_5% PM_EXTTS#1 H26 AG11
HD62# HADS# H_ADS# <4> PM_EXTTS1# RESERVED5
H_D#63 AC8 E7 H_TRDY# <4,25> H_THERMTRIP# H_THERMTRIP# G6 AF11
H_TRDY# <4>
2
24.9_0402_1%
V_DDR_MCH_REF
1
R1200
B4 H_RS#0 DDR_THERM# 2 1
HRS0# Route as short
E6 H_RS#1 spacing is 20/20. 10K_0402_5%
HRS1#
D6 H_RS#2 as possible
HRS2# R1209
H_RS#[0..2] <4>
2
PM_EXTTS#1 2 1
CALISTOGA_FCBGA1466~D +1.8V @ 10K_0402_5%
1
M_OCDOCMP0
R1201 M_OCDOCMP1
@ 100_0402_1%
Layout Note:
40.2_0402_1%
40.2_0402_1%
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 /
1
V_DDR_MCH_REF
<13,14,47> V_DDR_MCH_REF
H_SWNG1 trace width and spacing is 18/20.
0.1U_0402_16V4Z
R1344
R1202
R1203
GMCH_H32 1 2 CLKREQC# CLKREQC# <15>
1 R1204 0_0402_5%
+VCCP +VCCP @ 100_0402_1%
2
C895
@ @
+VCCP
2
2
221_0603_1%
221_0603_1%
1
1
100_0402_1%
1
R1206
R1207
R1208
A A
2
H_SWNG0 H_SWNG1
2
H_VREF
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
100_0402_1%
100_0402_1%
1 1
1
200_0402_1%
R1210
R1211
1
R1212
C898
C896
C897
2
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 7 of 54
5 4 3 2 1
5 4 3 2 1
D D
U15D U15E
DDR_A_D[0..63] <13> DDR_B_D[0..63] <14>
DDR_A_BS#0 AU12 AJ35 DDR_A_D0 DDR_B_BS#0 AT24 AK39 DDR_B_D0
<13> DDR_A_BS#0 SA_BS0 SA_DQ0 <14> DDR_B_BS#0 SB_BS0 SB_DQ0
DDR_A_BS#1 AV14 AJ34 DDR_A_D1 DDR_B_BS#1 AV23 AJ37 DDR_B_D1
<13> DDR_A_BS#1 SA_BS1 SA_DQ1 <14> DDR_B_BS#1 SB_BS1 SB_DQ1
DDR_A_BS#2 BA20 AM31 DDR_A_D2 DDR_B_BS#2 AY28 AP39 DDR_B_D2
<13> DDR_A_BS#2 SA_BS2 SA_DQ2 <14> DDR_B_BS#2 SB_BS2 SB_DQ2
AM33 DDR_A_D3 AR41 DDR_B_D3
SA_DQ3 DDR_A_D4 SB_DQ3 DDR_B_D4
SA_DQ4 AJ36 SB_DQ4 AJ38
<13> DDR_A_DM[0..7] AK35 DDR_A_D5 <14> DDR_B_DM[0..7] AK38 DDR_B_D5
DDR_A_DM0 SA_DQ5 DDR_A_D6 DDR_B_DM0 SB_DQ5 DDR_B_D6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDR_A_DM1 AM35 AH31 DDR_A_D7 DDR_B_DM1 AR38 AP41 DDR_B_D7
DDR_A_DM2 SA_DM1 SA_DQ7 DDR_A_D8 DDR_B_DM2 SB_DM1 SB_DQ7 DDR_B_D8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDR_A_DM3 AN22 AP33 DDR_A_D9 DDR_B_DM3 BA31 AV41 DDR_B_D9
DDR_A_DM4 SA_DM3 SA_DQ9 DDR_A_D10 DDR_B_DM4 SB_DM3 SB_DQ9 DDR_B_D10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDR_A_DM5 AL9 AP31 DDR_A_D11 DDR_B_DM5 AH8 AV38 DDR_B_D11
DDR_A_DM6 SA_DM5 SA_DQ11 DDR_A_D12 DDR_B_DM6 SB_DM5 SB_DQ11 DDR_B_D12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDR_A_DM7 AH4 AM36 DDR_A_D13 DDR_B_DM7 AN4 AR40 DDR_B_D13
SA_DM7 SA_DQ13 DDR_A_D14 SB_DM7 SB_DQ13 DDR_B_D14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDR_A_D15 AY38 DDR_B_D15
SA_DQ15 DDR_A_D16 SB_DQ15 DDR_B_D16
SA_DQ16 AK26 SB_DQ16 BA38
<13> DDR_A_DQS[0..7] AL27 DDR_A_D17 <14> DDR_B_DQS[0..7] AV36 DDR_B_D17
DDR_A_DQS0 SA_DQ17 DDR_A_D18 DDR_B_DQS0 SB_DQ17 DDR_B_D18
AK33 SA_DQS0 SA_DQ18 AM26 AM39 SB_DQS0 SB_DQ18 AR36
DDR_A_DQS1 AT33 AN24 DDR_A_D19 DDR_B_DQS1 AT39 AP36 DDR_B_D19
DDR_A_DQS2 SA_DQS1 SA_DQ19 DDR_A_D20 DDR_B_DQS2 SB_DQS1 SB_DQ19 DDR_B_D20
AN28 AK28 AU35 BA36
CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 8 of 54
5 4 3 2 1
5 4 3 2 1
D D
LVDS
D29 LB_DATA1 EXP_RXN10 V34
F28 W38 PEG_RXN11
LB_DATA2 EXP_RXN11 PEG_RXN12
EXP_RXN12 Y34
G30 AA38 PEG_RXN13
LB_DATA#0 EXP_RXN13 PEG_RXN14
D30 LB_DATA#1 EXP_RXN14 AB34
F29 AC38 PEG_RXN15
LB_DATA#2 EXP_RXN15 PEG_RXP[0..15] <18>
A32 D34 PEG_RXP0
LA_CLK EXP_RXP0 PEG_RXP1
A33 LA_CLK# EXP_RXP1 F38
E26 G34 PEG_RXP2
LB_CLK EXP_RXP2 PEG_RXP3
E27 H38
PCI-EXPRESS GRAPHICS
LB_CLK# EXP_RXP3 PEG_RXP4
EXP_RXP4 J34
D32 L38 PEG_RXP5
C LBKLT_CTL EXP_RXP5 PEG_RXP6 C
J30 LBKLT_EN EXP_RXP6 M34
H30 N38 PEG_RXP7
LCTLA_CLK EXP_RXP7 PEG_RXP8
H29 LCTLB_DATA EXP_RXP8 P34
G26 R38 PEG_RXP9
LDDC_CLK EXP_RXP9 PEG_RXP10
G25 LDDC_DATA EXP_RXP10 T34
F32 V38 PEG_RXP11
LVDD_EN EXP_RXP11 PEG_RXP12
B38 LIBG EXP_RXP12 W34
C35 Y38 PEG_RXP13
LVBG EXP_RXP13 PEG_RXP14
C33 LVREFH EXP_RXP14 AA34
C32 AB38 PEG_RXP15 PEG_M_TXN[0..15] <18>
+1.5VS LVREFL EXP_RXP15
F36 PEG_TXN0 C1066 1 2 0.1U_0402_16V4Z PEG_M_TXN0
EXP_TXN0 PEG_TXN1 C1067 1 0.1U_0402_16V4Z PEG_M_TXN1
A16 TVDAC_A EXP_TXN1 G40 2
C18 H36 PEG_TXN2 C1068 1 2 0.1U_0402_16V4Z PEG_M_TXN2
TVDAC_B EXP_TXN2 PEG_TXN3 C1069 1 0.1U_0402_16V4Z PEG_M_TXN3
A19 TVDAC_C EXP_TXN3 J40 2
TV
L36 PEG_TXN4 C1070 1 2 0.1U_0402_16V4Z PEG_M_TXN4
EXP_TXN4 PEG_TXN5 C1071 1 0.1U_0402_16V4Z PEG_M_TXN5
J20 TV_IREF EXP_TXN5 M40 2
N36 PEG_TXN6 C1072 1 2 0.1U_0402_16V4Z PEG_M_TXN6
EXP_TXN6 PEG_TXN7 C1073 1 0.1U_0402_16V4Z PEG_M_TXN7
B16 TV_IRTNA EXP_TXN7 P40 2
B18 R36 PEG_TXN8 C1074 1 2 0.1U_0402_16V4Z PEG_M_TXN8
TV_IRTNB EXP_TXN8 PEG_TXN9 C1075 1 0.1U_0402_16V4Z PEG_M_TXN9
B19 TV_IRTNC EXP_TXN9 T40 2
V36 PEG_TXN10 C1076 1 2 0.1U_0402_16V4Z PEG_M_TXN10
EXP_TXN10 PEG_TXN11 C1077 1 0.1U_0402_16V4Z PEG_M_TXN11
J29 TV_DCONSEL1 EXP_TXN11 W40 2
K30 Y36 PEG_TXN12 C1078 1 2 0.1U_0402_16V4Z PEG_M_TXN12
TV_DCONSEL0 EXP_TXN12 PEG_TXN13 C1079 1 0.1U_0402_16V4Z PEG_M_TXN13
EXP_TXN13 AA40 2
AB36 PEG_TXN14 C1080 1 2 0.1U_0402_16V4Z PEG_M_TXN14
EXP_TXN14 PEG_TXN15 C1081 1 0.1U_0402_16V4Z PEG_M_TXN15
EXP_TXN15 AC40 2
C26 DDCCLK PEG_M_TXP[0..15] <18>
CRT
CALISTOGA_FCBGA1466~D
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 9 of 54
5 4 3 2 1
5 4 3 2 1
0.1U_0402_16V4Z
1
C831
D D
U15H
+VCCP 2
VCC_SYNC H22
AC14 VTT0
AB14 VTT1 VCCTX_LVDS0 B30
W14 C30 +1.5VS_PCIE
VTT2 VCCTX_LVDS1 R1163
V14 VTT3 VCCTX_LVDS2 A30
T14 0_0805_5%
VTT4 10U_0805_6.3V6M
R14 VTT5 VCC3G0 AB41 2 1 +1.5VS
P14 AJ41
N14
VTT6
VTT7
VCC3G1
VCC3G2 L41 W=40 mils 1
M14 VTT8 VCC3G3 N41 1 C824 1 C825
L14 R41 +
VTT9 VCC3G4
AD13 VTT10 VCC3G5 V41
AC13 Y41 10U_0805_6.3V6M
VTT11 VCC3G6 2 2 2
220U_D2_2VM_R9
AB13 VTT12
1 AA13 VTT13 VCCA_3GPLL AC33 +1.5VS_3GPLL
Y13 VTT14 VCCA_3GBG G41 +2.5VS
+
C830
2.2U_0805_16V4Z
C837
N11 VTT37
M11 E19 +1.5VS_3GPLL +1.5VS
VTT38 VCCA_TVDACA0 +1.5VS
R10 F19 R1339 R1168
2 2 VTT39 VCCA_TVDACA1 3GPLL 2
P10 VTT40 VCCA_TVDACB0 C20 1 2 1
0.5_0805_1% 0_0805_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
N10 VTT41 VCCA_TVDACB1 D20
M10 VTT42 VCCA_TVDACC0 E20
P9 VTT43 VCCA_TVDACC1 F20 1 1 1
N9 C839
VTT44
C838
C841
M9 VTT45
R8 VTT46 VCCD_HMPLL0 AH1 +1.5VS
P8 AH2 2 2 2
VTT47 VCCD_HMPLL1
N8 VTT48
M8 @
VTT49 10U_0805_6.3V6M
P7 VTT50 VCCD_LVDS0 A28
N7 VTT51 VCCD_LVDS1 B28
M7 VTT52 VCCD_LVDS2 C28
R6 VTT53
P6 VTT54 VCCD_TVDAC D21 +1.5VS
M6 VTT55 VCCDQ_TVDAC H19
MCH_A6 +1.5VS_MPLL +1.5VS_HPLL
A6 VTT56 R1173 R1174
0.47U_0603_10V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M5 VTT60 1 1
P4 AK31 C846
VTT61 VCCAUX0
N4 VTT62 VCCAUX1 AF31 1 1 1 1
2
C845
C859
C861
R3 VTT64 VCCAUX3 AC31
B P3 AL30 10U_0805_6.3V6M 10U_0805_6.3V6M B
VTT65 VCCAUX4 2 2 2 2
N3 VTT66 VCCAUX5 AK30
0.22U_0603_10V7K
MCH_D2 D2 AE30
VTT71 VCCAUX10
AB1 VTT72 VCCAUX11 AD30 1
0.22U_0603_10V7K
2
C850
2
2
1 VCCAUX17 AC29
C856
1 1
1 1
VCCAUX21
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
AF14 AJ20 R127 +2.5VS R520 +3VS
VCCAUX33 VCCAUX24
AE14 VCCAUX34 VCCAUX25 AH20
Y14 AH19 @ 10_0402_5% @ 10_0402_5%
VCCAUX35 VCCAUX26
AF13 P19
2
VCCAUX36 VCCAUX27
AE13 VCCAUX37 VCCAUX28 P16
+1.5VS AF12 AH15
VCCAUX38 VCCAUX29
AE12 VCCAUX39 VCCAUX30 P15
AD12 VCCAUX40 VCCAUX31 AH14
CALISTOGA_FCBGA1466~D
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 10 of 54
5 4 3 2 1
5 4 3 2 1
AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
AC27 VCC_NCTF1 VCCAUX_NCTF1 AF27 W33 VCC1 VCC_SM1 AT41 VCCSM_LF4 CFG[2:0] 001 = 533MT/s FSB
AB27 AG26 P33 AM41 VCCSM_LF5
VCC_NCTF2 VCCAUX_NCTF2 VCC2 VCC_SM2
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 0 = DMI x 2
CFG5 1 = DMI x 4 *(Default)
0.47U_0603_10V7K
0.47U_0603_10V7K
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved
CFG7 1 = Mobile Yonah CPU *(Default)
C794
D D
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34
C795
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0 = Lane Reversal Enable *
0.22U_0603_10V7K
0.22U_0603_10V7K
0.22U_0603_10V7K
C797
C798
AA26 AF21 L32 AW30 (According to Intel Napa Schematic Checklist & CRB
VCC_NCTF13 VCCAUX_NCTF13 VCC13 VCC_SM13
2 2 2
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30 CFG11 Rev1.301 document 2.2Kohm pull-down resistor request)
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 1 = Reserved
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 W31 VCC16 VCC_SM16 AT30
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin AT41 & AM41
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 T31 VCC18 VCC_SM18 AP30 00 = Reserved
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 R31 VCC19 VCC_SM19 AN30 CFG[13:12] 01 = XOR Mode Enabled
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 P31 VCC20 VCC_SM20 AM30 10 = All Z Mode Enabled
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 N31 VCC21 VCC_SM21 AM29
+1.8V
11 = Normal Operation *(Default)
AB25 VCC_NCTF22 VCCAUX_NCTF22 AG17 M31 VCC22 VCC_SM22 AL29
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 0 = Dynamic ODT Disabled
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 Y30 VCC24 VCC_SM24 AJ29 CFG16 1 = Dynamic ODT Enabled *(Default)
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29
0 = 1.05V *(Default)
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
V25 VCC_NCTF26 VCCAUX_NCTF26 AB17 V30 VCC26 VCC_SM26 AJ28
10U_0805_6.3V6M U25 VCC_NCTF27 VCCAUX_NCTF27 AA17 U30 VCC27 VCC_SM27 AH28 CFG18 1 = 1.5V
1U_0603_10V4Z
C799
C800
C801
C802
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26
C803 C804 AC24 R17 N30 AY26
VCC_NCTF31 VCCAUX_NCTF31 VCC31 VCC_SM31 2 2 2 2
P O W E R 0 = No SDVO Device Present *
C805
0.47U_0603_10V7K
AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22
220U_D2_2VM_R9
C807
R22 VCC_NCTF49 VCCAUX_NCTF49 AC15 R28 VCC49 VCC_SM49 AU22
C806
0.47U_0603_10V7K
AC22 AW15 R1158 1 2 @ 1K_0402_5%
+1.8V VCC74 VCC_SM74 <7> CFG18
M19 AB22 AV15 R1159 1 2 @ 1K_0402_5%
VCC100 VCC75 VCC_SM75 <7> CFG19
L19 AR6 Y22 AU15 1 R1160 1 2 @ 1K_0402_5%
VCC101 VCC_SM100 VCC76 VCC_SM76 <7> CFG20
N18 VCC102 VCC_SM101 AP6 W22 VCC77 VCC_SM77 AT15
C812
M18 VCC103 VCC_SM102 AN6 P22 VCC78 VCC_SM78 AR15
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13
M17 VCC107 VCC_SM106 AV1 VCCSM_LF2 AC21 VCC82 VCC_SM82 AH13
N16 VCC108 VCC_SM107 AJ1 VCCSM_LF1 AA21 VCC83 VCC_SM83 AK12
M16 VCC109 W21 VCC84 VCC_SM84 AJ12
0.47U_0603_10V7K
0.47U_0603_10V7K
C814
CALISTOGA_FCBGA1466~D
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 11 of 54
5 4 3 2 1
5 4 3 2 1
U15I U15J
AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
D D
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 VSS19 VSS119 AG32 K19 VSS219 VSS299 C8
AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7
AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39
T39
VSS29
VSS30
VSS129
VSS130
AJ31
AG31
AP17
AM17
VSS229
VSS230
P O W E R VSS309
VSS310
G7
D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 VSS32 VSS132 Y31 AV16 VSS232 VSS312 AD6
N39 VSS33 VSS133 AB30 AN16 VSS233 VSS313 AB6
M39
L39
VSS34
VSS35
P O W E R VSS134
VSS135
E30
AT29
AL16
J16
VSS234
VSS235
VSS314
VSS315
Y6
U6
J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
C C
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
F39 VSS39 VSS139 N29 AM15 VSS239 VSS319 B6
D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 VSS49 VSS149 AP28 AD14 VSS249 VSS329 U4
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3
L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
H37 VSS62 VSS162 C27 F13 VSS262 VSS342 AC3
G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
AY36 VSS66 VSS166 K26 AC12 VSS266 VSS346 AR2
AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
B B
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2
B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
AR35 VSS78 VSS178 AL24 AL10 VSS278 VSS358 F2
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 VSS81 VSS181 AN23
Y35 AM23 CALISTOGA_FCBGA1466~D
VSS82 VSS182
W35 VSS83 VSS183 AH23
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21
CALISTOGA_FCBGA1466~D
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (6/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 12 of 54
5 4 3 2 1
5 4 3 2 1
+1.8V +1.8V
V_DDR_MCH_REF
<8> DDR_A_DQS#[0..7] V_DDR_MCH_REF <7,14,47>
2.2U_0805_16V4Z
0.1U_0402_16V4Z
1 VREF VSS 2
3 4 DDR_A_D7 1 1
<8> DDR_A_DM[0..7] VSS DQ4
C363
C362
DDR_A_D0 5 6 DDR_A_D1
DDR_A_D4 DQ0 DQ5
<8> DDR_A_DQS[0..7] 7 DQ1 VSS 8
9 10 DDR_A_DM0
DDR_A_DQS#0 VSS DM0 2 2
<8> DDR_A_MA[0..13] 11 DQS0# VSS 12
DDR_A_DQS0 13 14 DDR_A_D5
DQS0 DQ6 DDR_A_D6
15 VSS DQ7 16
DDR_A_D2 17 18
D DDR_A_D3 DQ2 VSS DDR_A_D12 D
19 DQ3 DQ12 20
21 22 DDR_A_D13
DDR_A_D8 VSS DQ13
23 DQ8 VSS 24
Layout Note: DDR_A_D14 25 26 DDR_A_DM1
DQ9 DM1
27 VSS VSS 28
Place near JP34 DDR_A_DQS#1 29 30 M_CLK_DDR0
M_CLK_DDR0 <7>
DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
31 DQS1 CK0# 32 M_CLK_DDR#0 <7>
33 VSS VSS 34
DDR_A_D10 35 36 DDR_A_D9
DDR_A_D11 DQ10 DQ14 DDR_A_D15
37 DQ11 DQ15 38
39 VSS VSS 40
+1.8V 41 42
DDR_A_D21 VSS VSS DDR_A_D20
43 DQ16 DQ20 44
DDR_A_D17 45 46 DDR_A_D16
DQ17 DQ21
47 VSS VSS 48
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_DQS#2 49 50
DQS2# NC DDR_THERM# <7,14>
1 1 1 1 1 1 1 1 1 DDR_A_DQS2 51 52 DDR_A_DM2
DQS2 DM2
C458
C498
C473
C491
C465
C255
C242
C280
C235
53 VSS VSS 54
DDR_A_D22 55 56 DDR_A_D18
DDR_A_D19 DQ18 DQ22 DDR_A_D23
57 DQ19 DQ23 58
2 2 2 2 2 2 2 2 2
59 VSS VSS 60
DDR_A_D25 61 62 DDR_A_D29
DDR_A_D24 DQ24 DQ28 DDR_A_D28
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_A_DM3 67 68 DDR_A_DQS#3
DM3 DQS3# DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_A_D27 73 74 DDR_A_D26
DDR_A_D30 DQ26 DQ30 DDR_A_D31
75 DQ27 DQ31 76
77 VSS VSS 78
C DDR_CKE0_DIMMA DDR_CKE1_DIMMA C
<7> DDR_CKE0_DIMMA 79 CKE0 NC/CKE1 80 DDR_CKE1_DIMMA <7>
81 VDD VDD 82
83 NC NC/A15 84
DDR_A_BS#2 85 86
<8> DDR_A_BS#2 BA2 NC/A14
Layout Note: DDR_A_MA12
87 VDD VDD 88
DDR_A_MA11
89 A12 A11 90
Place one cap close to every 2 pullup DDR_A_MA9 91 92 DDR_A_MA7
DDR_A_MA8 A9 A7 DDR_A_MA6
resistors terminated to +0.9V 93 A8 A6 94
95 VDD VDD 96
DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 A3 A2 100
DDR_A_MA1 101 102 DDR_A_MA0
A1 A0
103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS#1
A10/AP BA1 DDR_A_BS#1 <8>
DDR_A_BS#0 107 108 DDR_A_RAS#
<8> DDR_A_BS#0 BA0 RAS# DDR_A_RAS# <8>
DDR_A_WE# 109 110 DDR_CS0_DIMMA#
+0.9V <8> DDR_A_WE# WE# S0# DDR_CS0_DIMMA# <7>
111 VDD VDD 112
DDR_A_CAS# 113 114 M_ODT0
<8> DDR_A_CAS# CAS# ODT0 M_ODT0 <7>
DDR_CS1_DIMMA# 115 116 DDR_A_MA13
<7> DDR_CS1_DIMMA# NC/S1# NC/A13
117 VDD VDD 118
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C239
C250
C257
C272
C279
C281
C274
C268
C252
C241
C234
C227
1
10K_0402_5%
10K_0402_5%
DDR_A_CAS# 1 4 4 1 DDR_A_MA0 1
DDR_A_WE# 2 3 3 2 DDR_A_BS#1 C308 FOX_ASOA426-M4R-TR
R455
R453
A A
RP35 56_0404_4P2R_5% RP34 56_0404_4P2R_5%
DDR_CS1_DIMMA# 2
0.1U_0402_16V4Z
2
SO-DIMM A
3 4 1 M_ODT0
REVERSE
2
M_ODT1 1 4 3 2 DDR_A_MA13
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 13 of 54
5 4 3 2 1
5 4 3 2 1
+1.8V +1.8V
<8> DDR_B_DQS#[0..7]
<8> DDR_B_D[0..63]
V_DDR_MCH_REF
V_DDR_MCH_REF <7,13,47>
<8> DDR_B_DM[0..7] JP10
2.2U_0805_16V4Z
0.1U_0402_16V4Z
<8> DDR_B_DQS[0..7] 1 VREF VSS 2
3 4 DDR_B_D4 1 1
DDR_B_D0 VSS DQ4 DDR_B_D1
<8> DDR_B_MA[0..13] 5 DQ0 DQ5 6
C89
C90
DDR_B_D5 7 8
DQ1 VSS DDR_B_DM0
9 VSS DM0 10
DDR_B_DQS#0 2 2
11 DQS0# VSS 12
DDR_B_DQS0 13 14 DDR_B_D6
DQS0 DQ6 DDR_B_D2
15 VSS DQ7 16
D DDR_B_D7 D
17 DQ2 VSS 18
Layout Note: DDR_B_D3 19 20 DDR_B_D12
DQ3 DQ12 DDR_B_D13
21 VSS DQ13 22
Place near JP34 DDR_B_D8 23 24
DDR_B_D9 DQ8 VSS DDR_B_DM1
25 DQ9 DM1 26
27 VSS VSS 28
DDR_B_DQS#1 29 30 M_CLK_DDR3
DQS1# CK0 M_CLK_DDR3 <7>
DDR_B_DQS1 31 32 M_CLK_DDR#3
DQS1 CK0# M_CLK_DDR#3 <7>
33 VSS VSS 34
DDR_B_D10 35 36 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
37 DQ11 DQ15 38
+1.8V 39 40
VSS VSS
41 VSS VSS 42
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
2.2U_0805_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_B_D21 43 44 DDR_B_D16
DDR_B_D20 DQ16 DQ20 DDR_B_D18
1 1 1 1 1 1 1 1 1 45 DQ17 DQ21 46
C236
C265
C247
C159
C164
C166
C219
C188
C161
47 VSS VSS 48
DDR_B_DQS#2 49 50
DQS2# NC DDR_THERM# <7,13>
DDR_B_DQS2 51 52 DDR_B_DM2
2 2 2 2 2 2 2 2 2 DQS2 DM2
53 VSS VSS 54
DDR_B_D22 55 56 DDR_B_D17
DDR_B_D23 DQ18 DQ22 DDR_B_D19
57 DQ19 DQ23 58
59 VSS VSS 60
DDR_B_D24 61 62 DDR_B_D26
DDR_B_D25 DQ24 DQ28 DDR_B_D28
63 DQ25 DQ29 64
65 VSS VSS 66
DDR_B_DM3 67 68 DDR_B_DQS#3
DM3 DQS3# DDR_B_DQS3
69 NC DQS3 70
71 VSS VSS 72
DDR_B_D30 73 74 DDR_B_D29
DDR_B_D31 DQ26 DQ30 DDR_B_D27
75 DQ27 DQ31 76
C C
77 VSS VSS 78
DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB
<7> DDR_CKE2_DIMMB CKE0 NC/CKE1 DDR_CKE3_DIMMB <7>
81 VDD VDD 82
Layout Note: DDR_B_BS#2
83 NC NC/A15 84
<8> DDR_B_BS#2 85 BA2 NC/A14 86
Place one cap close to every 2 pullup 87 88
DDR_B_MA12 VDD VDD DDR_B_MA11
resistors terminated to +0.9V 89 A12 A11 90
DDR_B_MA9 91 92 DDR_B_MA7
DDR_B_MA8 A9 A7 DDR_B_MA6
93 A8 A6 94
95 VDD VDD 96
DDR_B_MA5 97 98 DDR_B_MA4
DDR_B_MA3 A5 A4 DDR_B_MA2
99 A3 A2 100
DDR_B_MA1 101 102 DDR_B_MA0
A1 A0
103 VDD VDD 104
DDR_B_MA10 105 106 DDR_B_BS#1
+0.9V A10/AP BA1 DDR_B_BS#1 <8>
DDR_B_BS#0 107 108 DDR_B_RAS#
<8> DDR_B_BS#0 BA0 RAS# DDR_B_RAS# <8>
DDR_B_WE# 109 110 DDR_CS2_DIMMB#
<8> DDR_B_WE# WE# S0# DDR_CS2_DIMMB# <7>
111 VDD VDD 112
DDR_B_CAS# 113 114 M_ODT2
<8> DDR_B_CAS# CAS# ODT0 M_ODT2 <7>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C179
C186
C197
C213
C220
C183
C210
C199
C173
C218
C163
C177
1
10K_0402_5%
DDR_B_WE# 2 3 3 2 DDR_B_MA2 1 10K_0402_5%
R254
A RP23 C301 FOX_ASOA426-M2RN-7F A
56_0404_4P2R_5% RP21 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2
M_ODT3
3 4 1 M_ODT2
DDR_B_MA13
0.1U_0402_16V4Z
2
SO-DIMM B
1 4 3 2
STANDARD
2
56_0404_4P2R_5% RP9
4 1 DDR_B_BS#2 Bottom side
3 2 DDR_CKE2_DIMMB
56_0404_4P2R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 14 of 54
5 4 3 2 1
5 4 3 2 1
+CK_VDD_MAIN1
C371 2 1 CLK_PCI_PCM
+CK_VDD_DP
Stuff CLK_Ra CLK_Rb CLK_Rc 4.7P_0402_50V8C
CPU Driven R1389 C372 2 1 CLK_PCI_SIO
+3VS 1 2 4.7P_0402_50V8C
*(Default) No Stuff CLK_Rd CLK_Re CLK_Rf NOXDP@0_0805_5% 1
C1062
1
C734
1
C735
1 0.1U_0402_16V4Z
C736
C373 2 1 CLK_DEBUG_PORT
@ 5P_0402_50V8C
R1390
Stuff CLK_Rd CLK_Re CLK_Rf +VCCP 1 2
2
10U_0805_10V4Z
2
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2
Place crystal within
533MHz XDP@ 0_0805_5%
500 mils of CK410 C361 2 1
18P_0402_50V8J
1
+CK_VDD_DP +CK_VDD_MAIN1
No Stuff CLK_Ra CLK_Rb CLK_Rc U25
Y3 Routing the trace at least 10mil
16 57 CLK_XTAL_IN 14.31818MHZ_16P
VDD X1
Stuff CLK_Rd CLK_Rf
2
CK_VDD_48 10 56 CLK_XTAL_OUT 2 1
VDD48 X2
667MHz 1 C364 18P_0402_50V8J
No Stuff CLK_Ra CLK_Rb CLK_Rc +CK_VDD_DP
C742 5 VDDPCI
28 R1352 1 2 LP@0_0402_5%
SATACLKT
CLK_Re 0.1U_0402_16V4Z
2
24 VDDSRC
2 R1393 1 CLKIREF
SATACLKC 29 R1333 1 2 LP@0_0402_5%
@ 0_0402_5% 1 33
+VCCP C743 VDDSATA
1 41 52 CPU_BCLK 1 2 CLK_CPU_BCLK
VDDSRC CPUCLKT0 CLK_CPU_BCLK <4>
C1061 0.1U_0402_16V4Z R1070 24_0402_5%
2
CLK_Rb 33_0402_5%
@ R1113 CLK_PCI_TCG 2 1 R1140 PCI_CLK5 3 21 T92 PAD C741
<35> CLK_PCI_TCG **SEL_SATA2/PCICLK5 SRCCLKC1
33_0402_5% CLKREQB# 1 2 @ 1000P_0402_50V4Z
0_0402_5% +3VS CLK_PCI_PCM 2 1 R1141 PCI_PCM 6
<30> CLK_PCI_PCM PCICLK6
CLK_Re 33_0402_5% 26 PCIE_DOCK 1 2 CLK_PCIE_DOCK
CLK_PCIE_DOCK <38>
C744
2
SRCCLKT3
R1394 2 1@ 10K_0402_5% PCI_EC R1144 24_0402_5% CPU_XDP 1 2 @ 1000P_0402_50V4Z
27 PCIE_DOCK# 1 2 CLK_PCIE_DOCK#
B SRCCLKC3 CLK_PCIE_DOCK# <38> B
ICH_SMBDATA 54 R1145 24_0402_5% C745
+VCCP <4,13,14,23,26,28,30> ICH_SMBDATA SDATA CPU_XDP# 1 2 @ 1000P_0402_50V4Z
<4,13,14,23,26,28,30> ICH_SMBCLK ICH_SMBCLK 53 35 PCIE_ICH 1 2 CLK_PCIE_ICH
SCLK SATA2/SRCCLKT5 CLK_PCIE_ICH <26>
R1123 24_0402_5%
2
34 PCIE_ICH# 1 2 CLK_PCIE_ICH#
SATA2/SRCCLKC5 CLK_PCIE_ICH# <26>
R1128 R1126 24_0402_5%
R1120 2 1 NOXDP@10K_0402_5% +3VS
R1130 1K_0402_5% 13 2 1 CLKREQC#
DOTT_96MHz CLKREQC# <7>
8.2K_0402_5% R1142 NOXDP@0_0402_5%
1
CLK_Rc 4 GND
R1115 24_0402_5%
@ R1139
NOXDP@ : means just build when XDP function disable. 12 43 T93 PAD
0_0402_5% GND SRCCLKT8
CLK_Rf XDP@ : means just build when XDP function enable. 17 42 T94 PAD R1147 2 1 NOXDP@10K_0402_5% +3VS
2
GND SRCCLKC8
CLKREQD#
When this time, docking PCI express will not work. 58 GND 2 1
R1254 NOXDP@0_0402_5%
CLKREQD# <30>
47 44 CPU_XDP# 1 2 CLK_CPU_XDP#
+3VS GNDCPU *CPUCLKC2_ITP/CLKREQD# CLK_CPU_XDP# <4>
LCD(Low)/SRC(High) R1143 XDP@ 24_0402_5%
clock select Pin44/45 function select 25 GNDSRC SRCCLKT7 39 PCIE_MCARD 1 2 CLK_PCIE_MCARD
CLK_PCIE_MCARD <30>
R1249 24_0402_5%
1
@ 10K_0402_5%
R1108 R1245
2
CLK_ENABLE#
A 10K_0402_5% 10K_0402_5% ICS9LP306_TSSOP64 A
1
300_0402_5%
R1246 R1247
1 2
@ 10K_0402_5%
@ 10K_0402_5%
J29 Security Classification Compal Secret Data Compal Electronics, Inc.
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock generator
*High:Pin18/19 = 100MHz
Low:Pin18/19 = 96MHz
High:Pin44/45 = CLKREQ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
*Low:Pin44/45 = CPUCLK2_ITP DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-2951 1.0
F1 D18
CRT Connector 1
1.1A_6VDC_FUSE
2 2
CH491D_SC59
1 W=40mils BLUE_R
GREEN_R
RED_R
DAN217_SC59
DAN217_SC59
@ DAN217_SC59
1
C315
D19
D20
1
1
D4
0.1U_0402_16V4Z
2
<38> BLUE
JP2
<38> GREEN 6
1 R542 @ @ 1
11
RED_R +CRTVDD
<38> RED 1 2 1
3
BK1608LL560-T 7
18P_0402_50V8C
R543 12
1 2 GREEN_R 2
18P_0402_50V8C
C313
BK1608LL560-T 8
R544 13
C314
1 2 BLUE_R 3
BK1608LL560-T 9
18P_0402_50V8C
+5VS +5VS 14 16
C359 C370
1 1 1 4 17
C310
1 2 1 2 10
15
0.1U_0402_16V4Z 0.1U_0402_16V4Z 5 +3VS
2 2 2
SUYIN_070912FR015S207CR
5
1
U33
SN74AHCT1G125GW_SOT353-5 R545
P
OE#
2 4 HSYNC_G_A 1 2 D_HSYNC
<19> M_HSYNC A Y
2
2.2K_0402_5%
2.2K_0402_5%
0_0603_5%
5
1
D_HSYNC <38>
R2
R4
R546
P
OE#
3
2 4 VSYNC_G_A 1 2 D_VSYNC +CRTVDD +CRTVDD
<19> M_VSYNC A Y 0_0603_5%
1
G
U54
D_VSYNC <38>
1
R53 51K_0402_5%
R54 51K_0402_5%
3
C351 C352 R162 R183
2
2
Q46
G
Place close to docking connector
1
2 D_DDCDATA 2
<38> D_DDCDATA 1 3 DDC1_DATA <19>
S
2
RHU002N06_SOT323
G
D_DDCCLK 1 3
<38> D_DDCCLK DDC1_CLK <19>
S
Q52
RHU002N06_SOT323
TV-Out Connector
3 3
1
2
JP1
1
2
R547 C_LUMA 3
<19,38> LUMA 1 2 4
0_0603_5%
R548 C_CRMA 5
<19,38> CRMA 1 2 6
0_0603_5%
R549 C_COMP 7
<19,38> COMP 1 2
0_0603_5%
SUYIN_33007SR-07T1-C
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TVout Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 16 of 54
A B C D E
5 4 3 2 1
1 2
LCD POWER CIRCUIT LCDVDD +3VALW
C586 0.1U_0603_50V4Z
1 2 LCDVDD
C587 68P_0402_50V8J
S
1 3
D
1
JP35
R19 Q8
SI2301BDS_SOT23 R12
40 2 1
G
2
40 L76 @ KC FBM-L11-201209-221LMA30T_0805 100_0402_1%
39 39 1 2
D D
38 2 1
1 2
38 B+
37 L62 KC FBM-L11-201209-221LMA30T_0805 1M_0402_5%
37 D R474 C28
36 36
35 +3VS Q5 2 1 2 1 2
35 G
34 34
33 RHU002N06_SOT323 S 47K_0402_5% 1 1 0.047U_0402_16V7K 1
3
33 C29 C31 C20
32 32 LCDVDD
31 31
1
30 4.7U_0805_10V4Z @ 4.7U_0805_10V4Z
30 Q6 2 2 2
29 29 +5VS_INV
28 DTC124EK_SC59
28 BKLT_PWM ALS_EN <24>
27 27
26 2 0.1U_0402_16V4Z
26 DDC2_CLK <19> <19> M52_ENAVDD
25 25
24 DDC2_DATA <19>
24
23 23 TXCLK_U+ <19>
22 TXCLK_U- <19>
3
22
21 21
20 20 TXOUT_U2+ <19>
19 19 TXOUT_U2- <19>
18 18
17 17 TXOUT_U1+ <19>
16 Q53
16 TXOUT_U1- <19>
15 DTA114YKA_SC59
15
14 14 TXOUT_U0+ <19>
13 13 TXOUT_U0- <19>
12 12 +5VS 3 1 +5VS_INV
11
47K
11 TXOUT_L0- <19>
10K
10 10 TXOUT_L0+ <19>
9 9
8 +3VS
8 TXOUT_L1- <19>
7 TXOUT_L1+ <19>
2
C 7 U43A C
6 6
SN74LVC08APW_TSSOP14
14
5 5 TXOUT_L2- <19>
4 4 TXOUT_L2+ <19>
1
LID_SW# D
3 1
P
3 <26,37> LID_SW# A
2 3 2 Q36
2 TXCLK_L- <19> O
1 2 G BSS138_SOT23
1 TXCLK_L+ <19> <19> OPT_BL_ENA B
2
S
3
2
R360
7
ACES_88316-4000 100K_0402_5%
1
R501
1
@ 100K_0402_5%
Support 3V inverter
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 17 of 54
5 4 3 2 1
5 4 3 2 1
D D
U1A
PART 1 OF 6
PEG_M_TXP0 AE26 W21 PEG_M_RXP0 C968 0.1U_0402_16V4Z PEG_RXP0
PEG_M_TXN0 PCIE_RX0P PCIE_TX0P PEG_M_RXN0 C1032 0.1U_0402_16V4Z PEG_RXN0
AD26 PCIE_RX0N PCIE_TX0N V21
PEG_M_TXP3
X PEG_M_RXP3 C969 0.1U_0402_16V4Z PEG_RXP3
W26 T21
PEG_M_TXN3 V26
PCIE_RX3P
PCIE_RX3N
P PCIE_TX3P
PCIE_TX3N R21 PEG_M_RXN3 C1037 0.1U_0402_16V4Z PEG_RXN3
R CLK_PCIE_M52
PEG_M_TXP4 V25 E R22 PEG_M_RXP4 C1030 0.1U_0402_16V4Z PEG_RXP4
<15> CLK_PCIE_M52
<15> CLK_PCIE_M52#
CLK_PCIE_M52#
PCIE_RX4P PCIE_TX4P
PEG_M_TXN4 U25 PCIE_RX4N S PCIE_TX4N P22 PEG_M_RXN4 C972 0.1U_0402_16V4Z PEG_RXN4
S PEG_RXP[0..15]
<9> PEG_RXP[0..15]
PEG_M_TXP5 T26 P23 PEG_M_RXP5 C963 0.1U_0402_16V4Z PEG_RXP5
PEG_M_TXN5 PCIE_RX5P PCIE_TX5P PEG_M_RXN5 C1031 0.1U_0402_16V4Z PEG_RXN5 PEG_RXN[0..15]
R26 N23
PCIE_RX5N I PCIE_TX5N <9> PEG_RXN[0..15]
N <9> PEG_M_TXP[0..15]
PEG_M_TXP[0..15]
PEG_M_TXP6 R25 N21 PEG_M_RXP6 C947 0.1U_0402_16V4Z PEG_RXP6
PEG_M_TXN6 P25
PCIE_RX6P T PCIE_TX6P
M21 PEG_M_RXN6 C1040 0.1U_0402_16V4Z PEG_RXN6 PEG_M_TXN[0..15]
PCIE_RX6N PCIE_TX6N <9> PEG_M_TXN[0..15]
C
E C
PEG_M_TXP7 N26
R M22 PEG_M_RXP7 C1029 0.1U_0402_16V4Z PEG_RXP7
PCIE_RX7P PCIE_TX7P
PEG_M_TXN7 M26 PCIE_RX7N
F PCIE_TX7N L22 PEG_M_RXN7 C1028 0.1U_0402_16V4Z PEG_RXN7
A
PEG_M_TXP8 M25 PCIE_RX8P
C PCIE_TX8P L23 PEG_M_RXP8 C946 0.1U_0402_16V4Z PEG_RXP8
PEG_M_TXN8 PEG_M_RXN8 C1034 0.1U_0402_16V4Z PEG_RXN8
L25 PCIE_RX8N E PCIE_TX8N K23
Clock Calibration
CLK_PCIE_M52 AA22
CLK_PCIE_M52# PCIE_REFCLKP R1365 2K_0402_1%
Y22 PCIE_REFCLKN
PCIE_CALRN V19 1 2 PCIE_1.2V
PCIE_CALRP Y20 1 2
R1366 562_0402_1%
<26> VGA_RST# Y21 PERSTb PCIE_CALI W19 1 2
R1367 1.47K_0402_1%
AA21 PCIE_TEST
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M52-T PCIE interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 18 of 54
5 4 3 2 1
5 4 3 2 1
U1F
1 2
U1B R126 100_0402_5% PART 6 OF 6 R23 10K_0402_5%
PART 2 OF 6 1 2
R124 100_0402_5% Forward Control and External SSC AA8
VARY_BL BLON_PWM <17>
Integrated 1 2 AC8
Compatibility DIGON M52_ENAVDD <17>
D3 TMDS AD20 2 1
NC_MEMVMODE_0 GENERICD R661 4.7K_0402_5%
D2 NC_MEMVMODE_1 TXCM AF8 DVI_CLK- <38>
TXCP AE8 DVI_CLK+ <38>
TX0M AF9 DVI_TX0- <38> TXCLK_UP AB16 TXCLK_U+ <17>
TX0P AE9 DVI_TX0+ <38> TXCLK_UN AB15 TXCLK_U- <17>
V TX1M AE10 DVI_TX1- <38> TXOUT_U3P AC16
AE11 AC15
AE7 I TX1P
AF11
DVI_TX1+ <38> TXOUT_U3N
AA15
NC_DVOVMODE TX2M DVI_TX2- <38> TXOUT_U2P TXOUT_U2+ <17>
AA2 DVPCNTL_0 D TX2P AF12 DVI_TX2+ <38> TXOUT_U2N AA14 TXOUT_U2- <17>
AA3 1 2 AE17
D
AB2
DVPCNTL_1 E 1 2 R132 100_0402_5% TXOUT_U1P
AE16
TXOUT_U1+ <17> D
DVPCNTL_2 TXOUT_U1N TXOUT_U1- <17>
AC1 DVPCNTL_3 O R178 100_0402_5% LVDS channel
TXOUT_U0P AE15 TXOUT_U0+ <17>
AA1 DVPDATA_0 TXOUT_U0N AE14 TXOUT_U0- <17>
AA4 DVPDATA_1
AB3 DVPDATA_2
& TXOUT_L0N AD11 TXOUT_L0- <17>
AC2 VDD_PNL_PLL L22 AD12
DVPDATA_3 TXOUT_L0P TXOUT_L0+ <17>
AF3 1 2 +VDD25 T19 AE12
+2.5VS TXOUT_L1- <17>
+3VS AD1
DVPDATA_4
DVPDATA_5
M 0_0603_5% U8
VDD25_4
VDD25_5
TXOUT_L1N
TXOUT_L1P AE13 TXOUT_L1+ <17>
AB4 DVPDATA_6 U 1 1 W16 VDD25_6 TXOUT_L2N AB12 TXOUT_L2- <17>
AC3 AB13 TXOUT_L2+ <17>
AE2
DVPDATA_7
DVPDATA_8
L 1 C601 TXOUT_L2P
TXOUT_L3N AF15
AC4 T C600 AF14
DVPDATA_9 TXOUT_L3P
1
C168 2
2
AF5 AD9 AC12
R5 R3 AB5
DVPDATA_10 I TPVDD
AD8 0.001U_0402_50V7M TXCLK_LN
AC13
TXCLK_L- <17>
TXCLK_L+ <17>
DVPDATA_11 TPVSS 2 TXCLK_LP
2.2K_0402_5% 2.2K_0402_5% AD5 DVPDATA_12 M 1U_0402_6.3V4Z 10U_0805_10V4Z
LVDS AE3
AE4
DVPDATA_13 E AB10 216PLAKB11FG
2
DVPDATA_14 TXVDDR_1
AD2 DVPDATA_15 D TXVDDR_2 AB9 VDD_PNL_IO2.5
AD4 1
T1 PAD
AB6
DVPDATA_16 I AC10
T2 PAD DVPDATA_17 TXVSSR_1
<17> DDC2_DATA AE6 DVPDATA_18 A TXVSSR_2 AC9 C165
<17> DDC2_CLK AD7 DVPDATA_19 TXVSSR_3 AD10
2 1U_0402_6.3V4Z
<23> VRAM_ID0 AC6 DVPDATA_20
<23> VRAM_ID1 AE5 DVPDATA_21
<23> VRAM_ID2 AD6 DVPDATA_22
<23> VRAM_ID3 AB8 DVPDATA_23
AF23 M52_RED
DAC / CRT R M52_GRN
G AE23
L23 L18 AE22 M52_BLU
M52_RED M52_RED_L M_RED B
1 2 1 2 M_RED <38>
0_0603_5% MCI1608HQ39NJA_0603 AE21 M_HSYNC <16>
1 1 1
R180 R182 C182 C180 C181 AD19
AVDD AVDD_2.5
75_0402_1% 75_0402_1%
AVSSN AD18
2 2 2
Y18
2
AVSSQ
12P_0402_50V8J
R181 12P_0402_50V8J AA19
VDD1DI VDDDI_2.5
75_0402_1% 12P_0402_50V8J W6
<23> GPIO0 GPIO_0 General
<23> GPIO1 V6 GPIO_1 VSS1DI AA20
Purpose
Place those components as close T9 PAD
T22 PAD
Y3
W5
GPIO_2 I/O
GPIO_3 DAC2 (TV/CRT2)
as U1 within 500 mils. <23> GPIO4 Y4
V4
GPIO_4
<23> GPIO5 GPIO_5
2
R658
1
10K_0402_5%
T23 PAD Y2 GPIO_6 Place close to U1
<17> OPT_BL_ENA V5 GPIO_7_BLON H2SYNC AE20
W3 AF20 L5 1 2 LUMA <16,38>
<23> GPIO8 GPIO_8 V2SYNC
Y1 AF17 LUMA_M CHB1608U301_0603
<23> ROM_ID3 GPIO_9 Y_G
W2 AE18 CRMA_M
T8 PAD GPIO_10 C_R_PR
V1 L3 1 2 CRMA <16,38>
+3VS <23> ROM_ID0 GPIO_11
V3 AF18 COMP_M CHB1608U301_0603
<23> ROM_ID1 GPIO_12 COMP_B_PB
U4 R20 715_0402_1%
<23> ROM_ID2 GPIO_13
V2 AD17 1 2 L4 1 2 COMP <16,38>
GPIO_14 R2SET
1
1
R11 1 2 AB17 1 1 1 1 1 1
B A2VDD_2 VDD_DAC2.5 B
499_0402_1% R659 R185 R187 C14 C6 C30 C317 C316 C318
10K_0402_5% AC17 75_0402_1% 75_0402_1% 82P_0402_50V8J
2
2
<23> D+ AB7 216PLAKB11FG
DPLUS NC_A2VDDQ AB19 82P_0402_50V8J
AA7 DMINUS Thermal
<23> D-
1
1
18P_0402_50V8J C611 XXTALIN AF24 Interface
XTALIN
C610
2 2
AF25 XTALOUT
AC21
CRT R17
4.7K_0402_5%
R1
4.7K_0402_5%
DDC1DATA DDC1_DATA <16>
AB21 PLLTEST DDC1CLK AB20 DDC1_CLK <16>
R39
DVI
2
1 2 AD23 TESTEN DDC2DATA AA10 DVI_DAT <38>
1.1K_0402_5% Test AA9
R46 DDC2CLK DVI_CLK <38>
0_0402_5%
XOUT 8 3 R189
XOUT NC 75_0402_1%
1
2 VSS PD# 6
C612
Security Classification Compal Secret Data Compal Electronics, Inc.
2
ASM3P1819N-SR_SO8 @ 22P_0402_50V8J 1
2
2005/05/26 2006/07/26 Title
Issued Date Deciphered Date M52-T CRT/LVDS/TV-OUT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
C613 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.1U_0402_16V4Z DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 19 of 54
5 4 3 2 1
5 4 3 2 1
U1C
Part 3 of 6
MEMORY INTERFACE B
F18 DQB_7 MAB_7 E7
MDB8 F14 G6 MAB8
MDB9 DQB_8 MAB_8 MAB9
F13 DQB_9 MAB_9 F9
D MDB10 MAB10 D
E14 DQB_10 MAB_10 E8
MDB11 E13 F8 MAB11
MDB12 DQB_11 MAB_11 MAB12
F10 DQB_12 MAB_12 C6
MDB13 E10 F7 MAB13
MDB14 DQB_13 MAB_13 MAB14
F11 DQB_14 MAB_14 H7
MDB15 E11
MDB16 DQB_15
C20 DQB_16
MDB17 B19
MDB18 DQB_17 DQMB#0
B20 DQB_18 DQMBb_0 F17
MDB19 C19 F12 DQMB#1
MDB20 DQB_19 DQMBb_1 DQMB#2
C16 DQB_20 DQMBb_2 B18
MDB21 C17 B13 DQMB#3
MDB22 DQB_21 DQMBb_3 DQMB#4
B16 DQB_22 DQMBb_4 J5
MDB23 B17 J2 DQMB#5
MDB24 DQB_23 DQMBb_5 DQMB#6
B12 DQB_24 DQMBb_6 P5
MDB25 C15 P2 DQMB#7
MDB26 DQB_25 DQMBb_7
C11 DQB_26
MDB27 B15
MDB28 DQB_27
C14 DQB_28
MDB29 B11 E18 QSB0
MDB30 DQB_29 QSB_0 QSB1
B14 DQB_30 QSB_1 E12
MDB31 C12 C18 QSB2
MDB32 DQB_31 QSB_2 QSB3
F5 DQB_32 QSB_3 C13
MDB33 G5 J6 QSB4
MDB34 DQB_33 QSB_4 QSB5
H6 DQB_34 QSB_5 H3
MDB35 QSB6
read strobe
H5 DQB_35 QSB_6 P6
MDB36 K6 P3 QSB7
MDB37 DQB_36 QSB_7 QSB[7..0]
K5 DQB_37 <22> QSB[7..0]
MDB38 L6
MDB39 DQB_38
L5 DQB_39
MDB40 F2
MDB41 DQB_40 DQMB#[7..0]
G2 DQB_41 <22> DQMB#[7..0]
write strobe
C MDB42 C
H2 DQB_42
MDB43 G3 MDB[63..0]
DQB_43 <22> MDB[63..0]
MDB44 K2
MDB45 DQB_44 MAB[15..0]
L2 DQB_45 <22> MAB[15..0]
MDB46 J3
MDB47 DQB_46
K3 DQB_47
MDB48 M5
MDB49 DQB_48
M6 DQB_49
MDB50 N6
MDB51 DQB_50
N5 DQB_51
MDB52 R6 C9 CLKB0
DQB_52 CLKB0 CLKB0 <22>
MDB53 U5 B9 CLKB0#
DQB_53 CLKB0b CLKB0# <22>
MDB54 R5
MDB55 DQB_54 CKEB0
T5 DQB_55 CKEB B6 CKEB0 <22>
MDB56 M2
MDB57 DQB_56 RASB#0
M3 DQB_57 RASBb C5 RASB#0 <22>
MDB58 N2
MDB59 DQB_58 CASB#0
N3 DQB_59 CASBb E6 CASB#0 <22>
VDD_MEM18 MDB60 R2
MDB61 DQB_60 WEB#0
R3 DQB_61 WEBb C4 WEB#0 <22>
MDB62 T2 DQB_62
1
MDB63 T3 B5 CSB0#
DQB_63 CSBb_0 CSB0# <22>
R51 F6 CSB1#
CSBb_1 CSB1# <22>
100_0402_1%
B4 CLKB1
CLKB1 <22>
2
1 C10
R55 0.1U_0402_16V4Z
100_0402_1%
B 2 B
E3
2
VDD_MEM18 TEST_MCLK
E5 TEST_YCLK
1
E2 MEMTEST
1
R56 R223
100_0402_1% 4.7K_0402_5%
R221
4.7K_0402_5% 216PLAKB11FG
2
1
2
R112
243_0603_1%
1
1
R57
2
100_0402_1% C8
0.1U_0402_16V4Z
2
2
M52@ R51,R55,C10,R56,R57,C8,R223,R221,R112
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M52-T MEM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 20 of 54
5 4 3 2 1
U1E 5 4 3 2 1
Part 5 of 6 U1D
PART 4 OF 6 L2
A25 CHB1608U301_0603
PCIE_VSS_1 VDD_MEM18 PCIE_PVDD_12
AB22 PCIE_VSS_2 A12 VDDR1_1 PCIE_PVDD_12_1 AA24 2 1
AB25 G19 C119 A15 AB23 1 1 1 1
PCIE_VSS_3 VSS_1 0.01U_0402_16V7K VDDR1_2 PCIE_PVDD_12_2
AC22 PCIE_VSS_4 VSS_2 A10 A18 VDDR1_3 PCIE_PVDD_12_3 AB24
AC26 A13 1 1 A21 AC23 C109 C113 C107 C143
PCIE_VSS_5 VSS_3 VDDR1_4 PCIE_PVDD_12_4
B24 PCIE_VSS_6 VSS_4 A16 A3 VDDR1_5
C124 2 2 2 2
B26 PCIE_VSS_7 VSS_5 A19 A6 VDDR1_6 PCIE_VDDR_12_10 N19
C23 A2 0.01U_0402_16V7K A9 N20 1000P_0402_50V7K 22U_0805_6.3V4Z
PCIE_VSS_8 VSS_6 2 2 VDDR1_7 PCIE_VDDR_12_11 1U_0402_6.3V7K 0.1U_0402_16V4Z
C24 PCIE_VSS_9 VSS_7 A7 C1 VDDR1_8 PCIE_VDDR_12_12 P19
D22 PCIE_VSS_10 VSS_8 AC5 D11 VDDR1_9 PCIE_VDDR_12_13 P20
D D
D24 PCIE_VSS_11 VSS_9 AC7 D13 VDDR1_10 PCIE_VDDR_12_14 R19 PCIE_VDD12
D25 PCIE_VSS_12 VSS_10 AE1 D15 VDDR1_11 PCIE_VDDR_12_15 T20
E24 PCIE_VSS_13 VSS_11 AF2 D17 VDDR1_12 PCIE_VDDR_12_16 U20
F23 PCIE_VSS_14 VSS_12 B1 D19 VDDR1_13 PCIE_VDDR_12_17 L19
0.1U_0402_16V4Z 0.1U_0402_16V4Z L21
PCI-Express
F24 PCIE_VSS_15 VSS_13 B21 D5 VDDR1_14 PCIE_VDDR_12_18 L20
G22 C10 D8 CHB1608U301_0603
PCIE_VSS_16 VSS_14 VDDR1_15 1U_0402_6.3V7K
G24 PCIE_VSS_17 VSS_15 C21 1 1 1 1 E1 VDDR1_16 PCIE_VDDR_12_1 AC24 2 1 PCIE_1.2V
G25 D12 C98 C99 C101 C102 E4 AC25 1 1 1 1
PCIE_VSS_18 VSS_16 1000P_0402_50V7K VDDR1_17 PCIE_VDDR_12_2
H20 PCIE_VSS_19 VSS_17 D14 F20 VDDR1_18 PCIE_VDDR_12_3 AD25
H21 D16 G12 AE25 C116 C112 C117 C108
PCIE_VSS_20 VSS_18 2 2 2 2 VDDR1_20 PCIE_VDDR_12_4
Memory I/O
H24 D18 G15 J19 0.1U_0402_16V4Z
PCIE_VSS_21 VSS_19 1000P_0402_50V7K VDDR1_21 PCIE_VDDR_12_5 2 2 2 2
J23 PCIE_VSS_22 VSS_20 D20 G18 VDDR1_22 PCIE_VDDR_12_6 J20
J24 D21 G4 K19 22U_0805_6.3V4Z 1000P_0402_50V7K
PCIE_VSS_23 VSS_21 VDDR1_23 PCIE_VDDR_12_7
K22 PCIE_VSS_24 VSS_22 D4 G9 VDDR1_24 PCIE_VDDR_12_8 K20
K24 D6 0.1U_0402_16V4Z 0.1U_0402_16V4Z H1 M19
PCIE_VSS_25 VSS_23 VDDR1_25 PCIE_VDDR_12_9 0.1U_0402_16V4Z 0.1U_0402_16V4Z
K25 PCIE_VSS_26 VSS_24 D7 H12 VDDR1_26 1 VDD_CORE
L21 PCIE_VSS_27 VSS_25 D9 1 1 1 1 H15 VDDR1_27 PCIE_PVSS AA23 1 1 1 1 1
L24 E21 C135 C136 C85 H18 +
PCIE_VSS_28 VSS_26 VDDR1_28
PCI-Express GND
Core
R20 H10 1 1 1 N8 N13 C24 C22 C82 C27 C38
PCIE_VSS_37 VSS_35 VDDR1_37 VDDC_9
R23 PCIE_VSS_38 VSS_36 H13 C129 C130 C131 R1 VDDR1_38 O VDDC_10 N14
2 2 2 2 2
R24 H16 R7 P13
T22
PCIE_VSS_39
PCIE_VSS_40
VSS_37
VSS_38 H17 0.1U_0402_16V4Z
2 2 2
1000P_0402_50V7K R8
VDDR1_39
VDDR1_40 W VDDC_11
VDDC_12 P14 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
T24 H4 T6 P15
T25
PCIE_VSS_41
PCIE_VSS_42
VSS_39
VSS_40 J1 0.1U_0402_16V4Z VDDR1_41 E VDDC_13
VDDC_14 R12 1 1 1 1
C C
U21
U24
PCIE_VSS_43 VSS_41 K4
L13 R VDDC_15 R14
R15 C240 C245 C246 C244
PCIE_VSS_44 VSS_42 VDDC_16
V20 PCIE_VSS_45 VSS_43 L15 VDDC_17 R16
2 2 2 2
V23 PCIE_VSS_46 VSS_44 L3 VDDC_18 T11
V24 M1 T15 0.1U_0402_16V4Z 10U_0805_10V4Z
PCIE_VSS_47 VSS_45 VDDC_19 0.1U_0402_16V4Z 0.1U_0402_16V4Z
W22 PCIE_VSS_48 VSS_46 M14 VDDC_20 T16
W23 M16 W11 0.1U_0402_16V4Z
PCIE_VSS_49 VSS_47 VDDC_21 M52_VDD25 0.1U_0402_16V4Z 2
W24 PCIE_VSS_50 VSS_48 M4 VDDC_22 W9 1 +2.5VS
W25 M7 Y11 1 1 1 1 L1
PCIE_VSS_51 VSS_49 VDDC_23
Y23 PCIE_VSS_52 VSS_50 M8 VDDC_24 Y9
Y24 N11 M52_VDDR 0.01U_0402_16V7K 0.1U_0402_16V4Z V8 C134 C118 C121 C97 CHB1608U301_0603
PCIE_VSS_53 VSS_51 VDDR3_1
VSS_52 N15 1 1 1 1 1 W15 VDDR3_2 VDD25_1 H11
2 2 2 2
P1 W17 H14
I/O Internal
VSS_53 C110 C114 C111 C106 C115 VDDR3_3 VDD25_2 0.01U_0402_16V7K 0.1U_0402_16V4Z
VSS_54 P12 W18 VDDR3_4 VDD25_3 H19
P16 2.2U_0603_6.3V6K W7 K8
VSS_55 2 2 2 2 2 VDDR3_5 VDD25_4
VSS_56 P4 Y15 VDDR3_6 VDD25_5 P8
P7 Y17 W13 M52_VDDPLL
VSS_57 0.1U_0402_16V4Z 0.1U_0402_16V4Z VDDR3_7 VDDPLL M52_VDDC 1U_0402_6.3V7K
VSS_58 R11 VDDCI_1 L14 2 1
R13 N16 1 1 1 1 1 L63 CHB1608U301_0603
VSS_59 VDDCI_2
I/0
R4 P11 C100
VSS_60 VDDCI_3 C104 C103 C105 C144
VSS_61 T12 VDDCI_4 T13
T14 @ R137 0_0402_5% AA5 22U_0805_6.3V4Z
VSS_62 VDDR4_1 2 2 2 2 2
VSS_63 T4 2 1 +3VS AA6 VDDR4_2
T8 AD3 AD15 1U_0402_6.3V7K 1U_0402_6.3V7K 0.1U_0402_16V4Z
VSS_64 VDDR4_3 LPVDD VDD_PNL_PLL
VSS_65 U3 Y6 VDDR4_4 1
U6 Q34 AA11
VSS_66 LVDDR C169
U7 AA12
CORE GND VSS_67 LVDDR 1U_0402_6.3V4Z
S
W10 1 3 AA13
D
VSS_68 LVDDR 2
VSS_69 W12
W14 SI2301BDS_SOT23 1
W8 R138 AB11
G
VDD_PNL_IO2.5
2
Clock
I/O
Memory
VSS_74 Y8 1 L7 VDDRH1
1
C123 VDD_PNLIO2.5
0.1U_0402_16V4Z
216PLAKB11FG 2
J7 VSSRH1
1
<36,39,40,49,50> PWR_GD 2
G 216PLAKB11FG
S Q20
3
RHU002N06_SOT323
PLACE ALL CAPS ON THIS PAGE CLOSE TO ASIC M52_VDDPLL 2 1 PCIE_1.2V
L17
1 1 1 CHB1608U301_0603
C172 C141
C140 10U_0805_10V4Z
0.1U_0402_16V4Z 1U_0402_6.3V4Z
2 2 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M52-T POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 21 of 54
5 4 3 2 1
5 4 3 2 1
G10
G10
H10
D11
D10
D10
D11
H10
K10
B11
B11
K10
F10
F10
J10
J10
G5
G5
H5
D9
D6
D5
D4
D4
D5
D6
D9
H5
K5
E9
E6
B4
B4
E6
E9
K5
F5
F5
J5
J5
U67 U68
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
MDB27 B7 N5 MAB0 N5 B7 MDB56
MDB25 DQ0 A0 MAB1 A0 DQ0 MDB57 QSB[7..0]
C6 DQ1 A1 N6 N6 A1 DQ1 C6 <20> QSB[7..0]
MDB30 B6 M6 MAB2 M6 B6 MDB59
MDB28 DQ2 A2 MAB3 A2 DQ2 MDB58 DQMB#[7..0]
B5 DQ3 A3 N7 N7 A3 DQ3 B5 <20> DQMB#[7..0]
MDB24 C2 N8 MAB4 N8 C2 MDB60
MDB31 DQ4 A4 MAB5 A4 DQ4 MDB61 MDB[63..0]
Place VREF divider and CAP D3 DQ5 A5 M9 M9 A5 DQ5 D3 <20> MDB[63..0]
D MDB26 MAB6 MDB63 D
close to memory D2 DQ6 A6 N9 N9 A6 DQ6 D2
MDB29 E2 N10 MAB7 N10 E2 MDB62 MAB[15..0]
DQ7 A7 A7 DQ7 <20> MAB[15..0]
MDB15 K13 N11 MAB8 N11 K13 MDB42
VDD_MEM18 MDB10 DQ8 A8/AP MAB9 A8/AP DQ8 MDB47
K12 DQ9 A9 M8 M8 A9 DQ9 K12
MDB13 J13 L6 MAB10 L6 J13 MDB43
MDB11 DQ10 A10 MAB11 A10 DQ10 MDB45
J12 DQ11 A11 M7 M7 A11 DQ11 J12
1
1
G4 VDDQ NC L12 L12 NC VDDQ G4
G11 VDDQ NC L13 L13 NC VDDQ G11 VDD_MEM18
J4 M3 M3 J4 R1371 R1372
VDDQ NC CSB1# NC VDDQ 56_0402_5% 56_0402_5%
J11 VDDQ CS1# M4 M4 CS1# VDDQ J11
K4 N3 N3 K4
2
VDDQ NC NC VDDQ
K11 VDDQ VDDQ K11
VSS E7 E7 VSS 1
D7 VDD VSS E8 E8 VSS VDD D7
D8 E10 E10 D8 C998
VDD VSS VSS VDD 470P_0402_50V7K
E4 VDD VSS K6 K6 VSS VDD E4
2
E11 VDD VSS K7 K7 VSS VDD E11
L4 VDD VSS K8 K8 VSS VDD L4
L7 VDD VSS K9 K9 VSS VDD L7
L8 VDD VSS L5 L5 VSS VDD L8
L11 VDD VSS L10 L10 VSS VDD L11
VSS E5 E5 VSS Place close to U68
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
CLKB1
CLKB1#
HY5DU573222AFM-33_FBGA144 HY5DU573222AFM-33_FBGA144
J9
J8
J7
J6
H9
H8
H7
H6
G9
G8
G7
G6
F9
F8
F7
F6
F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9
1
R1375 R1376
56_0402_5% 56_0402_5%
B B
2
Place close to U68
Place close to U67 C999
1
VDD_MEM18 470P_0402_50V7K
VDD_MEM18 2
1U_0603_10V6K 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1U_0603_10V6K 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 C1004
C1013
C1000 C1001 C1002 C1003 C1005 C1006 C1007 C1008
C1009 C1010 C1011 C1012 C1014 C1015 C1016 C1017 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2
0.1U_0402_16V4Z 1000P_0402_50V7K 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z 1000P_0402_50V7K 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z
VDD_MEM18
VDD_MEM18
1U_0603_10V6K 0.01U_0402_16V7K
1U_0603_10V6K 0.1U_0402_16V4Z
1 1 1 1 1
1 1 1 1 1 C1022
C1027
C1018 C1019 C1020 C1021
C1023 C1024 C1025 C1026 2 2 2 2 2
2 2 2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_6.3V6M
0.1U_0402_16V4Z 1000P_0402_50V7K 10U_0805_6.3V6M
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M52-T VRAM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 22 of 54
5 4 3 2 1
5 4 3 2 1
+2.5VS
+3VS
1
2 2 2
1
1 2 R144 C258
R148 @ 4.7K_0402_5% 0.1U_0402_16V4Z
0_0402_5% R703
@ 10K_0402_5% L9
2
CHB1608U301_0603
M52_THERM# <19>
2
2 1 VDD_PNL_PLL
1
C 1 1 1
2 Q12 (40mA 2.5V)
B @ PMST3904_SOT323 C212 C256
E 10U_0805_10V4Z 0.001U_0402_50V7M
3
2 2 2
C259
0.1U_0402_16V4Z
+3VS 1 2 L12
THERM_SCI# <4,26>
R154 @ 10K_0402_5% R173 CHB1608U301_0603
1 2 0_0402_5% 2 1
<19> GPIO0 AVDD_2.5
1 1 1
R152 @ 10K_0402_5% (65mA 2.5V)
1 2 C209 C208
<19> GPIO1 10U_0805_10V4Z 0.001U_0402_50V7M
R6 2 2 2
R149 @ 10K_0402_5%
1 2 1 2 STRAPS PIN DESCRIPTION OF RECOMMENDED SETTING RECOMMENDED C225
<19> GPIO4
0.1U_0402_16V4Z
C R174 10K_0402_5% @ 2.2K_0402_5% C
1 2 TX_PWRS_ENB GPIO0 FULL SWING 1 L13
<19> GPIO5
CHB1608U301_0603
2 1 VDDDI_2.5
TX_DEEMPH_EN GPIO1 TRANSMITTER DE-EMPHASIS ENABLE 1 1 1
- TX DE-EMPHASIS DISABLED FOR MOBILE 0 (40mA 2.5V)
R157 @ 10K_0402_5% C216 C214
1 2 10U_0805_10V4Z 0.001U_0402_50V7M
<19> GPIO8 2 2 2
DEBUG_ACCESS GPIO4 Strap to set the debug muxes to bring out
DEBUG signals even if registers are inaccessible 0 C215
0.1U_0402_16V4Z
R153 @ 10K_0402_5%
1 2 FORCE_COMPLIANCE GPIO8 Force chip to get to compliance state 0 L11
<19> ROM_ID0
queckly for tester pruposes CHB1608U301_0603
R150 @ 10K_0402_5% 2 1 VDD_PNLIO2.5
<19> ROM_ID1 1 2 1 1
No ROM , with 128M frame buffer 0 0 0 X (200MA 2.5V)
R155 F64@ C221 C224
1 2 10K_0402_5% GPIO 10U_0805_10V4Z 0.1U_0402_16V4Z
<19> ROM_ID2 0 1 0 X 2 2
ROMIDCFG(3:0) (9,13,12,11) No ROM , with 64M frame buffer
R156 @ 10K_0402_5%
<19> ROM_ID3 1 2
L14
CHB1608U301_0603
2 1 VDD_DAC2.5
R158 @ 10K_0402_5% (130mA 2.5V)
1 1 1
<19> VRAM_ID0 1 2
C217 C222
10U_0805_10V4Z 0.1U_0402_16V4Z
R159 @ 10K_0402_5% 2 2 2
1 2 Samsung 8Mx32 1.8V F die K4D553235F-VC33 0 0 0 0 C223
B <19> VRAM_ID1 B
VRAM_ID[0:3] 0.1U_0402_16V4Z
R165 Hynix 16Mx32 1.8V HY5DS113222FMP-28 0 0 0 1
1 2 DVPDATA
<19> VRAM_ID2 Hynix 8Mx32 1.8V HY5DS573222F-33 0 0 1 0
128M@ 10K_0402_5% (20,21,22,23)
R165 0 0 1 1
VDD_MEM18
R166 0 1 0 1 L16 L66
CHB1608U301_0603 CHB1608U301_0603
2 1 VDD_MEM_CLK PCIE_1.2V 2 1 PCIE_VDD12
1 1 1 1 1
C196 C198 C190 C195
10U_0805_10V4Z 0.1U_0402_16V4Z 22U_0805_6.3V4Z 1U_0402_6.3V4Z
2 2 2 2 2
A C194 A
0.001U_0402_50V7M
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
M52-T Filters / Strap
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 23 of 54
5 4 3 2 1
5 4 3 2 1
D D
+5VS
+3VS
2
R433
R1041 1 2 8.2K_0402_5% PCI_DEVSEL#
330_0402_5%
R1042 1 2 8.2K_0402_5% PCI_STOP#
1
ALS_EN
ALS_EN <17>
R1043 1 2 8.2K_0402_5% PCI_TRDY#
1
D
R1044 1 2 8.2K_0402_5% PCI_FRAME# <30> PCI_AD[0..31] U26B ALS_EN# 2
PCI_AD0 E18 D7 PCI_REQ0# G Q45
AD0 REQ0# PCI_REQ0#
R1045 1 2 8.2K_0402_5% PCI_PLOCK# PCI_AD1 C18 E7 PCI_GNT0# S
PCI_GNT0#
3
AD1 GNT0#
R1046 1 2 8.2K_0402_5% PCI_IRDY#
PCI_AD2
PCI_AD3
A16
F18
AD2 PCI REQ1# C16
D16
PCI_REQ1# RHU002N06_SOT323
5
PCI_AD12 B12 U56
PCI_AD13 AD12 PCI_CBE#0 PCI_PCIRST#
C13 B15 1
P
AD13 C/BE0# PCI_CBE#0 <30> B
PCI_AD14 G15 C12 PCI_CBE#1 4 PCI_RST#
AD14 C/BE1# PCI_CBE#1 <30> Y PCI_RST# <25,30>
PCI_AD15 G13 D12 PCI_CBE#2 2
AD15 C/BE2# PCI_CBE#2 <30> A
G
PCI_AD16 E12 C15 PCI_CBE#3
AD16 C/BE3# PCI_CBE#3 <30>
PCI_AD17 C11 @ TC7SH08FU_SSOP5
3
PCI_AD18 AD17 PCI_IRDY# R1051
D11 AD18 IRDY# A7 PCI_IRDY# <30>
C PCI_AD19 PCI_PAR 0_0402_5% C
A11 AD19 PAR E10 PCI_PAR <30>
PCI_AD20 A10 B18 PCI_PCIRST# 2 1
PCI_AD21 AD20 PCIRST# PCI_DEVSEL#
F11 AD21 DEVSEL# A12 PCI_DEVSEL# <30>
+3VS PCI_AD22 F10 C9 PCI_PERR#
AD22 PERR# PCI_PERR# <30> +3VS
PCI_AD23 E9 E11 PCI_PLOCK#
PCI_AD24 AD23 PLOCK# PCI_SERR#
D9 AD24 SERR# B10 PCI_SERR# <30,36>
R1052 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD25 B9 F15 PCI_STOP#
AD25 STOP# PCI_STOP# <30>
5
PCI_AD26 A8 F14 PCI_TRDY# U59
AD26 TRDY# PCI_TRDY# <30>
R1053 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD27 A6 F16 PCI_FRAME# PCI_PLTRST# 1
P
AD27 FRAME# PCI_FRAME# <30> B
PCI_AD28 C7 4 PLT_RST#
AD28 Y PLT_RST# <7,25,26,28,30,36>
R1054 1 2 8.2K_0402_5% PCI_PIRQC# PCI_AD29 B6 C26 PCI_PLTRST# 2
AD29 PLTRST# A
G
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH <15>
R1055 1 2 8.2K_0402_5% PCI_PIRQD# PCI_AD31 D6 B19 PCI_PME# @ TC7SH08FU_SSOP5
PCI_PME#
3
AD31 PME#
R1056 1 2 8.2K_0402_5% PCI_PIRQE# R1057
2
R1065
@10_0402_5%
1
1
C729
@ 8.2P_0402_50V
2
1K_0402_5%
BIOS_SEL1 Short Open
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(1/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 24 of 54
5 4 3 2 1
5 4 3 2 1
C516
+3VS
C641 Multi Bay II connector
1 2 ICH_RTCX1 1 2
15P_0402_50V8J
<24> IDE_RESET# JP5
0.1U_0402_16V4Z
14
1
1 1
4
R432 12 R301 2
P
Y4 A 2
O 11 2 1 ODD_RST# 3 3
10M_0402_5% PLT_RST_B# 2 1 13 33_0402_5% 4
B 4
G
U26A R1036 0_0402_5% 5 ODD_RST#
LPC_AD[0..3] <30,34,35,36>
2
32.768KHZ_12.5P_MC-146 U43D 5 PD_D8
6
7
6
RTC
AB1 AA6 LPC_AD0 SN74LVC08APW_TSSOP14 7 PD_D7
C528 ICH_RTCX2 RTXC1 LAD0 LPC_AD1 7 PD_D9
1 2 AB2 RTCX2 LAD1 AB5 <24,30> PCI_RST# 2 1 8 8
15P_0402_50V8J AC4 LPC_AD2 R1037 @ 0_0402_5% 9 PD_D6
D R230 1 ICH_RTCRST# AA3 LAD2 LPC_AD3 9 PD_D10 D
+RTCVCC 2 RTCRST# LAD3 Y6 10 10
LPC
20K_0402_5% 11 PD_D5
R1026 11
ICH_INTVRMENW4 AC3 LPC_DRQ#0 12 PD_D11
INTVRMEN LDRQ0# LPC_DRQ#0 <34> 12
CMOS_CLR1 +RTCVCC 1 2 SM_INTRUDER#Y5 AA5 PAD T88 13 PD_D4
1M_0402_5% INTRUDER# LDRQ1# / GPIO23 13 PD_D12
1 2 14 14
AB3 LPC_FRAME# 15 PD_D3
LFRAME# LPC_FRAME# <30,34,35,36> 15
NO SHORT PADS W1 16 PD_D13
EE_CS 16 PD_D2
Y1 EE_SHCLK 2 1 R1243 10K_0402_5% +3VS 17 17
C287 Y2 AE22 GATEA20 18 PD_D14
EE_DOUT A20GATE GATEA20 <36> 18
LAN
1U_0603_10V4Z W3 AH28 H_A20M# 19 PD_D1
EE_DIN A20M# H_A20M# <4> 19
CPU
1 2 20 PD_D15
H_CPUSLP_R# 20 PD_D0
V3 LAN_CLK CPUSLP# AG27 PAD T86 21 21
22 PD_DREQ
C721 R1028 DPRSLP# R1025 2 22
U3 LAN_RSTSYNC TP1 / DPRSTP# AF24 1 0_0402_5% H_DPRSTP# <4,49> 23 23
2 1 1 2 AH25 DPSLP# R1035 2 1 0_0402_5% 24 PD_IOR#
TP2 / DPSLP# H_DPSLP# <4> 24
@ 10_0402_5% U5 R1027 2 1 56_0402_5% +VCCP 25 PD_IOW#
@ 10P_0402_25V8K LAN_RXD0 H_FERR# 25
V4 LAN_RXD1 FERR# AG26 H_FERR# <4> 26 26
T5 27 PD_IORDY
33_0402_5% 1 LAN_RXD2 27
<37> AC97_BITCLK_MDC 2 R1314 GPIO49 / CPUPWRGD AG24 H_PWRGOOD
H_PWRGOOD <4> 28 28 PD_DACK#
U7 29 PD_IRQ
33_0402_5% 1 LAN_TXD0 H_IGNNE# 29
<31> AC97_BITCLK_CODEC 2 R371 V6 LAN_TXD1 IGNNE# AG22 H_IGNNE# <4> 30 30
V7 AG21 FWH_INIT# 31 PD_A1
LAN_TXD2 INIT3_3V# FWH_INIT# 31
<37> AC97_SYNC_MDC 33_0402_5% 1 2 R402 AF22 H_INIT# 32
INIT# H_INIT# <4> +3VS +VCCP 32
AF25 H_INTR 33 PD_A0
INTR H_INTR <4> 33
<31> AC97_SYNC_CODEC 33_0402_5% 2 1 R376 34 PD_A2
34
AC-97/AZALIA
AC97_BITCLK U1 R1244 2 1 10K_0402_5% 35 PD_CS#1
33_0402_5% 1 ACZ_BCLK 35
<37> AC97_RST#_MDC 2 R1315 AC97_SYNC R6 ACZ_SYNC RCIN# AG23 KB_RST#
KB_RST# <36> 36 36 PD_CS#3
37 MB2_LED#
37
1
<31> AC97_RST#_CODEC 33_0402_5% 2 1 R1029 AC97_RST# R5 AF23 H_SMI# 38
ACZ_RST# SMI# H_SMI# <4> 38
AH24 H_NMI R1030 39
NMI H_NMI <4> +3VS 39
AC97_SDIN0 T2 40
<31> AC97_SDIN0 ACZ_SDIN0 40
AC97_SDIN1 T3 AH22 2 1 H_STPCLK# 56_0402_5% 41
C <37> AC97_SDIN1 ACZ_SDIN1 STPCLK# H_STPCLK# <4> 41 C
T1 R1408 0_0402_5% 42 +5VS_MB
2
ACZ_SDIN2 42
1
+5VS +3VS AF26 THRMTRIP_ICH# 1 2 43
THERMTRIP# H_THERMTRIP# <4,7> 43
<31> AC97_SDOUT_CODEC 33_0402_5% 2 1 R367 AC97_SDOUT T4 R1031 24.9_0402_1% R72 44
ACZ_SDOUT 4.7K_0402_5% 44 MBAY_DET#
45 45
<37> AC97_SDOUT_MDC 33_0402_5% 2 1 R405 AH17 PD_A0 Place close to ICH7 46
SATA_LED# DA0 PD_A1 46
AF18 AE17 47
2
SATALED# DA1 47
1
AF17 PD_A2 48
DA2 48
1
R88 MBAY_DET# 49
<26> MBAY_DET# 49
R90 10K_0402_5% SATA_RXN0_C AF3 AE16 PD_CS#1 1 50 R1032
10K_0402_5% SATA_RXP0_C SATA0RXN DCS1# PD_CS#3 C628 50 0_0402_5%
AE3 SATA0RXP DCS3# AD16 55 GND 51 51
SATA_TXN0_C AG2 56 52
2
SATA0TXN GND 52
SATA
SATA_TXP0_C AH2 0.1U_0402_16V4Z 57 53
2
SATA0TXP PD_D0 2 GND 53
DD0 AB15 58 GND 54 54
SATA_LED# 1 2 IDE_LED# AF7 AE14 PD_D1
D16 CH751H-40_SC76 IDE_LED# <30> SATA2RXN DD1 PD_D2
AE7 SATA2RXP DD2 AG13
AG6 AF13 PD_D3 JAE_WM2M054JKB
MB2_LED# SATA2TXN DD3 PD_D4 +5VS +5VS_MB
1 2 AH6 SATA2TXP DD4 AD14 Q92
D15 CH751H-40_SC76 AC13 PD_D5 +5VS
CLK_PCIE_SATA# AF1 DD5 PD_D6 AO4407_SO8
<15> CLK_PCIE_SATA# SATA_CLKN DD6 AD12
CLK_PCIE_SATA AE1 AC12 PD_D7 1 8
<15> CLK_PCIE_SATA SATA_CLKP DD7
AE12 PD_D8 2 7
R1256 DD8 PD_D9
AH10 SATARBIASN DD9 AF12 3 6 1 1
1
1 2 AG10 AB13 PD_D10 1 5 C625
SATARBIASP DD10 PD_D11 R83 C640
DD11 AC14
24.9_0402_1% AF14 PD_D12 470K_0402_5%
4
DD12 PD_D13 10U_0805_10V4Z C624 2 2
DD13 AH13
2
IDE AH14 PD_D14
R93
10U_0805_10V4Z
2
+3VALW +RTCVCC 4.7K_0402_5% 2 DD14
+3VS 1 R1033 PD_IORDY AG16 IORDY DD15 AC15 PD_D15 0.1U_0402_16V4Z
8.2K_0402_5% 2 1 R1034 PD_IRQ AH16 IDEIRQ 1 2
PD_DACK# AF16 DDACK#
1
PD_IOW# PD_DREQ D
AH15 DIOW# DDREQ AE15 220K_0402_5% 1C633
1
PD_IOR# AF15 2
B DIOR# <26> MB_PWR B
R1263 R1240 G
Q38 S 0.1U_0402_16V4Z
3
@ 332K_0402_1% 332K_0402_1% ICH7_BGA652~D RHU002N06_SOT323 2
2
ICH_INTVRMEN +5VS_MB
+3VL JP42
1
1
2
-
D14 1 1
R133
@ 0_0402_5% S1 3 C626 C627
GND
1
S2 SATA_TXP0 1 2 1
SATA CONN
2
1 2
TX+ 2
GND S7 D
C955 3900P_0402_50V7K 2
SATA_TXN0_C 1 2 SATA_TXN0
3.3V P1
P2 Q39
G
S
Place close to JP37
3
C956 3900P_0402_50V7K 3.3V RHU002N06_SOT323
3.3V P3
SATA_TXP0_C 1 2 SATA_TXP0 P4 +3VS
GND
GND P5
GND P6
5V P7
P8
Near ICH7(U26) side. 5V
14
5V P9 +5VS
GND P10
P11 4
P
Rsv <7,24,26,28,30,36> PLT_RST# A
P12 1 1 1 6 PLT_RST_B# PLT_RST_B# <30,34,35> ZZZ ZZZ
GND C630 C631 O
12V P13 5 B
G
A 0.1U_0402_16V4Z A
12V P14
P15 U43B 7
C957 3900P_0402_50V7K 12V C629 2 2 2 SN74LVC08APW_TSSOP14
SATA_RXN0_C 1 2 SATA_RXN0 10U_0805_10V4Z
GND
GND
boss
boss
24
23
HDD_HALTLED# <30>
Place closely pin B2 Place closely pin AC1
1
D CLK_48M_ICH CLK_14M_ICH
+3VALW +3VALW HDD_HALTLED 2 Q43
2
G RHU002N06_SOT323
1
R213,R233 change from 2.2Kohm to R1437 S
L
3
100K_0402_5% R997 R998
1
10Kohm when Q23,Q24,R206,R204 stuffed.
2
R213 R233 @ 10_0402_5% @ 10_0402_5%
1
R1000 R1001
2
2.2K_0402_5% 2.2K_0402_5% U26C
10K_0402_5% 10K_0402_5% R1319 1 1
2
ICH_SMBCLK 1 2 0_0402_5% ICH_SMB_CLK C22 AF19 C706 C707
MB_PWR <25>
1
D ICH_SMBDATA ICH_SMB_DATA SMBCLK GPIO21 / SATA0GP HDD_HALTLED D
1 2 0_0402_5% B22 SMBDATA GPIO19 / SATA1GP AH18
SMB
SATA
GPIO
R1320 LINKALERT# A26 AH19 @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C
ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP 2 2
B25 SMLINK0 GPIO37 / SATA3GP AE19 1 2
+3VS ICH_SMLINK1 A25 R1002 100_0402_5%
SMLINK1
+3VALW
R1003 AC1 CLK_14M_ICH
CLK14 CLK_14M_ICH <15>
Clocks
1 2 ICH_RI# A28 B2 CLK_48M_ICH
RI# CLK48 CLK_48M_ICH <15>
R206 R204 8.2K_0402_5%
SB_SPKR A19
<31> SB_SPKR SPKR
@ 2.2K_0402_5% @ 2.2K_0402_5% LPC_PD# A27 C20 ICH_SUSCLK T67 PAD
<35,36> LPC_PD# SUS_STAT# SUSCLK
2 Q23 <4> XDP_DBRESET# XDP_DBRESET# A22
2
SYS_RST#
SYS
@ RHU002N06_SOT323 B24 SLP_S3#
SLP_S3# SLP_S3# <28,30,31,32,36,38,39,46,47,48>
PM_BMBUSY# AB18 D23 SLP_S4#
<7> PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4# SLP_S4# <47>
S
D
ICH_SMBDATA 3 1 ICH_SMB_DATA F22 SLP_S5#
<4,13,14,15,23,28,30> ICH_SMBDATA SLP_S5# SLP_S5# <39,47>
OCP# B23 R1011
<4,50> OCP# GPIO11 / SMBALERT#
D
ICH_SMBCLK 3 1 ICH_SMB_CLK AA4 PM_POK R1010 8.2K_0402_5%
<4,13,14,15,23,28,30> ICH_SMBCLK PWROK PM_POK <7,36>
H_STP_PCI# 2 10K_0402_5%
G
AC20 1 2 1
POWER MGT
<15> H_STP_PCI# +3VALW
2
GPIO18 / STPPCI#
GPIO
Q24 H_STP_CPU# AF21 AC22 DPRSLPVR
<15> H_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR DPRSLPVR <7,49>
G @ RHU002N06_SOT323 D58
2 +5VS <30> WXMIT_OFF# A21 GPIO26 TP0 / BATLOW# C21 ICH_LOW_BAT# 2 1 LOW_BAT# <36>
R1005 2 1 XDP_DBRESET# <7,49> VGATE_INTEL R1374 1 2 0_0402_5% PWROK_ICH7 R1015 need be removed when ICH7M ES2 samples used,
200_0402_1%
<7,36> PM_POK R1373 1 2 @ 0_0402_5% but need be stuffed when ICH7M ES1 samples used.
R1006 1 2 OCP# U26D
10K_0402_5% PCIE_RXN1 F26 V26 DMI_RXN0
<28> PCIE_RXN1 PERn1 DMI0RXN DMI_RXN0 <7>
PCIE_RXP1 F25 V25 DMI_RXP0
<28> PCIE_RXP1 PERp1 DMI0RXP DMI_RXP0 <7>
R1009 1 2 LID_SW# <28> PCIE_TXN1 0.1U_0402_16V4Z 2 1 C708 PCIE_C_TXN1 E28 PETn1 DMI0TXN U28 DMI_TXN0
DMI_TXN0 <7>
PCI-EXPRESS
K26 AB26 DMI_RXN2
PERn3 DMI2RXN DMI_RXN2 <7>
R1007 R1008 K25 AB25 DMI_RXP2
PERp3 DMI2RXP DMI_RXP2 <7>
J28 AA28 DMI_TXN2
PETn3 DMI2TXN DMI_TXN2 <7>
10K_0402_5% 10K_0402_5% J27 AA27 DMI_TXP2
D57 PETp3 DMI2TXP DMI_TXP2 <7>
2
T25 PERn6
R1292/R1293 should be placed T24 F1 USB20_N0 USB_OC#3 4 5
9 VGARST# L R28
PERp6 USBP0N
F2 USB20_P0
USB20_N0 <33>
USB_OC#0 3 6
+3VALW
P
A less than 100 mils from U26. PETn6 USBP0P USB20_P0 <33>
8 R27 G4 USB20_N1 USB_OC#1 2 7
<18> VGA_RST# O PETp6 USBP1N USB20_N1 <30>
10 PLT_RST# 47_0402_5% G3 USB20_P1 USB_OC#2 1 8
B PLT_RST# <7,24,25,28,30,36> USBP1P USB20_P1 <30>
G
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(3/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 26 of 54
5 4 3 2 1
5 4 3 2 1
+VCCP
U26F U26E
A4 VSS[0] VSS[98] P28
ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
Vcc1_05[2] L12 B1 VSS[2] VSS[100] R11
AD17 V5REF[2] Vcc1_05[3] L14 1 1 B8 VSS[3] VSS[101] R12
Vcc1_05[4] L16 1 1 B11 VSS[4] VSS[102] R13
+1.5VS ICH_V5REF_SUS F6 L17 C974 C975 + + C979 B14 R14
V5REF_Sus Vcc1_05[5] VSS[5] VSS[103]
Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
D 0.1U_0402_16V4Z @ 330U_D2E_2.5VM_R9 D
AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B20 VSS[7] VSS[105] R16
2 2 2 2
150U_D_6.3VM
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 VSS[8] VSS[106] R17
+5VS +3VS AB22 P11 C670 B28 R18
1 1 1 Vcc1_5_B[3] Vcc1_05[9] VSS[9] VSS[107]
C570
+ C672 C673 C674 AB23 P18 C2 T6
Vcc1_5_B[4] Vcc1_05[10] 1U_0603_10V4Z 220U_D2_2VM_R9 VSS[10] VSS[108]
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 C6 VSS[11] VSS[109] T12
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P23 Vcc1_5_B[35] Vcc3_3[13] B13 H4 VSS[42] VSS[139] AA1
0.1U_0402_16V4Z R22 B16 1 1 1 H5 AA24
2 Vcc1_5_B[36] Vcc3_3[14] VSS[43] VSS[140]
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H24 VSS[44] VSS[141] AA25
C685
C686
C687
R24 Vcc1_5_B[38] Vcc3_3[16] C10 H27 VSS[45] VSS[142] AA26
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 VSS[46] VSS[143] AB4
2 2 2
R26 Vcc1_5_B[40] Vcc3_3[18] F9 J1 VSS[47] VSS[144] AB6
+3VS T22 G11 J2 AB11
Vcc1_5_B[41] Vcc3_3[19] VSS[48] VSS[145]
T23 Vcc1_5_B[42] Vcc3_3[20] G12 J5 VSS[49] VSS[146] AB14
T26 Vcc1_5_B[43] Vcc3_3[21] G16 J24 VSS[50] VSS[147] AB16
T27 Vcc1_5_B[44] J25 VSS[51] VSS[148] AB19
1 T28 Vcc1_5_B[45] VccRTC W5 +RTCVCC J26 VSS[52] VSS[149] AB21
C688 U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3VALW K27 VSS[54] VSS[151] AB27
0.1U_0402_16V4Z V22 1 1 1 1 K28 AB28
2 Vcc1_5_B[48] VSS[55] VSS[152]
C691
C692
V23 A24 C689 C690 L13 AC2
Vcc1_5_B[49] VccSus3_3[2] VSS[56] VSS[153]
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L15 VSS[57] VSS[154] AC5
W23 D19 0.1U_0402_16V4Z 0.1U_0402_16V4Z L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 Vcc1_5_B[52] VccSus3_3[5] D22 L25 VSS[59] VSS[156] AC11
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L26 VSS[60] VSS[157] AD1
M3 VSS[61] VSS[158] AD3
+1.5VS +1.5VS_DMIPLLR +1.5VS_DMIPLL
B27 Vcc3_3[1] VccSus3_3[7] K3 +3VALW M4 VSS[62] VSS[159] AD4
R991 R992 K4 1 1 M5 AD7
VccSus3_3[8] VSS[63] VSS[160]
0.01U_0402_16V7K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(4/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 27 of 54
5 4 3 2 1
5 4 3 2 1
J7 1 2
Layout Notice : Place as close
PAD-NO SHORT 2x2m
<7,24,25,26,30,36> PLT_RST# +3VALW chip as possible.
D
3 1 V_3P3_LAN
V_3P3_LAN Q31
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SI2301BDS_SOT23
R275 1 2 1K_0402_5% ICH_LAN_SMBCLK R1396 1 2 @ 0_0402_5% ICH_SMBCLK R267
G
ICH_SMBCLK <4,13,14,15,23,26,30> 2 2 2 2 2
2
R289 1 2 1K_0402_5% ICH_LAN_SMBDATA R1398 1 2 @ 0_0402_5% ICH_SMBDATA ICH_SMBDATA <4,13,14,15,23,26,30>
C324
C41
C39
C32
C44
4.7K_0402_5%
R1419
3
S
R1420
2
U7A
G
R268 2 1 1 1 1 1
2 1 2 1
BCM5753
D @ 0_0402_5% 47K_0402_5% D
LAN_TX3+ 220K_0402_5%
C12 LAN_TX3+ <29>
1
TRD3+ LAN_TX3-
D
C13 LAN_TX3- <29> NIC_PD <29>
1
TRD3-
1
D12 LAN_TX2+ LAN_TX2+ <29> Q40
TRD2+
1
R277 LAN_TX2- D
2 1 10K_0402_5% J10 D13 AO7407_SOT323 R1397
Media
GPIO0_TST_CLKOUT TRD2- LAN_TX2- <29>
5751_GPIO1 J12 E12 LAN_TX1+ LAN_TX1+ <29> 2 LP_EN#
GPIO1 TRD1+ LAN_TX1- @ 0_0402_5% G
ICH_LAN_SMBCLK D9 TRD1- E13
LAN_TX0+
LAN_TX1- <29>
PLT_RST_LAN# Q94
Must having maximized
F12 S
LAN_TX0+ <29>
L
3
ICH_LAN_SMBDATA D8 SMB_CLK TRD0+ LAN_TX0- RHU002N06_SOT323 copper under pin 2 & 4 of Q13
SMB_DATA TRD0- F13 LAN_TX0- <29>
5751_EECLK H10 V_3P3_LAN V_1P2_LAN
EECLK
1
5751_EEDAT D BCP69_SOT223
J11 EEDATA
Misc
2 Q13 4
Control
R1039 <36,43,44,45,50> ADP_PRES
F11 G REGSUP12 3 2
Power
SI LOM_LOW_PWR 1 Q30
E10 J5 2 S
3
SO LOW_PWR RHU002N06_SOT323 2 2 2 1
1
4.7K_0402_5% D C347 C55 C68
D10 SCLK
<26,30,31,32,36,38,39,46,47,48> SLP_S3# 2 C228
1
G 0.1U_0402_16V4Z 10U_0805_10V4Z
REGSUP12 Q29 1 1 1 2
D11 L13 S
3
CS# REGSUP12 VAUX_1.2_CTL RHU002N06_SOT323 4.7U_0805_10V4Z VAUX_1.2_CTL 0.1U_0402_16V4Z
K12
Regulator
REGCTL12
K13
Control
REGSEN12 V_1P2_LAN
N13 V_2P5_LAN NIC_PD
REGOUT25
M13 V_3P3_LAN
REGSUP25 V_3P3_LAN
2
G
Support LOM_PCIE_WAKE# 1 3 ICH_PCIE_WAKE# <26,30>
Hot Plug PCIE_C_RXN1 C17 1
D
N4 2
S
PCIE_TXDN PCIE_RXN1 <26> 2 2
V_3P3_LAN H2 0.1U_0402_16V4Z Q103 C348 C83
C PWR_IND# PCIE_C_RXP1 C18 1 AO7407_SOT323 C
J2 ATTN_IND# PCIE_TXDP M4 2 PCIE_RXP1 <26>
1 2 B3 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z
R73 4.7K_0402_5% ATTN_BTTN# 1 1
PCIE_RXDN M8 PCIE_TXN1 <26> 1 2
@ 0_0402_5% R1091
PCIE_RXDP N8 PCIE_TXP1 <26>
B5 LOM_PCIE_WAKE#
PCI-E
WAKE# CLK_PCIE_LOM#
REFCLK- M6
CLK_PCIE_LOM
CLK_PCIE_LOM# <15>
NIC_PD_N L Place close U6 pin M13
REFCLK+ N6 CLK_PCIE_LOM <15>
C4 2 1 V_3P3_LAN R1082
REFCLK_SEL R36 4.7K_0402_5% 1 2
100K_0402_5%
1
LANLINK_STATUS# B10 D7 1 2 D Q104
<26,29,38> LANLINK_STATUS# LINKLED# PCIE_TST V_2P5_LAN
LED
1
C6 S 0_0402_5% 1
3
TCK R1089 R1088
TDI G4 2 1
C5 1 2 C74 + C976
TEST
TDO V_3P3_LAN
F4 0_0402_5%
TMS 0.1U_0402_16V4Z 100U_B2_6.3VM
E5 1 2 +3VS
2
TRST# R1090 1 2 2
2 1 V_3P3_LAN @ 0_0402_5%
R14 200_0402_1%
1
Y1 XTALO N10 C243
XTALO
Clock
R1085 @10U_0805_10V4Z
Bias
B9 10K_0402_5%
XTALI RDAC
1 2 M10 XTALI NIC_PD#
1 2
2
V_3P3_LAN
25MHZ_20P_1BG25000CK1A D C580 L Place close U6 pin N13
B BCM5753MKFBG_P31_FPBGA196 R70 NIC_PD Q105 B
2 2 2 1 2
C16 C19 G RHU002N06_SOT323
Layout Notice : No high 1.21K_0402_1% S 0.1U_0402_16V4Z
1
5
27P_0402_50V8J 27P_0402_50V8J
1 1 speed signal should be U36 R503
P
routed near RDAC or on LOM_LOW_PWR 4 2 1 2
<26> LOM_LOW_PWR O I
adjacent layer to RDAC 1 NC
G
V_3P3_LAN 100K_0402_5%
C9 @ SN74LVC1G17DBVR_SOT23-5
3
2 1 1
C576
0.1U_0402_16V4Z
1
1
1K_0402_5%
1K_0402_5%
1K_0402_5%
0.1U_0402_16V4Z
2
R16
R35
R34
1
1 A0 VCC 8
2
2
AT24C64AN-10SU-2.7_SO8 R507 10K_0402_5%
5 1
1
@ 0_0402_5% D
1
P
3
SN74LVC1G17DBVR_SOT23-5 2 RHU002N06_SOT323
3
0.1U_0402_16V4Z U55
1
1
A A
R1392 R1403
@ 2.2K_0402_5% @ 2.2K_0402_5% CKT Notice : CABLE IN, CABLE_DETECT=0
CABLE OUT, CABLE_DETECT=1
Q96 @ RHU002N06_SOT323
2
Q93 @ RHU002N06_SOT323
S
ICH_SMBDATA 3 1 ICH_LAN_SMBDATA
Security Classification Compal Secret Data Compal Electronics, Inc.
S
BCM5751M
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
G
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
2
+5VS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 28 of 54
5 4 3 2 1
5 4 3 2 1
LAN_TX0- 12
T66
TD4- MX4- 13 MDO0- RJ-45 CONN. Layout Notice : 1.2V filter. Place as close
chip as possible.
V_2P5_LAN
+3VS
LAN_TX0+ 11 14 MDO0+ V_2P5_LAN V_1P2_LAN
TD4+ 1:1 MX4+
2
2 1 TRM_CT 10 15 MCT0 2 R269 1
TCT4 MCT4 NIC_PD <28>
C330 75_0402_1% R871
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.01U_0402_16V7K LAN_TX1- 9 16 MDO1-
TD3- MX3-
2
10K_0402_5%
G
2 2 2 2 2 2 2 2 2 2 2 2
C65
C15
1
C341
C334
C340
C335
C336
C343
C337
C338
C66
C61
VMAINPRSNT 1 3 VMAINPRSNT_R
D D
S
LAN_TX1+ MDO1+ Q106 @ AO7407_SOT323 1 1 1 1 1 1 1 1 1 1 1 1
8 TD3+ 1:1 MX3+ 17
C333
2 1 TRM_CT 7 18 MCT1 2 R270 1 1 2
C327 TCT3 MCT3 75_0402_1% 1 2
0.01U_0402_16V7K LAN_TX2- 6 19 MDO2- 1000P_1808_3KV7K 0_0402_5% R1040
TD2- MX2-
LAN_TX2+ 5 20 MDO2+
TD21+ 1:1 MX2+
2 1 TRM_CT 4 21 2 R271 1
C328 TCT2 MCT2 75_0402_1%
0.01U_0402_16V7K LAN_TX3- 3 22 MDO3- V_1P2_LAN U7B
TD1- MX1-
E6 VDDC_0
BCM5753 VSS_0 A3
E7 VDDC_1 VSS_1 A8
Layout Notice : Filter place as close E8 VDDC_2 VSS_2 A12
LAN_TX3+ 2 23 MDO3+ E9 A14
TD1+ 1:1 MX1+ C320
chip as possible. VDDC_3 VSS_3
J6 VDDC_4 VSS_4 B1
2 1 TRM_CT 1 24 2 R272 1 1 2 J7 C1
C329 TCT1 MCT1 75_0402_1% VDDC_5 VSS_5
J9 VDDC_6 VSS_6 C3
0.01U_0402_16V7K 24HST1041-3 1000P_1808_3KV7K K5 C11
V_3P3_LAN VDDC_7 VSS_7
VSS_8 F1
A2 VDDIO_0 VSS_9 F5
0.1U_0402_16V4Z 1 2 C56 R50 1 2 49.9_0402_1% LAN_TX0- V_2P5_LAN A6 F6
LAN_TX0- <28> VDDIO_1 VSS_10
R63 1 2 49.9_0402_1% LAN_TX0+ LAN_TX0+ <28> A10 F7
VDDIO_2 VSS_11
Digial power
0.1U_0402_16V4Z 1 2 C54 R45 1 2 49.9_0402_1% LAN_TX1- LAN_TX1- <28> R985 B4 F8
R48 1 49.9_0402_1% LAN_TX1+ VDDIO_3 VSS_12
2 LAN_TX1+ <28> 2 1 XTALVDD D3 VDDIO_4 VSS_13 F9
0.1U_0402_16V4Z 1 2 C50 R42 1 2 49.9_0402_1% LAN_TX2- LAN_TX2- <28> 0_0603_5% 2 E11 F10
VDDIO_5 VSS_14
C
R44 1 2 49.9_0402_1% LAN_TX2+ LAN_TX2+ <28> C35 G2 VDDIO_6 GND VSS_15 G5
C
0.1U_0402_16V4Z 1 2 C49 R40 1 2 49.9_0402_1% LAN_TX3- LAN_TX3- <28> H11 G6
R41 1 49.9_0402_1% LAN_TX3+ 0.1U_0402_16V4Z VDDIO_7 VSS_16
2 LAN_TX3+ <28> K3 VDDIO_8 VSS_17 G7
1
M2 VDDIO_9 VSS_18 G8
R986 P12 G9
V_3P3_LAN XTALVDD V_2P5_LAN VDDIO_10 VSS_19
2 1 AVDD1 VSS_20 G10
0_0603_5% 2 B6 H6
C60 VDDP_0 VSS_21
Layout Notice : Place H4 VDDP_1 VSS_22 H7
termination as close as M12 VDDP_2 VSS_23 H8
0.1U_0402_16V4Z J13 H9
BCM5751M as possible 1 1K_0402_5% 1 R276 LAN_AUXPWR XTALVDD VSS_24
2 C7 VAUXPRSNT VSS_25 J1
R987 VMAINPRSNT H12 M3
VMAINPRSNT VSS_26
2 1 AVDD2 L5 PCIE_SDSVDD VSS_27 M7
0_0603_5% 2 N1
C46 VSS_28
PCIE_SDS_VDD A1 NC_0 VSS_29 N7
A4 NC_1 VSS_30 P11
0.1U_0402_16V4Z A5 P14
1 NC_2 VSS_31
A7 NC_3
A9 NC_4 DC_0 A11
V_1P2_LAN B2 A13
NC_5 DC_1
B7 NC_6 DC_2 B14
L33 B8 C14
JP4 NC_7 DC_3
2 1 AVDDL C8 NC_8 DC_4 D6
V_3P3_LAN_LED R266 2 1 300_0402_5% 13 BLM11A601S_0603 2 2 D1 D14
Yellow LED+ C342 C339 NC_9 DC_5
D2 NC_10 DC_6 E3
LAN_ACT# 14 D4 E14
<28,38> LAN_ACT# Yellow LED- NC_11 DC_7
16 4.7U_0805_10V4Z 0.1U_0402_16V4Z D5 F14
MDO3- SHLD1 1 1 V_3P3_LAN NC_12 DC_8
<38> MDO3- 8 PR4- E1 NC_13 DC_9 G14
DETECT PIN1 9 E2 NC_14 DC_10 H5
MDO3+ 7 CABLE_DETECT <26,28> L32 E4 H14
<38> MDO3+ PR4+ NC_15 DC_11
Disconnected
2 1 F2 J8
Don't care
GPHY_PLLVDD NC_16 DC_12
MDO1- 6 BLM11A601S_0603 2 2 R284 F3 J14
<38> MDO1- PR2- NC_17 DC_13
1 C331 C332 G1 K4
B MDO2- C579 @ 4.7K_0402_5% NC_18 DC_14 B
<38> MDO2- 5 PR3- G3 NC_19 DC_15 K6
4.7U_0805_10V4Z 0.1U_0402_16V4Z H1 K7
1
MDO2+ 0.1U_0402_16V4Z 1 1 NC_20 DC_16
<38> MDO2+ 4 PR3+ T59 H3 NC_21 DC_17 K8
2
J3 NC_22 DC_18 K9
MDO1+ 3 L30 J4 K10
<38> MDO1+ PR2+ NC_23 DC_19
2 1 PCIE_PLLVDD K1 NC_24 DC_20 K14
MDO0- 2 BLM11A601S_0603 2 2 K2 L6
<38> MDO0- PR1- PAD NC_25 DC_21
10 C323 C326 K11 L10
MDO0+ DETCET PIN2 NC_26 DC_22
<38> MDO0+ 1 PR1+ 4.7U_0805_10V4Z 0.1U_0402_16V4Z L T59 , T60 place together L1 NC_27 DC_23 L12
SHLD1 15 L2 NC_28 DC_24 L14
R265 2 1 1
V_3P3_LAN_LED 1 300_0402_5% 11 Green LED+ L3 NC_29 DC_25 M11
L29 V_3P3_LAN L4 M14
LANLINK_STATUS# NC_30 DC_26
<26,28,38> LANLINK_STATUS# 12 Green LED- 2 1 PCIE_SDS_VDD L8 NC_31 DC_27 N5
BLM11A601S_0603 1 2 R285 1 2 @ 4.7K_0402_5% L9 N11
FOX_JM36113-P1122-7F C322 C325 NC_32 DC_28
L11 NC_33 DC_29 N12
T60 M1 N14
4.7U_0805_10V4Z 0.1U_0402_16V4Z PAD NC_34 DC_30
M5 NC_35 DC_31 P3
2 1 R287 1 2 @ 4.7K_0402_5% M9 NC_36 DC_32 P4
N2 NC_37 DC_33 P5
N3 NC_38 DC_34 P6
R286 1 2 @ 4.7K_0402_5% N9 P7
NC_39 DC_35
P1 NC_40 DC_36 P8
P2 NC_41 DC_37 P9
DC_38 P10
AVDDL G11 AVDDL_0 DC_39 P13
G12 AVDDL_1 Analog
B12
V_3P3_LAN V_3P3_LAN_LED AVDD1
G13
AVDD_0 power
AVDD2 AVDD_1 V_2P5_LAN
S
L8
D
3 1 PCIE_PLLVDD L7 PCIE_PLLVDD
GPHY_PLLVDD H13 GPHY_PLLVDD PLL BIAS BIASVDD B13 BIASVDD_LAN 1 2
1
Q60 1 BLM11A601S_0603
A R525 SI2301BDS_SOT23 BCM5753MKFBG_P31_FPBGA196 C63 A
G
2
100K_0402_5% 0.1U_0402_16V4Z
2
2
D
2
<26,31,38> PREP#
Q61
G Security Classification Compal Secret Data Compal Electronics, Inc.
S Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
3
RHU002N06_SOT323
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Magnetic & RJ45/RJ11
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 29 of 54
5 4 3 2 1
A B C D E
15 15 16 16 PLT_RST# <7,24,25,26,28,36>
PCI_AD27 17 18 PCI_AD30 DEBUG@0_0402_5%
PCI_AD25 17 18 PCI_AD28 DEBUG@0_0402_5%
19 19 20 20
21 22 PCI_AD26 DEBUG@0_0402_5%
<24> PCI_CBE#3 21 22 JP44
PCI_AD23 23 24 PCI_AD24
PCI_AD21 23 24 ICH_PCIE_WAKE#
25 25 26 26 PCM_SPK <31> <26,28> ICH_PCIE_WAKE# 1 1 2 2
27 28 PCI_AD22 CH_DATA 3 4
27 28 <33> CH_DATA 3 4
PCI_AD19 29 30 PCI_AD20 CH_CLK 5 6
29 30 <33> CH_CLK 5 6
PCI_AD17 31 32 <15> CLKREQD# 1 2 CLKREQD#_MC 7 8 R1413 1 2 LPC_FRAME# <25,34,35,36>
PCI_CBE#2 31 32 PCI_PAR R1336 0_0402_5% 7 8 R1414 LPC_AD3
<24> PCI_CBE#2 33 33 34 34 PCI_PAR <24> 9 9 10 10 1 2
PCI_IRDY# 35 36 PCI_AD18 CLK_PCIE_MCARD# 11 12 R1415 1 2 LPC_AD2
<24> PCI_IRDY# 35 36 <15> CLK_PCIE_MCARD# 11 12
37 38 PCI_AD16 CLK_PCIE_MCARD 13 14 R1416 1 2 LPC_AD1
<26,34,35,36> PM_CLKRUN# 37 38 <15> CLK_PCIE_MCARD 13 14
PCI_SERR# 39 40 PCI_FRAME# 15 16 R1417 1 2 LPC_AD0
<24,36> PCI_SERR# 39 40 PCI_FRAME# <24> 15 16
PCI_PERR# 41 42 PCI_TRDY# PLT_RST_B# 1 2 17 18
<24> PCI_PERR# 41 42 PCI_TRDY# <24> <25,34,35> PLT_RST_B# 17 18 LPC_AD[0..3] <25,34,35,36>
PCI_CBE#1 43 44 PCI_STOP# R1412 DEBUG@0_0402_5% 19 20 XMIT_OFF#
<24> PCI_CBE#1 43 44 PCI_STOP# <24> <15> CLK_DEBUG_PORT 19 20
45 46 PCI_DEVSEL# R1348 0_0402_5% 21 22 0_0402_5%
45 46 PCI_DEVSEL# <24> 21 22 PLT_RST_B# <25,34,35>
PCI_AD14 47 48 PCI_AD15 <26> PCIE_RXN2 PCIE_RXN2 1 2 PCIE_C_RXN2 23 24 R1363 1 2 V_3P3_LAN
PCI_AD12 47 48 PCIE_RXP2 PCIE_C_RXP2 25 23 24 R1364
49 49 50 50 <26> PCIE_RXP2 1 2 25 26 26 1 2 +3VS
PCI_AD10 51 52 PCI_AD13 R1349 0_0402_5% 27 28 @ 0_0402_5%
PCI_AD8 51 52 PCI_AD11 27 28
53 53 54 54 29 29 30 30 ICH_SMBCLK <4,13,14,15,23,26,28>
PCI_AD7 55 56 PCI_AD9 PCIE_TXN2 31 32
55 56 <26> PCIE_TXN2 31 32 ICH_SMBDATA <4,13,14,15,23,26,28>
PCI_AD5 57 58 PCI_CBE#0 PCIE_TXP2 33 34
PCI_AD3 57 58 PCI_AD6 PCI_CBE#0 <24> <26> PCIE_TXP2 33 34
59 59 60 60 35 35 36 36
PCI_AD1 61 62 PCI_AD4 37 38
61 62 PCI_AD2 37 38
63 63 64 64 39 39 40 40
65 66 PCI_AD0 41 42 WW_LED#
<26> HDD_HALTLED# 65 66 41 42 WW_LED# <35>
+3VL 67 68 43 44 WL_LED#
67 68 43 44 WL_LED# <35>
69 70 +3VL R1418 1 2 DEBUG@ 0_0402_5% 45 46 WP_LED#
<35,37> WL_BLUE_LED# 69 70 IRRX <34> 45 46 WP_LED# <35>
71 72 R1358 1 2 DEBUG@ 0_0402_5% 47 48
2 <36> GREEN_BATLED# 71 72 IRTXOUT <34> <36,37,38> STB_LED# 47 48 2
73 74 R1353 1 2 DEBUG@ 0_0402_5% 49 50
<36> AMBER_BATLED# 73 74 IRMODE <34> <36,37> NUM_LED# 49 50
75 76 R1360 1 2 DEBUG@ 0_0402_5% 51 52
<36,37,38> STB_LED# 75 76 <36,37> CAPS_LED# 51 52
77 78 SC_CD#
<25> IDE_LED# 77 78 SC_CD# <33> +3VALW
79 80 SC_FCB 53 54
79 80 SC_FCB <33> GND1GND2
CLK_48M_CB +3VS 81 82 SC_CLK
81 82 SC_CLK <33> +3VALW +3V_MINI +3VS
83 84 SC_RST Q41 MOLEX 67910-0002 52P
83 84 SC_RST <33>
1
85 85 86 86 +SC_PWR
1
R106 +5VS 87 88 SC_DATA @ SI2301BDS_SOT23
87 88 SC_DATA <33>
@ 10_0402_5% 89 90 SC_RFU L78 R517
89 90 SC_RFU <33>
1
S
D
3 1 1 2
R516 @ 100K_0402_5%
2
1 91 92 FBMA-L11-201209-102LMA10T
R519
2
GND GND @ 10K_0402_5% XMIT_OFF#
G
93 94
2
C142 GND GND
95 96 1 2
2
GND GND
1
@18P_0402_50V8J @ 100K_0402_5% D
1
2 D
<26> XMIT_OFF 2
88020-90101 <26,28,31,32,36,38,39,46,47,48> SLP_S3# 2 G
G Q58 S
3
Q42 S @ RHU002N06_SOT323
3
@ RHU002N06_SOT323
1 2
R1422 0_0402_5%
+1.5VS +3VS
19
11
7 7 8 8
3
9 10 UIM_DATA U64
0.1U_0402_16V4Z 9 10 UIM_CLK +3VS_ACL_IO
11 12
Vdd
Vdd
Vdd_IO
11 12 UIM_RST
13 13 14 14
15 16 UIM_VPP +3VS 2 1 18 6
15 16 U72 Reserved2 RDY/INT ACCEL_INT <24>
17 18 R1357 0_0402_5%
17 18 M_WXMIT_OFF# +3VS_ACL
19 19 20 20 1 CH1 CH4 6
21 21 22 22 PLT_RST_B# <25,34,35> 2 1 20 Reserved3
23 24 1 2 +3VALW 2 5 R1359 0_0402_5% 9
23 24 R1382 @ 0_0402_5% Vn Vp SDO
25 25 26 26
27 27 28 28 1 2 +3VS 3 CH2 CH3 4 4 Reserved1
+3VS 29 30 R1383 0_0402_5%
29 30
1
31 32 S DIO(BR) NUP4301MR6T1 TSOP-6 +3VS 10
31 32 SDA/SDI/SDO ICH_SMBDATA <4,13,14,15,23,26,28>
33 34 R1361
33 34
35 35 36 36 USB20_N1 <26> 1 NC1 ICH_SMBCLK <4,13,14,15,23,26,28>
37 38 D13 0_0402_5% 7
37 38 USB20_P1 <26> NC2
1 2 39 40 JP50 8 12
2
R1071 39 40 NC3 SCL/SPC +3VS_ACL
1 20_0603_5% 41 41 42 42 WW_LED#
WW_LED# <35> 3 14 NC4
R1073 0_0603_5% 43 44 4 1 UIM_PWR 1 15 R1362
43 44 UIM_VPP GND VCC UIM_RST NC5
45 45 46 46 5 VPP RST 2 2 21 NC6 CS 13 1 2
47 48 UIM_DATA 6 3 UIM_CLK 22 10K_0402_5%
47 48 I/O CLK NC7
49 49 50 50 DAN217_SC59 23 NC8 R1391
51 51 52 52 SUYIN_254021MA006G100ZL 24 NC9
+3VS_ACL
0.1U_0402_16V4Z
25 NC10 CK 16 1 2
53 GND1GND2 54 26 NC11
PADDLE
1 1 27 0_0402_5%
MOLEX 67910-0002 52P C554 C960 NC12
28
GND
GND
GND
NC13
1 1 1
4.7U_0805_10V4Z C994 C995 C996
2 2 LIS3LV02DQ_QFN28
29
17
@ 0.01U_0402_16V7K 10U_0805_10V4Z
D66 2 2 2
@
4 +3VS 1 2 M_WXMIT_OFF# 4
<26> WXMIT_OFF# CH751H-40_SC76 0.1U_0402_16V4Z
SW1
2 1BD002-1101L_4P
1 1 2 Must be placed in the center of the system.
D65 CH751H-40_SC76
1
1
C986 R521
4 3
2
1K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
2
0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Mini-Card/Mini-PCI/Accelerometer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 30 of 54
A B C D E
A B C D E F G H
VDDA_CODEC VDDA_CODEC
1
<26,28,30,32,36,38,39,46,47,48> SLP_S3#
1
R329 +5VAMP
U18 R456
10K_0402_5% 1
C390 R341 IN 49.9K_0402_1% 1
1 5
2
10K_0402_5% MONO_IN OUT
1 2 1 2 1 2 2 2 3 1
2
C430 0.1U_0402_16V4Z + C548 C552 C551 EN + C309 C307
ADJ 4
1
D 0.1U_0402_16V4Z 150K_0402_1% 100P_0402_50V8J
2 2 GND
1
<30> PCM_SPK 2 R330 C377 22U_B_10V 1U_0603_10V4Z 2 22U_B_10V 0.1U_0402_16V4Z
G 2 1 1 MIC5205BM5_SOT23-5 C553 R457 2 2
1 2
1 Q35 S 0.01U_0402_16V7K R258 1
3
RHU002N06_SOT323 1 0_1206_5% 0.01U_0402_16V7K 143K_0402_1%
2
1
2
VDDA_CODEC
Place R258 between DGND & AGND & close to U14
1
R350
10K_0402_5%
C396 R359
2
1 2 1 2
1
D 0.1U_0402_16V4Z 150K_0402_1%
<26> SB_SPKR 2
G
Q37 S
3
RHU002N06_SOT323
0_1206_5%
2 2
+3VS
2 1 VDDA_CODEC
C409 0.1U_0402_16V4Z R1399
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS_CODEC 1 2
0_0805_5%
2 1 1 1 1 1 2 1 1 1
C427 0.1U_0402_16V4Z C395 C147 C417 C148 C402 C156 C175
C393
0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 2 2 1 2 2 2
25
38
2 1
9
C431 0.1U_0402_16V4Z U14
0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
AVDD1
AVDD2
DVDD1
DVDD2
GND GNDA 14 35 LINE_OUTL LINE_OUTL <32>
T16 PAD AUX_L LINE_OUT_L
15 36 LINE_OUTR LINE_OUTR <32>
T17 PAD AUX_R LINE_OUT_R
<32> INT_MIC INT_MIC C425 1 2 1U_0603_10V4Z 16 37 T14
MIC3 MONO_OUT PAD
C426 1 2 1U_0603_10V4Z 17 39 L_HP L_HP <32>
MIC4 HP_LOUT_L
<38> DLINE_IN_L R370 2 1 4.7K_0402_5% DLINE_IN_R_L C423 1 2 1U_0603_10V4Z DLINE_IN_RC_L 23 41 R_HP R_HP <32>
R375 4.7K_0402_5% LINE_IN_L HP_LOUT_R @ 10P_0402_25V8K
1 2 2 1 1 2
<38> DLINE_IN_R R369 2 1 4.7K_0402_5% DLINE_IN_R_R C422 1 2 1U_0603_10V4Z DLINE_IN_RC_R 24 R1038 @ 33_0402_5% C1064
R374 4.7K_0402_5% LINE_IN_R
1 2 BIT_CLK 6 AC97_BITCLK_CODEC <25>
18 CD_L
T18 PAD 8 AC97_SDIN0_CODEC 2 R373 1
SDATA_IN AC97_SDIN0 <25>
20 33_0402_5%
T19 PAD CD_R
3 3
19 CD_GND
T20 PAD 43 R168 1 2 @ 4.7K_0402_5%
GPIO_0 PORT_A_SNS <32>
<32> MIC1 MIC1 1 2 MIC1_C 21 44 R167 1 2 @ 4.7K_0402_5% PORT PLACE TO
C204 1U_0603_10V4Z MIC1 GPIO_1 R136 10K_0402_5%
GPIO_2 2 1 2
<32> MIC2 MIC2 1 2 MIC2_C 22 3 R32 1 2 @ 4.7K_0402_5% MONO_OUT X
MIC2 GPIO_3 PREP# <26,29,38>
C205 1U_0603_10V4Z
SENSE_A 13 PORT A HP OUT, DOCK HP LO
SENSE_B SENSEA
VDDA_CODEC 1 2 34 SENSEB
R231 2.2K_0402_1% PORT B M/B MIC
1 2
R169 @ 0_0402_5% 27 AUD_REF PORT C DOCK LI
VREF
<25> AC97_RST#_CODEC 11 RESET# 1 1
28 T21 C424 C416 PORT D M/B SPK
MIC_BIAS_B T13 PAD
<25> AC97_SYNC_CODEC 10 SYNC MIC_BIAS_C 29
30 T12 PAD 1U_0603_10V4Z 0.1U_0402_16V4Z PORT E X
MIC_BIAS_F T11 PAD 2 2
<25> AC97_SDOUT_CODEC 5 SDATA_OUT MIC_BIAS_D 32
VDDA_CODEC 12 MONO_IN PAD PORT F Internal MIC
PCBEEP
31 T6 PAD
N/C T7 PAD
N/C 33
<32,36> EAPD L53 1 2 47 40 T5 PAD
EAPD N/C
2
FBM-L10-160808-301-T_0603 45 T3 PAD
R969 NC T4 PAD
48 SPDIFO NC 46
2.67K_0402_1% T15 PAD
4 DVSS1 AVSS1 26
7 42
1
DVSS2 AVSS2
1 2 SENSE_A_A <32>
R970 39.2K_0402_1% AD1981HDJSTZ-REEL_LQFP48
VDDA_CODEC
SENSE_A 1 2 SENSE_A_B <32>
R972 20K_0402_1%
2
4 4
2
1 2 SENSE_A_C R974
R980 R973 10K_0402_1% @ 0_0402_5%
@ 0_0402_5% 2
1
Q97 D
1
SENSE_B @ 1U_0402_6.3V4Z G 1
2
1 S C978
Security Classification Compal Secret Data Compal Electronics, Inc.
3
2N7002_SOT23 R988
0.1U_0402_16V4Z 2005/05/26 2006/07/26 Title
2 Issued Date Deciphered Date
AC97 CODEC AD1981B
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
100K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 31 of 54
A B C D E F G H
A B C D E
0.1U_0402_16V4Z
10U_0805_10V4Z @ 0.1U_0402_16V4Z JP36
2 150U_D_6.3VM 2 2 2
2
100P_0402_50V8J
1U_0603_10V4Z INT_MIC_2 1
1
C441
1 C585 1
12
18
2 1
8
10 dB
C446
U39 1 2
Keep 10 mil width ACES_85205-0200
VDD
PVDD1
PVDD2
C503 R1410 @ 1200P_0402_50V7K 2
LINE_C_OUTR 1 LINE_C_R_OUTR C1044 2
<31> LINE_OUTR 1 2 2 5 INR BIAS 2 1 2 1U_0603_10V4Z
U27A
8
0.1U_0402_16V4Z 10K_0402_5% R1405 VDDA_CODEC
1 2 LINE_C_R_OUTR L57 TLV2462_SO8
12.1K_0402_1% 7.6 dB HLC0603CSCCR11JT_0603 3
P
C502 R1411 R_SPK+ R196 R193 C231 R388 + INT_MIC
OUTR+ 7 O 1
<31> LINE_OUTL 1 2 LINE_C_OUTL 1 2 LINE_C_R_OUTL 1 1 2INT_MIC_1 1 2 1 2INT_MIC_3
1 2 1 2 INT_MIC_4 2
INL -
G
9 R_SPK- 3K_0402_5% 1
0.1U_0402_16V4Z 10K_0402_5% OUTR- 3K_0402_5% 1 C226 0.22U_0603_10V7K C571 10K_0402_5%
4
10 dB R1406 1 2 LINE_C_R_OUTL INT_MIC <31>
R1407 12.1K_0402_1% 7.6 dB 68P_0402_50V8J
2
2 1 4 19 L_SPK+ 4.7U_0805_6.3V6K
0_0402_5% MUTE OUTL+ 2
17 L_SPK-
EAPD OUTL-
2 1
R1427 @ 0_0402_5%
3 C488
NC1
10 1 2
<26,28,30,31,36,38,39,46,47,48> SLP_S3# R430 1 2 10K_0402_5% 14 SHDN
NC2
NC3 13
16
C471
0.01U_0402_16V7K
AMP. FOR EXTERNAL MICROPHONE 100P_0402_50V8J
PGND1
PGND2
PGND3
PGND4
PGND5
NC4 R413
<37> MUTE_LED# 1 2
2 1 1 2
1
R1421 @ 0_0402_5% D
MAX9710ETP_QFN20 JJ_MIC_REF J_VDDA_CODEC 100K_0402_5%
<31,36> EAPD 2
6
11
15
20
21
Place close to JP15
G
Q28 S
3
100P_0402_50V8J
@ RHU002N06_SOT323
1
1
C249
2 2
<36> A_SD 2
G
Q32 S 2 U46A
3
RHU002N06_SOT323 MIC_REF
8
TLV2462_SO8
VDDA_CODEC VDDA_CODEC
3
P
+
1 C982 C276 L58 R211
O 1 J_MIC1
EXT_MICA 1 2 EXT_MICA_1 1 2 1 2 EXT_MICA_2 2 -
1
G
Place close to U14 audio CODEC R426 4.7U_0805_6.3V6K 0.22U_0603_10V7K
HLC0603CSCCR10JT_0603
1 10K_0402_5%
4
R978 2
VDDA_CODEC 47K_0402_5% 100_0402_5% C572
8
68P_0402_50V8J
2
1
1
J_VDDA_CODEC 2
5
P
R995 + C489
O 7
1
100K_0402_5% 2 6 1 2
- G
1
C490 R428 U27B
TLV2462_SO8 R427 100P_0402_50V8J
1 2
2
G MIC2 2 JJ_MIC_REF J_VDDA_CODEC 100K_0402_5%
<31> MIC2 3 3
S 4
3
1
VDDA_CODEC 5 2 1
<31> SENSE_A_A MIC_REF 5 2 J_MIC_REF
100P_0402_50V8J
MIC_SENSE 6 C492 R429 R1423 @ 0_0402_5%
6
1
D R_HP
<31> R_HP 7 7 1
1
VDDA_CODEC
C248
2 <31> L_HP L_HP 8 47K_0402_5%
Q49 G R423 8 4.7U_0805_10V4Z 1
9
2
RHU002N06_SOT323 DLINE_OUT_L 9
S 10
3
<38> DLINE_OUT_L 10
1
100K_0402_5% 2 U46B
<38> DLINE_OUT_R 11 11
R251 VDDA_CODEC 12
2
12
8
TLV2462_SO8
3 <38> DOCK_HPS# 100K_0402_5% ACES_87213-1200 3
5
P
+
1
G
C527 G 1 1 HLC0603CSCCR10JT_0603 1
S C536 100K_0402_5% C526 0.22U_0603_10V7K 1 10K_0402_5% C470
3
4
0.1U_0603_16V4Z
2 2.2U_0603_6.3V6K @ 1U_0603_10V6K C575 0.1U_0402_16V4Z
2 2 68P_0402_50V8J 2
RHU002N06_SOT323 2
VDDA_CODEC
R261 CHB1608B121_0603
JP24
2
J_R_HP 1 R_C_HP R_CR_HP 1 R_CRL_HP
+
2 1 2 2
C577 150U_D_6.3VM 16_0805_1% L52 5 8 R979
<31> SENSE_A_B
J_DLINE_OUT_R 7 47K_0402_5%
J_DLINE_OUT_L 4
1
D
1
R253 L51 3 Q50 2 MIC_SENSE
J_L_HP L_C_HP L_CR_HP 1 RHU002N06_SOT323
+
1 2 1 2 2 6 G 2
C581 150U_D_6.3VM 16_0805_1% CHB1608B121_0603 L_CRL_HP 2 S
3
1 C984
JP15
Place close to JP24 1
0.1U_0402_16V4Z
1 1 J_MIC_SENSE 5 8
1
+5VALW USB_VCCA
U57
1000P_0402_50V7K
150U_D_6.3VM
D D
0.1U_0402_16V4Z
3 6 1 USB20_N4 1 2USB20_N4_R 2 2 USB20_N5_R 1 2USB20_N5 USB20_N5 <26>
IN OUT <26> USB20_N4 USB20_P4 1 2 2
1 4 EN# OC# 5 1 1 <26> USB20_P4 2USB20_P4_R 3 3 3 3 USB20_P5_R 1 2USB20_P5 USB20_P5 <26>
C567
+
C515
C519
C550 0_0603_5% R605 4 4 0_0603_5% R607
4 4
5 GND GND 5
4.7U_0805_10V4Z G548A2P1U 6 6
2 2 2 2 GND GND
7 GND GND 7
8 GND GND 8
SUYIN_020173MR004S558ZL
SLP_S5 conn@
SUYIN_020173MR004S558ZL
1 2 +5VALW conn@
R163
10K_0402_5%
USB20_P5
USB20_N5
USB20_P4
2
USB20_N4
2
D51
PJDLC05_SOT23~D
D52
PJDLC05_SOT23~D
1
Right side USB CONNECTOR 0
1
+5VALW USB_VCCC
U65
1 8 W=40mils JP26
C GND OUT 0_0603_5% R617 C
2 IN OUT 7 1 1
1000P_0402_50V7K
150U_D_6.3VM
0.1U_0402_16V4Z
+
C517
USB20_P3
USB20_N3
2
D61
PJDLC05_SOT23~D
BT Connector
1
JP22
1 +3VAUX_BT
R562
2 USB20_P0_R USB20_P0
3 2 1 0_0402_5% USB20_P0 <26>
USB20_N0_R 2 1 0_0402_5% USB20_N0
B 4 USB20_N0 <26> B
R586
5 BT_LED <35>
R458 1 2 1K_0402_5%
6 R459 1 1K_0402_5% CH_DATA <30>
7 2 CH_CLK <30>
8
2
SMART Card connector +SC_PWR
ACES_87212-0800 D53
@ PACDN042_SOT23~D
1
JP3 1
1 11 SC_FCB C367
1 11 SC_FCB <30>
2 12 SC_CLK
2 12 SC_CLK <30>
3 13 SC_RST 0.1U_0402_16V4Z
3 13 SC_RST <30> 2 +3VALW +3VAUX_BT
4 4 14 14 +SC_PWR
5 15 SC_CD# SC_CD# <30> Q51 SI2301BDS_SOT23
5 15
6 6 16 16
D
7 7 17 17 3 1
8 8 18 18
9 19 SC_DATA SC_DATA <30>
9 19
1
SC_RFU
G
10 20 SC_RFU <30> 1 1 1 1
2
10 20 C306 R518 C546 C545 C549
ACES_85203-1002 4.7U_0805_10V4Z
1U_0603_10V4Z 100K_0402_5% 0.1U_0402_16V4Z
2 2 2 2
2
0.01U_0402_16V7K
C556
R454
<26> BT_OFF 1 2 1 2
47K_0402_5%
A A
0.1U_0402_16V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB & BT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 33 of 54
5 4 3 2 1
A B C D E
1 1
+3VS
RP3
DCD#1 1 8
RI#1 2 7
CTS#1 3 6
DSR#1 4 5
+5VS
4.7K_1206_8P4R_5%
2
IRRX 1 2
R76 D36
1K_0402_5%
CH751H-40_SC76
1
+5VS_PRN
RXD1 <38>
RP51
U8 R64 1K_0402_5% LPD3 1 8
<25,30,35,36> LPC_AD0 LPC_AD0 10 62 RXD1 1 2 LPD2 2 7
LPC_AD1 LAD0 RXD1 TXD1 LPD1
12 63 3 6
SERIAL I/F
<25,30,35,36> LPC_AD1 LAD1 TXD1 TXD1 <38>
<25,30,35,36> LPC_AD2 LPC_AD2 13 64 DSR#1 LPD0 4 5
LAD2 DSR1# DSR#1 <38>
<25,30,35,36> LPC_AD3 LPC_AD3 14 1 RTS#1
LAD3 RTS1# RTS#1 <38>
2 CTS#1 4.7K_1206_8P4R_5%
RP6 CTS1# CTS#1 <38>
<25,30,35,36> LPC_FRAME# LPC_FRAME# 15 3 DTR#1
LFRAME# DTR1# DTR#1 <38>
8 1 SIO_GPIO12 LPC_DRQ#0 16 4 RI#1 RP52
<25> LPC_DRQ#0 LDRQ# RI1# RI#1 <38>
LPC I/F
7 2 SIO_GPIO10 R108 1 2 0_0402_5% 5 DCD#1 LPD7 1 8
<26> NPCI_RST# DCD1# DCD#1 <38>
6 3 SIO_GPIO44 R109 1 2 @ 0_0402_5% SIO_RST# 17 LPD6 2 7
<25,30,35> PLT_RST_B# PCI_RESET#
5 4 SIO_GPIO43 +3VS R99 1 2 10K_0402_5% SIO_PD# 18 37 IRRX LPD5 3 6
LPCPD# IRRX2 IRRX <30>
FIR IRTX2 38 IRTXOUT <30>
LPD4 4 5
2 10K_1206_8P4R_5% PM_CLKRUN# 2
<26,30,35,36> PM_CLKRUN# 19 CLKRUN# IRMODE/IRRX3 39 IRMODE <30>
R120 CLK_PCI_SIO 20 4.7K_1206_8P4R_5%
<15> CLK_PCI_SIO PCI_CLK
1 2 SIO_IRQ SIRQ 21 41 LPTINIT#
R121 10K_0402_5% <26,30,35,36> SIRQ SIO_PME# SER_IRQ INIT# LPTSLCTIN# LPTINIT# <38> RP53
+3VS 1 2 6 IO_PME# SLCTIN# 42 LPTSLCTIN# <38>
1 2 SIO_DPIO45 R67 10K_0402_5% 44 LPD0 LPTACK# 1 8
PD0 LPD0 <38>
10K_0402_5% CLK_14M_SIO 9 46 LPD1 LPTBUSY 2 7
<15> CLK_14M_SIO CLK14 PD1 LPD1 <38>
CLOCK PD2 47 LPD2
LPD2 <38>
LPTPE 3 6
SIO_GPIO40 23 48 LPD3 LPTSLCT 4 5
GPIO40 PD3 LPD3 <38>
PARALLEL I/F
PID0 24 49 LPD4
+3VS GPIO41 PD4 LPD4 <38>
PID1 25 50 LPD5 4.7K_1206_8P4R_5%
GPIO42 PD5 LPD5 <38>
R119 SIO_GPIO43 27 51 LPD6
GPIO43 PD6 LPD6 <38>
CARD_ID# SIO_GPIO44 LPD7 RP54
GPIO
1 2 28 GPIO44 PD7 53 LPD7 <38>
SIO_DPIO45 29 55 LPTSLCT 1 8
GPIO45 SLCT LPTSLCT <38>
10K_0402_5% CARD_ID# 30 56 LPTPE LPTSTB# 2 7
GPIO46 PE LPTPE <38>
SER_SHD 31 57 LPTBUSY LPTAFD# 3 6
<38> SER_SHD GPIO47 BUSY LPTBUSY <38>
SIO_GPIO10 32 58 LPTACK# LPTERR# 4 5
GPIO10 ACK# LPTACK# <38>
SIO_GPIO11 33 59 LPTERR#
SIO_GPIO12 GPIO11/SYSOPT ERROR# LPTAFD# LPTERR# <38> 4.7K_1206_8P4R_5%
34 GPIO12/IO_SMI# ALF# 60 LPTAFD# <38>
SIO_IRQ 35 61 LPTSTB#
GPIO13/IRQIN1 STROBE# LPTSTB# <38>
R68 36 R480
EXPCRD_RST# EXPCRD_RST# GPIO14/IRQIN2 LPTSLCTIN#
1 2 40 GPIO23 1 2
<38> EXPCRD_RST#
10K_0402_5% 8 7 +3VS 4.7K_0402_5%
+3VS VSS VTR R481
22 VSS VCC 11
R77 43 VSS POWER VCC 26 LPTINIT# 1 2
1 2 PID0 52 45
VSS VCC 4.7K_0402_5%
VCC 54 1 1 1 1
10K_0402_5% C84 C88 C76 C57
LPC47N217_STQFP64
R80
1 2 SIO_GPIO11
10K_0402_5%
R100
1 2 SIO_GPIO40
1
R96 R81
@ 10_0402_5% @ 10_0402_5%
2
2
1 1
C94 C70
@18P_0402_50V8J @10P_0402_25V8K
2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SUPER I/O LPC47N217
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 34 of 54
A B C D E
5 4 3 2 1
BIOS ROM
+3VALW
+3VS
R1287 +3VALW
1 2 SPI_WP#
3.3K_0402_5%
D R1288 U66 D
1
1 2 SPI_HOLD# C989 8 VCC VSS 4 47K
Q75
3
3.3K_0402_5%
0.1U_0402_16V4Z SPI_WP# 3
DTA114YKA_SC59
Mini-PCIE Card LED
2 W
SPI_HOLD# 7 10K 2
HOLD WW_LED# <30>
SPI_CS# 1
<26> SPI_CS# S
SPI_CLK 6 +3VS
<26> SPI_CLK C R1291
1
SPI_SI 5 2 SPI_SO_L 1 2 SPI_SO SPI_SO <26>
<26> SPI_SI D Q 47K
3
47_0402_5%
SST25LF080A_SO8-200mil
R1291 place cloe to U66 10K 2 WL_LED# <30>
Q88
DTA114YKA_SC59 BLUE
+3VS
1
Q79 WL_BLUE_LED# <30,37>
RHU002N06_SOT323
47K
1
D
BT_LED 2
10K <33> BT_LED
2 G
WP_LED# <30>
S
3
2
R505
Q89 100K_0402_5%
DTA114YKA_SC59
1
C C
1
D Q78
WL_LED 2 RHU002N06_SOT323
G
S
3
2
R504
100K_0402_5%
1
TPM1.2
+3VS+3VALW
0.1U_0402_16V4Z
1 1 1 1
C1053 C1054 C1055 C1052
Base I/O Address
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0 = 02Eh +3VS
2 2 2 2 * 1 = 04Eh
0.1U_0402_16V4Z
24
19
10
U69
R1377
VSB
VDD
VDD
VDD
4.7K_0402_5%
LPC_AD0 26 28 LPC_PD#
<25,30,34,36> LPC_AD0 LPC_PD# <26,36>
2
LPC_AD3 17 R1378
B <25,30,34,36> LPC_AD3 LAD3 B
14 TPM_XTALO @ 4.7K_0402_5%
XTALO TPM_XTALI 1
XTALI 13 2 TPM_32K_CLK <36>
TPM R101 @ 0_0402_5%
CLK_PCI_TCG 21 SLB 9635 TT 1.1
<15> CLK_PCI_TCG
2
R1380 3 32.768KHZ_12.5P_Q13MC30610018
@ 4.7K_0402_5% NC R1381
12 1 NC 2
GND
GND
GND
GND
NC IN
1
R1409 4 3
SLB9635TT_TSSOP28 OUT NC
4
11
18
25
0_0402_5% Y8
TPM_XTALO C1056 1 2
2
10M_0402_5%
18P_0402_50V8J
1
C206
0.1U_0402_16V4Z
2
JP38
0_0402_5% 1
A R1334 USB20_N2_R 1 A
<26> USB20_N2 2 1 2 2
R1335 2 1 USB20_P2_R 3
<26> USB20_P2 3
0_0402_5% 4 4
3
ACES_85205-0400
conn@
D54
@ PACDN042_SOT23~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TCG/BIOS ROM/PS2/LED/SW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 35 of 54
5 4 3 2 1
5 4 3 2 1
+3VL +3VS
1 1 1 1 1 1 1 1 1
C37 C52 C51 C36 C34 C75 C79 C78 C81
11
67
81
94
30
38
47
2 7
3 6 KSI2 U47 +3VL
1
4 5 KSI1 KSO[0..13]
VCC1
VCC1
VCC1
VCC1
VCC2
VCC2
VCC2
<37> KSO[0..13]
R30 JP43
10K_1206_8P4R_5% KSO0 17 99 KBC_PWR_ON
KSO0 OUT0 KBC_PWR_ON <45> 1
KSO1 16 100 GREEN_BATLED# 10K_0402_5% VCC1_PWRGD
RP43 KSO2 KSO1 OUT1/IRQ8# GREEN_BATLED# <30> 2
15
2
KSI7 KSO3 KSO2 BATSELB_A# D7 EC_GPIO9 3
1 8 14 KSO3 OUT7/SMI# 98 BATSELB_A# <44> 4
2 7 KSI6 KSO4 13 97 KBRST# 1 2 EC_GPIO8
KSI5 KSO5 KSO4 OUT8/KBRST INV_PWM KB_RST# <25> 5
3 6 12 KSO5 OUT9/PWM2 96 INV_PWM <17> 6
4 5 KSI4 KSO6 10 95 FAN_PWM CH751H-40_SC76
KSO7 KSO6 OUT10/PWM0 CHGCTRL FAN_PWM <4> @ ACES_85201-0602
9 KSO7 OUT11/PWM1 93 CHGCTRL <43,44>
10K_1206_8P4R_5% KSO8 7
KSO9 KSO8 FWP# Pin82 250 -- nFWP
6 KSO9 GPIO01 82
Keyboard/Mouse Interface
KSO10 5 62 ON/OFFBTN_KBC# ON/OFFBTN_KBC# <37>
KSO10 GPIO02
SMSC_LPC47N250_TQFP-100P
GPIO07/PWM3 68 PM_RSMRST# <26>
R84 KSI0 25 69 EC_GPIO8 ADP_PS1 1 2
TP_CLK KSI1 KSI0 GPIO08/RXD EC_GPIO9 R538 @ 100K_0402_5%
1 2 24 KSI1 GPIO09/TXD 70
KSI2 23 D10 EC_GPIO13 1 R33 2
10K_0402_5% KSI3 KSI2 BATCON 100K_0402_5%
22 KSI3 GPIO11/AB2A_DATA 71 BATCON <44> 2 1 ADP_PRES <28,43,44,45,50>
R85 KSI4 21 72 ADP_PS1
KSI4 GPIO12/AB2A_CLK ADP_PS1 <50>
1 2 TP_DATA KSI5 20 KSI5 GPIO13/AB2B_DATA 73 EC_GPIO13 CH751H-40_SC76
KSI6 19 74 THM_MBAY# 2 R31 1 +3VL
KSI6 GPIO14/AB2B_CLK THM_MBAY# <42>
10K_0402_5% KSI7 18 75 PCI_SERR# 10K_0402_5%
KSI7 GPIO15/FAN_TACH1 PCI_SERR# <24,30>
76 THM_MAIN# D6
C RP5 GPIO16/FAN_TACH2 THM_MAIN# <42> C
77 A20M 1 2
KBD_CLK TP_CLK GPIO17/A20M CH751H-40_SC76 GATEA20 <25> +3VL
1 8 <37> TP_CLK 26 IMCLK
2 7 KBD_DATA TP_DATA 27 78 NUM_LED#
<37> TP_DATA IMDAT GPIO20/PS2CLK NUM_LED# <30,37>
3 6 PS2_CLK KBD_CLK 29 80 SLP_S3# RP1
<38> KBD_CLK KCLK GPIO21/PS2DAT SLP_S3# <26,28,30,31,32,38,39,46,47,48>
4 5 PS2_DATA KBD_DATA 31 1 AB1A_CLK 1 8
<38> KBD_DATA KDAT GPIO24/KSO16
PS2_CLK 32 57 MODE 1 2 0_0402_5% Pin1 250 -- TEST Pin ( NC !! ) AB1A_DATA 2 7
<38> PS2_CLK EMCLK GPIO27 EAPD <31,32> Pin57 250 -- MODE
10K_1206_8P4R_5% PS2_DATA 33 R140 AB1B_CLK 3 6
<38> PS2_DATA EMDAT AB1B_DATA 4 5
Bus
LPC
10K_0402_5% LPC_AD0 35 61 PWR_GD
<25,30,34,35> LPC_AD0 LAD[0] PWRGD PWR_GD <21,39,40,49,50> @ @
60 VCC1_PWRGD
VCC1_PWRGD VCC1_PWRGD <40>
LPC_FRAME# 41 50
<25,30,34,35> LPC_FRAME# LFRAME# 24MHZ_OUT/GPIO19/WINDMON Pin50 250 -- 24MHz_Out ADP_ID <50>
PLT_RST# 42
Pin34 250 -- LPCPD# <7,24,25,26,28,30> PLT_RST# LRESET#
34 52 TEST 1 2
Miscellaneous
R87 1 LPCPD#/GPIO23 TEST PIN Pin52 250 -- XOSEL
<26,35> LPC_PD# 2 @ 0_0402_5% LPCPD# R977 300_0402_5% R25
R1354 1 2 @ 0_0402_5% Pin91 250 -- nDMS_LED FWP# 1 2 PM_POK
<50> ADP_EN
CRY1 53 91
XTAL1 DMS_LED#/GPIO10 ADP_PS0 <50>
1 2 CRY2 54 88 AMBER_BATLED# 10K_0402_5%
XTAL2 BAT_LED# AMBER_BATLED# <30>
CLK_PCI_EC 90 STB_LED#
PWR_LED#/8051TX STB_LED# <30,37,38>
R74 51 89 CAPS_LED#
VCC0 FDD_LED#/8051RX CAPS_LED# <30,37>
1
B @ 2M_0402_5% R75 B
AGND
R86 2 1
GND
GND
GND
GND
GND
GND
GND
@ 10_0402_5% 120K_0402_5% +RTCVCC R62 R62 250@ +3VL
KBC1021_TQFP100 MODE 1 2 JP31
2
55
92
79
65
45
36
28
8
1
2 1
C80 Y2 @ 10K_0402_5% VCC1_PWRGD
IN
OUT
R58 2
18P_0402_50V8J 1 1 18P_0402_50V8J +3VL 1 2 100K_0402_5% NUM_LED# 3
R52
@ 10P_0402_50V8J R59 1 2 100K_0402_5% STB_LED# 4
1 C350 C349 PGM R60 100K_0402_5% CAPS_LED#
2 1 1 2 1 2 5
C69 C67
NC
NC
2 2 @ 1K_0402_5% 6
1U_0603_10V4Z 0.1U_0402_16V4Z
2
0.1U_0402_16V4Z R78
TEST 2 1
A @ 1K_0402_5% A
R27
EA# 2 1
250@ 1021@ 1K_0402_5%
R127 R129
R128 R131
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
R977 R78 LPC47N1021
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R62 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document Number
LA-2951
Rev
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 36 of 54
5 4 3 2 1
+3VS +5VS
INT_KBD CONN.
220P_0402_50V4Z C749
SWITCH
2 1 STB_LED#
220P_0402_50V4Z C750
2 1 ON/OFF#
JP18 220P_0402_50V4Z C751
BOARD.
14 28 2 1 KSI1 KSO[0..15]
14 28 <36> KSO[0..15]
13 13 27 27
12 26 KSI[0..7]
12 26 <36> KSI[0..7]
11 25 NUM_LED#
11 25 NUM_LED# <30,36>
10 24 CAPS_LED#
10 24 CAPS_LED# <30,36>
9 23 MUTE_LED#
9 23 MUTE_LED# <32>
8 22 WL_BLUE_LED#
8 22 WL_BLUE_LED# <30,35>
7 21 KSO12 +3VALW
7 21 KSI0 JP20 JP6
6 6 20 20
5 19 KSI4 1 KSO15 48 24
5 19 1 LID_SW# <17,26> 48 24
4 18 KSI5 2 KSO10 47 23
4 18 KSI6 2 STB_LED# KSO11 47 23
3 3 17 17 3 3 STB_LED# <30,36,38> 46 46 22 22
2 16 KSI7 8 4 ON/OFF# KSO14 45 21
2 16 GND 4 KSO12 KSO13 45 21
1 1 15 15 9 GND 5 5 44 44 20 20
6 KSI1 KSO12 43 19
ACES_85203-1402 6 KSO3 43 19
7 7 42 42 18 18
KSO6 41 17
ACES_85205-07001 KSO8 41 17
40 40 16 16
KSO7 39 15
39 15
WL,Vol up,Vol down,Mute,Present button KSO4
KSO2
38
37
38
37
14
13
14
13
KSI0 36 12
36 12
On/off ,information button KSO1
KSO5
35
34
35
34
11
10
11
10
KSI3 33 9
KSI2 33 9
32 32 8 8
KSO0 31 7
KSI5 31 7
30 30 6 6
1
C5
100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
TYCO_1-179396-2~D
13
14
15
16
17
18
19
20
CP7 CP2
KSI3 4 5 KSO14 4 5
Connector for MDC Rev1.5 KSO5 3 6 KSO11 3 6
KSO1 2 7 KSO10 2 7
KSI0 1 8 KSO15 1 8
100P_1206_8P4C_50V8 100P_1206_8P4C_50V8
+3VL +3VL
1
R536
1
ON/OFFBTN_KBC# <36>
SN74LVC14APWLE_TSSOP14
2
R26 D
P
100K_0402_5% S 1 2 +5VS
1 1
3
SP_DATA 3 4 TP_CLK 2
5 6 1 <36> TP_CLK 3 1
2
1U_0603_10V4Z 1U_0603_10V4Z 1 2 ON/OFFBTN# ON/OFFBTN# <26> +5VS C321 C319
2 2 Q70 7 8 4
RHU002N06_SOT323 D42 ACES_87153-0801L D67 0.1U_0402_16V4Z SP_DATA 5 0.1U_0402_16V4Z
CH751H-40_SOD323 2 6 2
SP_CLK 7
8
1
@ PACDN042_SOT23~D ACES_87212-0800
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MDC/KBD/ON_OFF/LID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 37 of 54
A B C D E
+5VALW
1
DOCK CONN. 184PIN R529
100K_0402_5%
JP29
2
C746 @ 1000P_0402_50V4Z
M_RED 1 2 L10 SLP_S5#_5R DOCK_MOD_RING
C747 @ 1000P_0402_50V4Z KC FBM-L18-453215-900LMA90T_1812 DOCK_MOD_TIP 2
1
1
M_GRN D
1 2 VIN 2 1 DOCKVIN
C748 @ 1000P_0402_50V4Z 1 2 Q65
1 1 <33,39> SLP_S5 1
M_BLU 1 2 C72 C73 G ACES_85205-0200
S RHU002N06_SOT323
3
1000P_0402_50V7K 1000P_0402_50V7K
2 2 SWAP
JP30B
JP30A
<34> LPTACK# LPTACK# 46 128
LPTBUSY 46 128
172 G1 P1 173 DOCKVIN <34> LPTBUSY 47 47 129 129
<34> LPTPE LPTPE 48 130
LPTSLCT 48 130
<34> LPTSLCT 49 49 131 131
<34> LPD7 LPD7 50 132
ON/OFF# DETECT LPD6 50 132
<37> ON/OFF# 1 1 83 83 <34> LPD6 51 51 133 133
2 84 <34> LPD5 LPD5 52 134 KBD_DATA
2 84 52 134 KBD_DATA <36>
MDO2+ 3 85 MDO3+ MDO3+ <29> <34> LPD4 LPD4 53 135 KBD_CLK
<29> MDO2+ 3 85 53 135 KBD_CLK <36>
MDO2- 4 86 MDO3- MDO3- <29> <34> LPD3 LPD3 54 136 CPPE#
<29> MDO2- 4 86 54 136 CPPE# <15,24>
5 87 <34> LPD2 LPD2 55 137 PS2_DATA
5 87 55 137 PS2_DATA <36>
MDO0+ 6 88 MDO1+ MDO1+ <29> <34> LPD1 LPD1 56 138 PS2_CLK
<29> MDO0+ 6 88 56 138 PS2_CLK <36>
MDO0- 7 89 MDO1- MDO1- <29> <34> LPD0 LPD0 57 139 DOCK_HPS#
<29> MDO0- 7 89 57 139 DOCK_HPS# <32>
8 90 <34> LPTSLCTIN# LPTSLCTIN# 58 140
LAN_ACT#_DOCK 8 90 PWR_LED LPTINIT# 58 140 DLINE_IN_L
9 9 91 91 <34> LPTINIT# 59 59 141 141 DLINE_IN_L <31>
LANLINK_STATUS#_DOCK 10 92 1 2 SLP_S5#_5R 60 142 DLINE_IN_R
10 92 60 142 DLINE_IN_R <31>
11 93 R515 1K_0402_5% 61 143
11 93 DVI_CLK 61 143 DLINE_OUT_L
<16> D_VSYNC 12 12 94 94 DVI_CLK <19> 62 62 144 144 DLINE_OUT_L <32>
<16> D_HSYNC 13 95 DVI_DAT DVI_DAT <19> 63 145 DLINE_OUT_R
13 95 63 145 DLINE_OUT_R <32>
<16> D_DDCDATA D_DDCDATA 14 96 64 146
D_DDCCLK 14 96 64 146
<16> D_DDCCLK 15 15 97 97 65 65 147 147
<19> DVI_DETECT DVI_DETECT 16 98 DVI_TX2- 66 148
16 98 DVI_TX2- <19> 66 148
17 99 67 149 PCIE_TXP4 PCIE_TXP4 <26>
M_RED R1404 DOCK_RED 17 99 DVI_TX2+ 67 149
1 2 0_0402_5% 18 18 100 100 DVI_TX2+ <19> 68 68 150 150
M_GRN R1428 1 2 0_0402_5% DOCK_GRN 19 101 69 151 PCIE_TXN4 PCIE_TXN4 <26>
2 M_BLU R1429 DOCK_BLU 19 101 69 151 2
1 2 0_0402_5% 20 20 102 102 70 70 152 152
21 103 DVI_TX1- 71 153
21 103 DVI_TX1- <19> 71 153
<16,19> COMP 22 104 <26> USB20_N6 72 154 PCIE_C_RXP4 1 R1346 2PCIE_RXP4
22 104 72 154 PCIE_RXP4 <26>
<16,19> CRMA 23 105 DVI_TX1+ 73 155 0_0402_5%
23 105 DVI_TX1+ <19> 73 155
<16,19> LUMA 24 106 <26> USB20_P6 74 156 PCIE_C_RXN4 1 R1347 2PCIE_RXN4
24 106 74 156 PCIE_RXN4 <26>
25 107 75 157 0_0402_5%
25 107 DVI_CLK- 75 157
26 26 108 108 DVI_CLK- <19> <26> USB20_N7 76 76 158 158
27 109 77 159 CLK_PCIE_DOCK
<31> LINE_IN_SENSE 27 109 77 159 CLK_PCIE_DOCK <15>
28 110 DVI_CLK+ <26> USB20_P7 78 160
28 110 DVI_CLK+ <19> 78 160
29 111 79 161 CLK_PCIE_DOCK#
<50> ACOCP_EN# 29 111 79 161 CLK_PCIE_DOCK# <15>
30 112 <34> SER_SHD SER_SHD 80 162
30 112 DVI_TX0- EXPCRD_RST# 80 162 PREP#
31 31 113 113 DVI_TX0- <19> <34> EXPCRD_RST# 81 81 163 163 PREP# <26,29,31>
32 114 DETECT 82 164 VA_ON#
32 114 DVI_TX0+ 82 164
33 33 115 115 DVI_TX0+ <19>
1
DCD#1 34 116 176 178 1
<34> DCD#1 34 116 GND GND
RI#1 35 117 DOCK_ADP_SIGNAL 169 180 R66 C59
<34> RI#1 35 117 GND GND
DTR#1 36 118 DOCK_ID 175 182
<34> DTR#1 36 118 DOCK_ID <26> GND GND
CTS#1 37 119 179 174 1K_0402_5% 0.1U_0402_16V4Z
<34> CTS#1 37 119 +3VS GND GND 2
RTS#1 38 120 181 171
<34> RTS#1
2
DSR#1 38 120 GND GND
<34> DSR#1 39 39 121 121 R1387 177 GND GND 170
TXD1 40 122 +5VS
<34> TXD1 40 122 C555
RXD1 41 123 DOCK_ID 1 2
<34> RXD1 41 123
+
42 42 124 124 165 G2 P2 167 1 2
LPTSTB# 43 125 @ 10K_0402_5%
<34> LPTSTB# 43 125 ADP_SIGNAL
LPTAFD# 44 126 @ 22U_1206_10V4Z
<34> LPTAFD# 44 126
LPTERR# 45 127 DOCK_MOD_RING 166 168 DOCK_MOD_TIP
<34> LPTERR# 45 127 R1401 RING TIP
2
DOCK_ADP_SIGNAL 1 2
JAE_SP03-14588-PCL03 JAE_SP03-14588-PCL03
1K_0402_1% D59
@ PACDN042_SOT23~D
3 3
1
V_3P3_LAN LAN_ACT#_DOCK
1
R527 D
2 1 2 Q62
10K_0402_5% G RHU002N06_SOT323
S
3
+3VS +3VS LAN_ACT#
+3VS LAN_ACT# <28,29>
C360 +3VALW
C366 C365
2 1 LANLINK_STATUS#_DOCK
1 2 2 1
1
0.1U_0402_16V4Z 0.1U_0402_16V4Z D
U52 0.1U_0402_16V4Z 2 Q63 R526
U51 U50 G RHU002N06_SOT323
5 VCC
5 VCC 5 S 10K_0402_5%
3
M_BLU VCC LANLINK_STATUS#
<19> M_BLU 1 LANLINK_STATUS# <26,28,29>
2
BLUE A M_GRN M_RED
<16> BLUE 2 B <19> M_GRN 1 A <19> M_RED 1 A
<16> GREEN GREEN 2 <16> RED RED 2 PWR_LED
ISO_PREP# B B
<26> ISO_PREP# 4 OE
1
ISO_PREP# ISO_PREP# D
4 OE 4 OE
3 GND <30,36,37> STB_LED# 2
3 3 G
4 FSA66P5X_SC70-5 GND GND Q59 4
S
3
FSA66P5X_SC70-5 FSA66P5X_SC70-5 RHU002N06_SOT323
<26,28,30,31,32,36,39,46,47,48> SLP_S3#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Docking CONN.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 38 of 54
A B C D E
A B C D E
U10
8 D S 1
1 1
7 D S 2
1 6 3 +5VALW
C171 D S
5 D G 4 1 1
C160 C170
1
SI4800DY_SO8
2 10U_0805_10V4Z C91
10U_0805_10V4Z R135
2 2
+VCC_CORE 1 2 +VCCP
RUNON 100K_0402_5%
2
0.1U_0402_16V4Z 0.1U_0402_16V4Z
+VCCP 1 2 +1.5VS
1
D
SLP_S5# 2
0.1U_0402_16V4Z <26,47> SLP_S5#
G
Q22 S
C93
3
RHU002N06_SOT323
+1.5VS 1 2 +1.8V
0.1U_0402_16V4Z
1
8 1 7 2 +3VL
D S R139 D S
7 D S 2 1 6 D S 3
1 6 3 C127 5 4 1 1
D S D G
1
C86 5 4 1 1 330K_0402_5% C132 C128
D G C71 C77 SI4800DY_SO8 R125
2
SI4800DY_SO8 2 10U_0805_10V4Z
2 10U_0805_10V4Z 10U_0805_10V4Z 2 2 100K_0402_5%
2 2 RUNON
2
RUNON
1
J34 0.1U_0402_16V4Z
0.1U_0402_16V4Z R469 SLP_S3
SHORT PADS
1 2
470_0402_5%
1
D D
2
SLP_S3 2 1 SLP_S3# 2
<26,28,30,31,32,36,38,46,47,48> SLP_S3#
G C120 G
Q18 S Q19 S
3
3
RHU002N06_SOT323 0.01U_0402_25V7Z RHU002N06_SOT323
2
3 3
+3VS
+0.9V +1.8V VDD_MEM18 +2.5VS +5VS +1.5VS
1
1
1
R134
R188 R1310 R95 R130 R116 R151
470_0402_5%
470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%
2
1 2
1 2
1 2
1 2
1 2
1 2
1
D D D D D D D
SLP_S5 1 2 2 SLP_S5 2 SLP_S3 2 SLP_S3 2 SLP_S3 2 SLP_S3 2 SLP_S3 2
R1311 @ 0_0402_5% G G G G G G G
S Q90 S Q14 S Q21 S Q17 S Q16 S Q47 S
3
3
SLP_S3 1 2 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323 RHU002N06_SOT323
0_0402_5%
R1312 Q27
RHU002N06_SOT323
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Circuits
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 39 of 54
A B C D E
VDD_MEM18 +3VS +3VS +3VL +3VL
+3VL
1
+3VL
R89 R82 R281 R7
14
14
1K_0402_5% 330_0402_5% 330_0402_5% U5A U5B D8 +3VL 10K_0402_5%
1
R38 CH751H-40_SOD323
P
1
2
1 2 1 2 3 4 1 2 R24
I O 47K_0402_5% I O
VCC1_PWRGD <36>
G
C 100K_0402_5%
14
2 Q10 SN74LVC14APWLE_TSSOP14 1 SN74LVC14APWLE_TSSOP14 U5D
1
B PMST3904_SOT323 C48 D
P
1
C E +3VS 9 8 2
3
Q11 0.1U_0402_16V4Z I O G Q3
2
G
B PMST3904_SOT323 2 S RHU002N06_SOT323
1
3
E C26 SN74LVC14APWLE_TSSOP14
3
7
1
0.1U_0402_16V4Z
+5VS +3VL R47 2
10K_0402_5%
1
2
C25
1
J32
R43 0.1U_0402_16V4Z 1 2 PWR_GD
2 PWR_GD <21,36,39,49,50>
180K_0402_5% SHORT PADS
14
2 U5C
1
D
P
5 I O 6 2
G Q9
G
S RHU002N06_SOT323
3
1
1 SN74LVC14APWLE_TSSOP14
7
R37 C47
560K_0402_5% 0.1U_0402_16V4Z
2
2
1
D
P
1
11 I O 10 2
G Q2
1
2 Q26 SN74LVC14APWLE_TSSOP14 1 1 1 1 1 1 1 1
7
B
1
C E PMST3904_SOT323
3
1
+3VS +3VS
Need be tune to H10 H11 H12 H13 H14
HOLEB HOLEB HOLEB HOLEB HOLEB
1 3msec time delay 1
C991 C992
D60
1
0.1U_0402_16V4Z CH751H-40_SOD323 0.1U_0402_16V4Z
2 2
1 2
5
G
0.47U_0603_10V7K
1
R1402 SN74LVC1G17DBVR_SOT23-5 SN74LVC1G17DBVR_SOT23-5
3
1 2 PGD_IN
1
C990
@ 0_0402_5%
2
1
H27 H28 H32 H33 H34 H35 H36 H37
HOLED HOLED HOLED HOLED HOLED HOLED HOLED HOLED
1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
POK CKT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 40 of 54
5 4 3 2 1
D D
G965
AC VIN +3VS LDO
Adapter LM358 (2.5V)
VS Thermal
in
Protector
+5VALWP
ACOK SWITCH
MAINPWON VL
+2.5VS 1A
+3VALWP 4A
ENBL2 ENBL1
+5VS
B+ B+ PWR_GD
C MAX8734A C
DC/DC
(3V/5V) VCC SHDN#
+5VALWP 4A
VMB VIN
ISL6260 &ISL6208
VS DC/DC
(CPU_CORE)
+3VLP 0.1A
BQ24703 MAX8743
Charger DC/DC +1.5VSP 4.2A
B+ (1.05V/1.5V) CPU_CORE
B
( 44A) B
SLP_S3#
+1.05V_VCCP 6.4A +5VALWP
ENBL1/ENBL2
BATSELB_A
Battery
Selector
Circuit BATSELB_A# VCC
Battery A Battery B
6 Cell 8 Cell TPS51116
B+ DC/DC +1.8VP 7A
VMB (+1.8VP/+0.9VSP)
BATT
BATT_A Title
POWER BLOCK DIAGRAM
BATT_B
Size Document Number Rev
PCN1 ADP_SIGNAL
9 GND6 SINGAL 5 VIN
8 GND5
1 PL1 1
7 1 FBM-L18-453215-900LMA90T_1812
GND4 PWR1
6 ADPIN 1 2
GND3
100P_0402_50V8J
4 GND2 PWR2 2
1000P_0402_50V7K
3 GND1
1
PC1
100P_0402_50V8J
1
1
PC4
FOX_JPD113E-LB103-7F PC2 PR1
1000P_0402_50V7K
PC3
15K_0402_5%
2
AB/I_A <44>
VMB_A PL2 BATT_A
PCN2
FBM-L18-453215-900LMA90T_1812
BATT+ 1 1 2
2 EC_SMD_A
SMD EC_SMC_A PR2
SMC 3
2
RES 4 2 1 2
1
5 1M_0402_1%
TS PC5 PC6
6 1000P_0402_50V7K 0.01U_0402_50V4Z
2
GND
1 2 +3VL
TYCO_C-1746706_6P PR10
210K_0402_1%
1
PR3
1K_0402_5%
1
PR4 PR5
100_0402_5% 100_0402_5%
THM_MAIN# <36>
2
1
220P_0402_25V8K
PC144
PC143 PC145
220P_0402_25V8K 220P_0402_25V8K
2
3 3
VMB_B
2 EC_SMD_B
SMD EC_SMC_B
SMC 3
1
4 AB/I_B 2 PR7 1
B/I TS_B 1K_0402_5% PC8 PC9
TS 5
1 2 1000P_0402_50V7K 0.01U_0402_50V4Z
+3VL
2
2
2
6 PR9
GND PR11 210K_0402_1%
SUYIN_20163S-06G1-K 1K_0402_5%
1
1
PR14 PR15
THM_MBAY# <36>
100_0402_5%
100_0402_5%
2
EC_SMD_B1
AB1B_DATA <36>
4 4
EC_SMC_B1
AB1B_CLK <36>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 42 of 54
A B C D
A B C D
1 1
VIN P2
BATT
P4 PQ2
PQ3 PQ4 AO4407_SO8
AO4407_SO8 AO4407_SO8 1 8
1 8 8 1 2 7
2 7 7 2 3 6
3 6 6 3 5
0.1U_0603_16V7K
PQ5 5 5
B+ P2
47K_0402_5%
DTA144EUA_SC70 PR17
4
1
3 1 0_0402_5%
4
4
1
PC12
PR16 1 2
2
47K
200K_0402_5%
2
0_0402_5%
PR20 PL4
47K
PR19
0.015_2512_1% FBM-L11-322513-151LMAT_1210
2
1 2 1 2
2
PR18
1
47P_0402_50V8J
1
2
ACDRV# CHG_B+
ACN <50>
2
PC13
10U_1206_25V6M
4.7U_1206_25V6K
PR21
1
1
100_0402_1% 0_0402_5%
PC14
PC15
ADP_PRES 2 1
1
1
2
1U_0805_25V4Z
1
1 2
PC17
PD7
2
ADP_EN# <50> PC16 PD5 2
2
2 1 1U_0603_6.3V6M RLZ16B_LL34
2
1 2
3
2
1
PR24 PU2
1SS355_SOD323 1K_0402_1% ACDRV#
SRSET <50> 8 ACN ACDRV# 25
9 ACP VCC 22
26 21 DH_CHG 4 PQ7
ACDET PWM# SI4835BDY_SO8
SRP 16
AC_CHG 2 PR25 1 5 15
1K_0402_1% ENABLE SRN
28 ACSEL BATP 12
PR26 ALARM 19 ALARM BATDRV# 24 BATT
1 2 2 SRSET
191K_0402_1% 3 18 PR28
PL5
5
6
7
8
<36,44> CHGCTRL ACSET VS
+3VL 2 PR27 1 27 ACPRES VHSP 20 0.015_2512_1%
100K_0402_5% 13 LX_CHG 1 2 1 2
BQ24703VREF IBAT
10U_1206_25V6M
133K_0402_1%
1U_0603_6.3V6M
4 VREF BATSET 6
2
100K_0402_1%
4.7U_1206_25V6K
1 8.2UH_MPL73-8R2_4A_20% 1
BATDEP
1
1
PC18
PR29
7 COMP GND 17
1
PGND
3K_0402_1%
3K_0402_1%
PR30
PC19
PC20
10 NC1 NC4 23
1
11 14
2
2
NC2 NC3 2
PR31
PR32
1
4.7U_0805_6.3V6K
PD8
2
29
BQ24703_QFN28 SKS30-04AT_TSMA
2
1
PC22
2
80.6K_0402_1%
PC21
1
1 2
2
1
1U_0603_6.3V6M
PC23
PR33
SE_CHG+
ACDET 0.1U_0402_16V7K
SE_CHG- CV=12.6V(6 CELLS LI-ION)
2
P2
PR34 16.8V(8 CELL LI-ION)
2
+3VL +3VL
150P_0402_50V8J
1 2 PR35
3 150_0402_1%
CC=3A for 2.4AHr 3
1
100K_0603_1%
PC24
330K_0402_5%
BATT CC=3.57A for 2.55AHr
4.7U_0805_10V6K
1 2
1
1
10K_0402_1%
VL
PR36
PR37
PC25
0.1U_0402_10V6K
PC26
2
1
2
2
8
+ BATT
Low 9.879V 1 2 O 4 ADP_PRES <28,36,44,45,50>
12
O I
1
12.4K_0603_1%
G
PR40
PR41
1
LM393M_SO8 100K_0603_0.1%
4
+3VL PR42
174K_0603_1%
2
2
1
PR43
2
1
+3VL
4.7K_0402_5%
1
PR46 PR44
1
1 2
@0.1U_0402_16V7K
2
2
8
100P_0402_50V8J
PU3B PQ9
2
1
BQ24703VREF PR53 D PQ8
5
P
+
1
D RHU002N06_SOT323
7 AC_CHG <44> 2.8K_0603_0.5% 2 RHU002N06_SOT323
2
O
1
10K_0603_1%
6 2 G
-
1
1
@47K_0402_1%
0.022U_0402_16V7K
PR49 G S
1 2
3
PR51
PC28
LM393M_SO8 100_0402_5% S
4
3
1
PR50
PC29
PR52
VL 10K_0402_1%
2
PR54 PR266
2
4 4
1 2 39.2_0402_1%
1
PQ10 D PQ11 D
2
33K_0402_1% AC_CHG 2 2
G G RHU002N06_SOT323 CELLSEL# <44>
PU5 S S
3
1.24VREF RHU002N06_SOT323
4 REF CATHODE 3
Airline detector NC 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2005/03/10 2006/03/10 Title
High 17.521V 5 1
Issued Date Deciphered Date
Low 16.871V ANODE NC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
LMV431ACM5X_SOT23-5 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 43 of 54
A B C D
A B C D
+3VL
@0.1U_0402_10V6K
1
PC30
1 1
BATT_A
2
5
PU6 PD9
BATT_B PQ12
5
+3VL PU7 1 2
P
INB RHU002N06_SOT323
1 4 1
P
<43> ALARM INB O PR55 PR56
O 4 2 INA 3
G
47K_0402_5%
BATT_IN
S
2 INA 1 2 1 3 1 2
2
PR57
74LVC1G02_04_SOT353 RB715F_SOT323 100_0402_5% 0_0402_5%
0.1U_0603_50V4Z
74LVC1G02_04_SOT353 PD10
3
PQ13
1SS355_SOD323
G
2
RHU002N06_SOT323 PR58
PC31
1
PC32
1.5M_0402_5%
1
S
D
BATSELB_A 1 2 3 1
1
2
1000P_0402_50V7K PQ14 PD11
2
D RHU002N06_SOT323 +3VL
22K_0402_5%
G
2
PR59
2 RLZ6.2C_LL34
G +3VL
2
S
3
1
1
PU8
NC
2 A Y 4
PQ15
G
PC33
1
3
BATSELB_A# 1 2 2 1
G D
2
22K_0402_5%
RHU002N06_SOT323 G
PR60
2
S 2
3
1
1
PMBT2222_SOT23
PR61
PQ17
470K_0402_5%
1
RHU002N06_SOT323 D
+3VL +3VL BATT_IN 2
1
C G
2
PQ18
2 S
3
B PR62
10K_0402_5%
E 470K_0402_5%
3
1
PQ19
PR63
PD12
1
RHU002N06_SOT323 D
1
CFET_A 1 2 2
G PR64
2
5
3
1SS355_SOD323
5
P
NC
PR65
1
BATSELB_A# BATSELB_A PQ20 D
2 4 1 1 2
P
<36> BATSELB_A#
2
A Y IN1
O 4 1 2 2
G
2 G RHU002N06_SOT323
IN2 SKS30-04AT_TSMA
G
SN74LVC1G14DCKR_SC70-5 S
3
3
10K_0402_5%
4
3
1
D
220P_0402_50V7K
SN74AHC1G08DCKR_SC70 PQ23 5 5
BATT_IN 2 3 6 6 3 PR66 BATT_A
1
PC34
G 2 7 7 2 470K_0402_5%
S 1 8 8 1
3
RHU002N06_SOT323 BATT
2
2
PQ21 PQ22
AO4407_SO8 AO4407_SO8
+3VL PQ24 PQ25
3
+3VL AO4407_SO8 AO4407_SO8 3
1
1 8 8 1
5
1
PU11 3 6 6 3 470K_0402_5%
P
PMBT2222_SOT23
0.22U_0402_10V4Z
2 1 2 PR68
I O 4 5 5
2
220K_0402_5%
470K_0402_5%
NC 1
2
2
2
470K_0402_5%
BATT_B
4
1SS355_SOD323
1
470K_0402_5%
PC35
PR70
PR69
3
PR72
PR71 PU12 C
PD15
5
PQ26
10K_0402_1% 2
2
PQ27
1
10K_0402_5%
1 B 1 2
P
1
1
O
1
PR74
BATSELB_A# 2 4.7K_0402_5%
IN2 PD16 SKS30-04AT_TSMA
G
S
3 1
1 2
3
2
+3VL SN74AHC1G08DCKR_SC70
G
2
1 2
ADP_PRES 1SS355_SOD323 PQ29
PR75
1
PQ28 D RHU002N06_SOT323 D
1
1 2 2 2
PR76 G RHU002N06_SOT323 G
+3VL 10K_0402_5% S S
100K_0402_5% 3
3
<50> CFET_B
2
PQ30
+3VL +3VL
PQ31
1
1
PQ32 D RHU002N06_SOT323 D
1
I_A# D BATT_IN 2
2
5
PD17 G BATT_IN 2 G
1
3
1
1 2 4 PR264 S
3
4 4
330K_0402_5%
1
100K_0402_5%
RB715F_SOT323 SN74LVC1G17DBVR_SOT23-5
3
2
PR77
CFET_B
2
I_A <50>
<42> AB/I_A PR262
2
PQ75 D PQ76 D
1 2 2 2
G G Security Classification Compal Secret Data Compal Electronics, Inc.
S S Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
3
+3.3V/+5V
B+
1 1
2
PL6
FBM-L18-453215-900LMA90T_1812 PC36 PC37
0.1U_0603_50V4Z 0.1U_0603_50V4Z
2
1 2 BST5B BST3B 1 2
B++
1
PD18
CHP202U_SC70
2200P_0402_50V7K
10U_1206_25V6M VL
1
1 PR78
1
2
PQ34 0_0402_5%
B++
PC38
PC39
47_0402_5%
2 7 0_0402_5% PQ35
2
D2 D1/S2/K
1
2
2200P_0402_50V7K
3 G1 D1/S2/K 6 1 D2 G2 8
PR80
4.7U_1206_25V6K
4 5 PR81 PC40 2 7
1
S1/A D1/S2/K 4.7_1206_5% 0.1U_0603_16V7K D2 D1/S2/K
3 6
2
G1 D1/S2/K
1
4 5
1
S1/A D1/S2/K
PC41
PC42
AO4916_SO8
2
1
4.7U_1206_25V6K
LX5 AO4916_SO8
2
PC43
0.1U_0603_50V4Z
VL PR82
2
<50> LX_5V 0_0402_5%
10UH_D104C-919AS-100M_20%
2VREF_1999
1
4.7U_0805_10V4Z
3HG
1
499K_0402_1% 200K_0402_1%
499K_0402_1% 200K_0402_1%
PL7
1U_0805_16V7K
1
2
PC44
PR83
PR84
1
1
BST3A
PC45
PC46
DL5 LX3
2
2 PR85 2
2
2
0_0402_5%
2 1
2 1
18
20
13
17
PR86
BST5A 14
TON
VCC
LD05
V+
1
BST5
PR87
ILIM3 5
16 DL3
DH5
1
+5VALWP
1
15 PL8
LX5 PU14
19 DL5 ILIM5 11 4.7UH_SIQB745-4R7_3A_30%
21 OUT5 MAX1999EEI_QSOP28
9 FB5 BST3 28
10.2K_0402_1%
1 26 DH3
2
N.C. DH3
2
B++ 24
DL3
PR88
6 SHDN# LX3 27
150U_B2_6.3VM
1 4 ON5 OUT3 22
1
47K_0402_5%
2VREF_1999 1 2 3
+ ON3
PC47
PR89 7
1
FB3
PR90
1 2 0_0402_5% 12 2 +3VALWP
@ @ 0_0402_5% SKIP# PGOOD
2 2VREF_19998
0_0402_5% @ 3.57K_0402_1%
PRO#
LDO3
PR91
GND
2
REF
2
2
0_0402_5%
PR93
150U_B2_6.3VM
PR92
PR94
1 2 1
1
0_0402_5%
23
25
10
PC49
+
0.22U_0603_10V7K
PC48
0.1U_0603_25V7K
1
2 1
1
MAINPWON
PC50
2
2
1
PR95 100K_0402_5%
PR96
0_0402_5%
4.7U_0805_10V4Z
VL PR242
+3VLP +3VALWP
1
1
1
3 3
2
PC51
PR97 +3VL
2
499K_0402_1%
2
+3VLP
1
+3VL
PR98 PJP1
100K_0402_5% 2 1
1
PAD-OPEN 2x2m
2
PC52
1
0.1U_0603_16V7K D
2
PQ36 2
RHU002N06_SOT323 G
S RHU002N06_SOT323
3
D PQ37
2
G KBC_PWR_ON <36>
S
3
RHU002N06_SOT323
1
D PQ77
2
G ADP_PRES <28,36,43,44,50>
S
3
4 4
PL9
MAX8743_B+ FBM-L11-322513-151LMAT_1210
10U_1206_25V6M
2 1 B+
1
1
2200P_0402_50V7K
+5VALW
PC53
PC54
2
PR99
2
2 0_0402_5%
1 1
1
1U_0805_50V4Z
2200P_0402_50V7K
4.7U_1206_25V6K
PC56
1
PD19
1
PC55
1
4.7U_1206_16V4Z
1
PR100
2
8
7
6
5
PC57
PC58
20_0603_5%
PQ38 CHP202U_SC70
D
D
D
D
2
AO4422_SO8
2
BST_1.05V_2
BST_1.5V_2 AO4916_SO8
G
S
S
S
1 D2 G2 8
1 2 BST_1.05V_1 2 7
1
2
3
4
PL10 PC59 D2 D1/S2/K
3 G1 D1/S2/K 6
0.1U_0603_50V4Z
3.3UH_MPL73-3R3_6A_20% 0.1U_0603_50V4Z PR101 VCC_MAX8743 4 5
S1/A D1/S2/K
V+ 1U_0805_16V7K
0_0402_5% +1.5VSP
+1.05V_VCCP
1
2 1 2 1 PR102 PC62 PL11
PQ39
PC60
PC61
0_0402_5% 0.1U_0603_50V4Z 3.3UH_SIQB74-3R3RF_4.8A_30%
220U_B2_2.5VM
1 1 2 2 1 1 2
2
8
7
6
5
2.2U_0603_6.3V6K
BST_1.5V_1
1
220U_B2_2.5VM
PC63
PR104
22
1
D
D
D
D
9
PC64
5.1K_0402_1%
PC66
AO4702_SO8 25 21 1 2 DH_1.5V_2 +
UVP
VCC
2
BST1 VDD
1
2 PR103
1
G
S
S
S
5.1K_0402_1%
PR105
2.2_0402_5% DH_1.05V_1 26 19
DH1 BST2 2
PR106
18 DH_1.5V_1
1
2
3
4
LX_1.05V DH2 LX_1.5V
27 LX1 LX2 17
DL_1.05V 24 20 DL_1.5V
2
DL1 DL2
2
16 2
2
CS2
28 CS1
1 OUT1 OUT2 15
FB2 14
2 FB1 ON2 12
PR109
1
PR110 7 @0_0402_5%
PGOOD
10K_0402_1%
PR107 @0_0402_5% 5 2 1 2 1 SLP_S3#
TON VCCP_POK <40>
PR111
100K_0402_1% SLP_S3# 1 2 11 PR108
ON1 0_0402_5%
ILIM2 13
3
SKIP
GND
OVP
2
REF
ILIM1
2
PR112
MAX8743EEI_QSOP28 PR113 100K_0402_5%
23
10
0_0402_5% 2 1
2 1
2VREF PR115
1
D 47K_0402_5%
2 1
100K_0402_1%
2 2 1 +5VALW
1
PR119 VCC_MAX8743 2 1 PR114 G
PR118
100K_0402_5% @0_0402_5% 0_0402_5% S
3
1
2 1 PR117 PQ41
1
D
0.22U_0603_10V7K
PR116 100K_0402_1% RHU002N06_SOT323
PC69
2 2 1
2
PR122 PR120 G PR121 SLP_S3# <26,28,30,31,32,36,38,39,47,48>
2
1
@0.001U_0402_50V7M
47K_0402_5% 0_0402_5% PQ42 S 0_0402_5%
3
+5VALW 1 2 2 Fine tune power sequenceRHU002N06_SOT323
G
PC70
S
3
PQ43
1
D RHU002N06_SOT323 +3VALW
2
<26,28,30,31,32,36,38,39,47,48> SLP_S3# 1 2 2
3 PR123 G 3
1
@0.001U_0402_50V7M
0_0402_5% S PQ44
3
RHU002N06_SOT323 PJP11
PAD-OPEN 2x2m
1.5VSP/ +1.05V_VCCP/+2.5VALWP
1
PC71
+2.5VSP
2
2
PU26
1
2 VIN VO 3
PC134
10U_1206_6.3V6M 1 4 PR244
2
EN ADJ 13K_0603_1%
1
5 7
2
GND GND PC135
6 8 10U_1206_6.3V6M
2
GND GND
1
PR243
G965-18P1U_SO8
10K_0402_5% PR245
PJP2 PJP3 12K_0402_1%
<26,28,30,31,32,36,38,39,47,48> SLP_S3# 1 2
+1.5VSP 1 2 +1.5VS +5VALWP 1 2 +5VALW
2
(4A,160mils ,Via NO.=8) (4.5A,180mils ,Via NO.= 9)
PAD-OPEN 3x3m
PAD-OPEN 4x4m
PJP5
(7A,280mils ,Via NO.= 14) +3VALWP 1 2 +3VALW
(3A,120mils ,Via NO.= 6)
PAD-OPEN 4x4m
PJP6
PAD-OPEN 4x4m
+1.05V_VCCP 1 2 +VCCP (6A,240mils ,Via NO.= 12)
4 4
PJP8 PJP9
+0.9VP 1 2 +0.9V (2A,80mils ,Via NO.= 4) +2.5VSP 2 1 +2.5VS (1A,40mils ,Via NO.= 2)
PAD-OPEN 2x2m
PAD-OPEN 3x3m
PJP10
PAD-OPEN 4x4m Security Classification Compal Secret Data Compal Electronics, Inc.
+VDD_COREP 1 2 VDD_CORE (7A,280mils ,Via NO.= 14) Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2.5VALW/1.5VS/1.05VCCP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 46 of 54
A B C D
5 4 3 2 1
D D
DDR_B+ PL12
FBM-L11-322513-151LMAT_1210
+1.5VS 2 1 B+
2200P_0402_50V7K
1
1
1
0_1206_5%
PC72
PC73
5
6
7
8
10U_1206_25V6M
PR124
2
PQ45 2
D
D
D
D
AO4422_SO8
PR125 PC74
2
0_0402_5% 0.1U_0603_50V4Z
12
7
G
S
S
S
PU17 BST_1.8V_1
1 2 BST_1.8V_2 1 2
PR126
NC
NC
4
3
2
1
0_0402_5%
10U_0805_10V4Z
1
PC76
PC75 23 22 DH_1.8V_1
1 2 DH_1.8V_2 +1.8V
10U_0805_10V4Z VLDOIN VBST 2.2UH_IHLP-2525CZ-01_8A_+-20%_2525CZ
2
24 21 LX_1.8V 1 2
VTT DRVH
C
+0.9VP PL13 1
C
5
6
7
8
1 VTTGND LL 20
DL_1.8V + PC78
D
D
D
D
PQ46 330U_D2E_2.5VM_R15
1
2 19 AO4702_SO8
PC79 VTTSNS DRVL 2
G
S
S
S
22U_1206_6.3V6M
2
3 18
4
3
2
1
GND PGND
22P_0402_50V8J
PR127
0_0402_5%
0.001U_0402_50V7M
1
20K_0603_1%
1 2 4 MODE CS 16
1
<7,13,14> V_DDR_MCH_REF
PC80
0.033U_0402_16V7K
14K_0402_1%
1
PC83
PR129
PR128
PC81
5 14
2
VTTREF V5FILT
4.7U_0805_10V6K
2
2
1
2
PC82
6 TPS51116RGE_QFN24 13 PR130
COMP PGOOD 3_0402_5%
2
2 1 +5VALWP
8 11 PR131
+5VALW VDDQSNS S5 0_0402_5%
Thermal pad
2 1
SLP_S5# <26,39>
CS_GND
9 10 PR132
VDDQSET S3 @ 0_0402_5%
B
V5IN
B
2 1
PR133 SLP_S4# <26>
0_0402_5%
17
25
15
2 1
SLP_S3# <26,28,30,31,32,36,38,39,46,48>
PR134
2 1
@0_0402_5% SLP_S5# <26,39>
@0.001U_0402_50V7M
@0.001U_0402_50V7M
1
1
PC84
PC85
2 10K_0402_1%
PR135
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.8V/0.9VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 47 of 54
5 4 3 2 1
5 4 3 2 1
B+_6269
PL18
D FBM-L11-322513-151LMAT_1210 D
B+ 2 1
10U_1206_25V6M
2200P_0402_50V7K
0.1U_0603_50V4Z
+6269_VCC
1
PC89
PC86
PC87
PR136
1
1 2 1 2 PC90
2
2 PR137 0_0402_5% 0.1U_0402_16V7K
10K_0402_5%
+5VS
1
PR138
5
6
7
8
@0_0402_5%
16
15
14
13
PU28 PQ47
D
D
D
D
17 1 PR139 2 AO4422_SO8
PHASE
PGOOD
UG
BOOT
+6269_VCC
2
GND 2.2_0603_5%
G
S
S
S
1 VIN PVCC 12 1 2 PC91
+6269_VCC
4
3
2
1
2.2U_0603_6.3V6K UG
2 11 1.0UH_IHLP-2525CZ-01_11A_+-20%_2525CZ
VCC LG
1
PR140 LX6269 1 2 +VDD_COREP
PC92 0_0402_5%
2.2U_0603_6.3V6K
0.1U_0402_10V7K
1 2 3 10 PL14
2
FCCM PGND
5
6
7
8
220U_B2_2.5VM
220U_B2_2.5VM
1 1 1
PQ48
D
D
D
D
PR249
PC142
+
PC137
+
PC93
C PR141 C
AO4702_SO8
1 2 4 9 1 2
<26,28,30,31,32,36,38,39,46,47> SLP_S3# EN ISEN 11.5K_0402_1% 2
COMP
G
2 2
S
S
S
TEST
0_0402_5%
1
VO
FB
4
3
2
1
PC136
@0.1U_0402_16V7K LG
2
8
ISL6269CRZ-T_QFN16
49.9K_0402_1%
1
1
22P_0402_50V8J
1
1
57.6K_0402_1%
PC95
PR142
PR143
PC96
0.01U_0402_16V7K
2
2
2
1
PC97
6800P_0402_25V7K
2
PR144
1 2
4.12K_0402_1%
+5VALW
B B
1
+5VS
PC139
PCIE_1.2V 1U_0603_6.3V6M
2
PR145 +1.5VS
1
1
1 2
PR246 PR6
100K_0402_1% 1K_0402_1%
49.9K_0402_1%
6
PU27
1
1
5
VCNTL
2
2
PR147 VIN PC138
7 POK
1
2
VIN
2
PR146 G 3
2
VOUT
1
10K_0402_5% PQ66 D
S
3
GND
1
S 2
3
RHU002N06_SOT323 FB PC141
APL5912-KAC-TRL_SO8 22U_1206_6.3V6M
2
1
1
PR247
1K_0402_1% PC140
2
0.01U_0402_16V7K
2
2005.08.30
POW_SW VDD_CORE
1
High 0.95V PR248
A Low 1V 2K_0402_1% A
2
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VDD_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 48 of 54
5 4 3 2 1
8 7 6 5 4 3 2 1
+CPU_B+ PL15
FBM-L18-453215-900LMA90T_1812
1 2 B+
68U_25V_M
2200P_0402_50V7K
4.7U_1206_25V6K
0.01U_0402_50V4Z
H 1 H
PC148
10U_1206_25V6M
+
1
1
PC100
PC103
PQ50
PC101
PC102
5
SI7840DP_SO8 2
2
2
+CPU_B+
PR148
+5VS 0_0402_5% 4
2 1
BST_CPU1_2
BST_CPU1_1
2
1U_0603_10V6K
PR149
3
2
1
1
PC104
10_0603_5%
PC105
0.01U_0402_25V7K
2
PU18 0.22U_0603_16V7K
G 5 1 1 2 PL16 G
VCC BOOT
6 8 DH_CPU1 .36UH_MPC1040LR36_ 24A_20%
FCCM UGATE
1
PC106
2 7 LX_CPU1 1 2 +VCC_CORE
PWM PHASE
2
3 4
2
GND LGATE
D 8
D 7
D 6
D 5
8
7
6
5
PR150
FDS6676AS_SO8
FDS6676AS_SO8
ISL6208CRZ-T_QFN8 10_0402_1%
D
D
D
D
+5VS
PQ52
PQ53
PR151 PC107
10K_0402_1% 0.22U_0603_16V7K
1
+3VS
10_0603_5%
1 2 2 1
4 G
G
1 S
2 S
3 S
S
S
S
1
2
3
4
2
PR152
PR153
1 5.11K_0402_1% 2 PR154 1
2
1U_0603_10V6K
@0_0402_5%
1
1
F PR155 F
PC108
1.91K_0603_1% VSUM VO
2
DL_CPU1
1
1 2
PR156 VGATE_INTEL<7,26> +CPU_B+
0_0402_5%
PC109 +5VS
2 1 NTC 19
VGATE
20
18
39
40
2200P_0402_50V7K
0.01U_0402_16V7K ISL6260CRZ-T_QFN40 PR157
4.7U_1206_25V6K
0.01U_0402_50V4Z
0_0402_5% PQ54
VSS
3V3
VDD
VIN
PGOOD
PR158 2 1 SI7840DP_SO8 1
1
PC110
1U_0603_10V6K
0_0402_5%
BST_CPU2_2
BST_CPU2_1
PC111
PC112
2 1 4 PC113
<4> H_PROCHOT# VR_TT#
1
10U_1206_25V6M
PC114
4
2
PR159 1 PWM1 2
2 3 RBIAS PWM1 27
147K_0402_1% PH2
2
E E
2 PR160 1 2 1 NTC 5
4.22K_0603_1% PC115 NTC PC116
3
2
1
2 1 470KB_0402_5%_ERTJ0EV474J 6 23 ISEN1 PU20 0.22U_0603_16V7K
SOFT ISEN1 PL17
5 VCC BOOT 1 1 2
0.015U_0402_16V7K PU19
2 PR1611 28 6 8 DH_CPU2 .36UH_MPC1040LR36_ 24A_20%
<5> CPU_VID0 VID0 FCCM UGATE
<5> CPU_VID1 2 PR162 1 0_0402_5% 29 VID1
0_0402_5% 2 PR163 1 30 26 PWM2 2 7 LX_CPU2 1 2 +VCC_CORE
<5> CPU_VID2 VID2 PWM2 PWM PHASE
<5> CPU_VID3 2 PR164 1 0_0402_5% 31 VID3
2
0_0402_5% 2 PR165 1 32 3 4
<5> CPU_VID4 VID4 GND LGATE
D 8
D 7
D 6
D 5
8
7
6
5
2 PR166 1 0_0402_5% PR167
FDS6676AS_SO8
<5> CPU_VID5 33 VID5
0_0402_5% 2 PR168 1 ISEN2 ISL6208CRZ-T_QFN8
FDS6676AS_SO8
34 22 10_0402_1%
D
D
D
D
<5> CPU_VID6 VID6 ISEN2
PQ56
PQ57
0_0402_5% PR170 PC117
2 PR169 1 37 10K_0402_1% 0.22U_0603_16V7K
1
<4,25> H_DPRSTP# 0_0402_5% DPRSTP#
1 2 2 1
4 G
G
1 S
2 S
3 S
S
S
S
2 PR171 1 36 41
<7,26> DPRSLPVR DPRSLPVR CS_GND
1
2
3
4
2
2 PR172 1 499_0402_1% 1
D
<5> H_PSI# 0_0402_5% PSI# PR173 D
2 PR174 1 2 24 5.11K_0402_1% 2 PR175 1
<40> PGD_IN 0_0402_5% PGD_IN FCCM
2 PR176 1 38 PR177 @0_0402_5%
1
<15,40> CLK_ENABLE# 0_0402_5% CLK_EN#
2 1 +5VS
<21,36,39,40,50> PWR_GD 2 PR178 1 35 0_0402_5% VSUM VO
0_0402_5% VR_ON
12 25 DL_CPU2
<5> VCCSENSE VSEN PWM3
13 RTN
+VCC_CORE 2 1
PR179 PC118 21
10_0402_1% ISEN3
2 1 11 VDIFF
PR180 PC119
10_0402_1% 1000P_0402_50V7K 2 1
2 1 10 FB
1000P_0402_50V7K PR181
OCSET 7 2 1
9 11.5K_0402_1%
C <5> VSSSENSE COMP C
PR182 PC120 17 VSUM
VSUM
3K_0402_1%
2 1 1 2 2 1
PR185
DROOP
2 PR184 1 0_0402_5%
1.2K_0402_1%
DFB
1
VO
0.22U_0603_16V7K
PC122
4.53K_0402_1%
2
2
PR186
PC123
1 2 2 PR187 1
14
15
16
51K_0603_1%
1
PC124 PC121
2
1 2 0.022U_0402_16V7K
0.1U_0402_16V7K
220P_0402_25V8K PC125 VO
10KB_0603_5%_ERTJ1VR103J
2 1
1000P_0402_50V7K
1
PC126
PR188
2 1
1
B B
@1K_0402_1%
PH3
6.19K_0603_1% 1K_0402_1%
PR189
2 1 2 1
2
PC127
2 1
330P_0402_50V7K
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-2821
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 49 of 54
8 7 6 5 4 3 2 1
5 4 3 2 1
PQ72 +5VS
+5VS PD20 NDS0610_SOT23
+3VS CH751H-40_SOD323
S
1 2 1 2 1 3
1
+5VS
PR259 PD21
PR193
1
PU22A 1M_0402_1% CH751H-40_SOD323
G
2
8
1U_0805_16V7K
PR194 PR192 1 2
PC128
3 330K_0402_5% PR256 133K_0402_1%
P
D D
2
+ 100K_0402_5% PR257
1 0 2 1
P4
220K_0402_5%
2 10K_0402_5%
2
-
G
220K_0402_5%
PU22B PU21B PU21A 10K_0402_5%
PR197
2
2
0_0402_5%
0_0402_5%
LM358A_SO8 5 3
P
4
2
+ +
1
PR196
PR195
1 2 5 + O 7 O 1
PR251
PR252
6.81K_0402_1% 7 6 2
0 - -
G
1 2 1 2 6 PR208
2
PR199 PR200 - LM393M_SO8 LM393M_SO8 10_0402_5%
1
4
10K_0402_1% 100K_0603_0.5% PR201
2
1
2K_0402_5%
LM358A_SO8 1 2
2
PR202
0_0402_5% 1 2
80.6K_0402_1%
1U_0805_50V4Z
PR203
PQ70
1
PC130
0.027U_0402_16V7K
1 2 604K_0603_1% LX_5V <45>
MMBT3906_SOT23
DTA144EUA_SC70
PR205
2
PC129 VIN
2
1
PQ58
39.2K_0402_1%
PC131
0.22U_0603_16V7K
2
3
7.87K_0402_1%
E
3 1
2
B
2
2
PR206
PR260
PR207 PD28
47K
C
3.9K_0402_5% 1SS355_SOD323
47K
1
PU23
3 2
1 2
1
S PD22
4 3 @CH751H-40_SOD323
REF CATHODE
1
G
2 1 2 PR254
PR211
422_0603_1%
PR210
2 PWR_GD <21,36,39,40,49> 150K_0402_5% PR253
NC
NDS0610_SOT23
1SS355_SOD323
0.1U_0402_16V7K
1
1
2
PQ73
PC132
5 1 0_0402_5%
2 2
ANODE NC
PD24
C C
2
2
1
LMV431ACM5X_SOT23-5 D
470K_0402_5%
2 PQ60 PD27 ADP_SIGNAL
1
G 1SS355_SOD323 +3VS
RHU002N06_SOT323
PR215
S PR255 PD26
1
1
1
1
PR261 <38> ACOCP_EN# PQ71 D
RHU002N06_SOT323
1 2 1 2
1
PR212 1M_0402_1% 2
0_0402_5% PQ61 G
B+ ADP_PRES
1
<28,36,43,44,45>
C MMBT3904_SOT323 1K_0402_5% 1SS355_SOD323
S
1 2
3
2
2
B I_A D
<44>
PR217 E 2 PQ74
3
3
CFET_B <44>
1
PR265
PQ62 2005.8.24 47K_0402_5%
NDS0610_SOT23
ADP_SIGNAL PD25
2
3900P_0402_50V7K
3.9K_0402_5%
S
3 1 2 1
1
1
PR214
VIN 1SS355_SOD323
PC147
G
2
1
VIN
1
PR223 +3VL 2
1
137K_0402_1% PR224 +3VS
B 22.6K_0402_1% B
1
PC146
2
2
8
1
0.1U_0603_16V7K PR219 +5VS
3
P
PR216
2
+ PR221 1M_0402_5% PR218
O 1
2 10K_0402_5% 2 1 1 2 10K_0402_5%
-
1
2
470K_0402_5%
8
10K_0402_1% 10K_0402_5% PU24A
+3VS
1 2 3
P
ADP_ID <36> ACN <43> + ADP_PS0 <36>
1
2
PR229 O
2 -
G
1M_0402_5%
1 2 PR222 LM393M_SO8
4
<43> SRSET 71.5K_0402_1% +3VS
2
1
2
PR235 1M_0402_5% @100K_0402_5% PR226 +5VS
1
10K_0402_1% VIN 1M_0402_5%
1 2
1
1
1 2
1
8
5 PR230 21K_0603_1% PU24B
P
2
+ 47K_0402_5%
7 1 2 5
P
2
1 2
O PR231 PR233 +
6 - O 7
1
D 220K_0402_5% 100K_0402_5% C
ADP_EN <36> 6 ADP_PS1 <36>
2
G
47K_0402_5%
2
1
4
1
D
0_0402_5%
PR237
S PQ65 E
3
A A
1
PR240
@RHU002N06_SOT323 2 PQ64
2
PR241 G RHU002N06_SOT323
1
220K_0402_5%
10K_0402_1% S
2
PD23
2
PR239
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ADP_OCP
ADP_EN# <43> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2821
2005.8.20 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 50 of 54
5 4 3 2 1
1 2 3 4 5
06/11/2005 06/24/2005
EE PIR list
Page28: 1.Delete R15 ,due to Internal PD Page19 : Add LVDS L-shape BOM option resistors
2.Delete R69 ,due to Internal PD
06/01/2005 schematics review start : 3. Add U70,U71,R69,R92 R1297 for serial falsh support.
Page10 : Enable TV/ CRT when using 945PM
06/02/2005 Page9 : Enable TV/ CRT when using 945PM
Page38 : Add R58,R59,R60 ,those are removed from daughter board Page19 : Add T8/T9 for GPIO10/14 06/25/2005
Page39 : JP18 pin3 change from ground to BT_LED Page23 : Change L1,L2,L63,L6,L7,L9,L11-16,L65,L66 to FB Page33 : Delete U58, R165,C568,C1,C312,C311 FOR LAYOUT SPACE
Page37 : Remove JP16 & change debug port interface to JP44 Page30 : Disconnect the I2C bus / WL_LED#/WP_LED# on JP46 06/27/2005
1
Page27 : ICH7M pin R7 change to +3VS Page10 : 1. Add R504/R505 for VCC_SYNC Change All 2N7002_SOT23 to RHU002N06_SOT323 to save layout space 1
Page32 : JP44 PLT_RST# change to PLT_RST_B# to reduce the loading 2. Add R490/R491 for VCCTX_LVDS
3. Add R494 for VCCA_CRTDAC 06/28/2005
Page33 : Update audio amp to MAX9710 4. Add R492/R493 for VCCA_LVDS Page40 : Change Q10,Q11,Q15,Q26 from SOT23 to SOT323
5. Add R495 for +3VS_TVBG to save layout space
06/03/2005 Page37 : 1 . Update JP20 to 6 pin connector
Page10 : Add R260 to reduce one 330U cap C666 6. Add R500 for +3VS_TVDACA
7. Add R502 for +1,5VS_TVDAC 2. Update JP20 & JP18 pin assignments to follow Taos
Page25 : 1. R27 change to +3VS 7. Add R499 for +3VS_TVDACB
2..Add R1035 for H_DPSLP# 8. Add R496 for +3VS_TVDACC 06/30/2005
Page28 : Y1 update to smaller package 6x3.5
Page26 : 1.Add T80 for GPIO25 Page09 : 1.Add R460,R461, R550,R552,R553 for CRT discrete/uma option
2. GPIO21 change net name to VGARST# 2. Add R462,R463,R464 for TV discrete/uma option Page25 : Y4 update to smaller package 14M-J
3. Add T88 for GPIO23 Page15 : Y3 update to smaller package 6x3.5
4. Add T89 for GPIO26 06/13/2005
5. GPIO30 change net name to USB_OC#6 07/01/2005
6. GPIO31 change net name to USB_OC#7 Page23 : Add R6 R15,R106,R128,R129 GPIO PD Page23 : Add HW strpping pin on DVPDATA20,21,22,23 for VRAM ID0,1,2,3
7. Add R1036/7 for RESET option Page33 : U57 change to 2A current limit power switch G548
8. Remove the connection of USB_OC#3/4/5 06/14/2005
Page21 : Change L1,L2,L63 to FB
07/04/2005
Page24 : Add ALS_EN on JP35 pin24 for light sensor Page17 : Add R131 for inverter PWM when ATI PWM issue
Page16 : 1. Add C174,C150,C142,C371,C358 for DVI
Page32 : 1.JP13 change to 90 pins connector 2. R103 change to 1% Page19 : 1. Add R49 , R189 for 1.2V voltage divider
2.Add U72 for ESD protection Page35 : U69 pin7 change to PD 2. Add Q12 for M52_therm# & change to GPIO14
2
Page32 : The limitation for 5 pin audio jack can't switch 2
Page38 : Pin96: INVPWM rename to OUT9 & add T90 Page18~23 : ATI VGA controller change to M52T
07/19/2005
Page36 : Delete R500 & rename to EXPCRD_RST# 06/22/2005 Page39 : Add C91,C93,C181 for low speed signal
Page35 : Add JP3 for Smart card FFC connector Page09 : Add R554 , R555 for CRT disable 07/20/2005
Page10 : 1. Add R508,R510 for VCCD_LVDS1/1/2
2. R504,R505 chnage for +2.5VS_GMCH,&delete R490,R491,R492,R493 Page30 : Add R1422 pad for XMIT_OFF
06/08/2005 Page30 : Delete JP48,49 & change screw holes
Page7 : Delete PD resistor R1340~R1343.
Page17 : Update JP35 LVDS connector
06/23/2005
Page16 : Change SDVOB_INT+/- net name to PEG_RXP1/N1
Page26 : A. GPIO28 ==Delete R1321 & A_SD , change to VGA_RST#
B. GPIO21 ==Change to MB_PWR Page10 : 1.R505 / R510 for M52 , R504 / R508 for UMA
C. GPIO19 ==Change to PD 2. R499,R500,R496 connect to +1.5VS for diable CRT
06/10/2005
Page17 : Add R458,R459 for ch_data,ch_clk
Page33 : Add C367 0.1U for +SC_PWR Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/05/26 Deciphered Date 2006/07/26 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H/W2 EE Dept. PIR SHEET
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 51 of 54
1 2 3 4 5
1 2 3 4 5
Page07: NI R1209 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H/W2 EE Dept. PIR SHEET
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 52 of 54
1 2 3 4 5
1 2 3 4 5
04/07/2006
Page16 : Change C310,C313,C314 to 18P
For CRT EMI issue
Page19 : Change L23,L24,L25 to 0 ohm;C182,C180,C181 to 12P
Change L18,L19,L20 to 39nH inductor
For CRT EMI issue
1 04/19/2006 1
04/28/2006
Page17 : UnIstall R501, duplicate PD resistor
Page28 : Install R1022 and UI R1021
For clock can't shut down under DC mode
2 2
3 3
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
H/W2 EE Dept. PIR SHEET
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-2951 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, April 28, 2006 Sheet 53 of 54
1 2 3 4 5
5 4 3 2 1
10/18/2005
4 43 HP sets Max charge current to 3.75A) Change PR29 from 100K to 143K_1% SI
(SI)
12/06/2005
5 50 43 HP Changes for OCP circuit PR225 is open and PR26.2 connects to PQ63.1 SI
(SI2)
12/12/2005
6 50 Compal Correct PR223 value. Correct PR223 from 180K to 137K SI2
(SI2)
12/19/2005
7 47 Compal DRR2 issue Change PC78 from 220u to 330u SI2
(SI2)
Delete PC81,PR127
12/21/2005 OTS#181928
B
8 49 Compal Add PC148(68uF) SI2 B
A A