Professional Documents
Culture Documents
2017 Noise and Non-Linearity Analysis of A Charge-Injection-Cell-Based 10-Bit 50-MSs SAR-ADC PDF
2017 Noise and Non-Linearity Analysis of A Charge-Injection-Cell-Based 10-Bit 50-MSs SAR-ADC PDF
Marcel Runge, Student Member IEEE, Dario Schmock and Friedel Gerfers, Member IEEE
Chair Mixed Signal Circuit Design
Technische Universität Berlin, Germany
Email: marcel.runge@tu-berlin.de
Abstract—This paper presents a detailed noise and non- DAC+ MSB MSB-1
linearity analysis of a 10-bit 1.2 Vppd 50 MS/s charge-injection DAC-
based SAR-ADC designed in a 65 nm low power process. Being MSB-2
more area-efficient in contrast to a conventional capacitor DAC, a
charge-injection-cell-based DAC allows to reuse its DAC cells dur-
ADC output
ing binary search. Based on extensive calculations and transistor- CS CS t
Ser2Par
DAC+
level simulations, the charge-injection cell design tradeoffs are VIN+
analyzed and optimized to maximize the overall ADC linearity VIN- DAC-
and ADC input range. Extensive system level simulations in
MATLAB evaluate the jitter sensitivity of the ADC. Combining CIC-DAC
the transistor-level and system level simulations, a detailed noise
study of the 8.86-bit ENOB ADC completes the evaluation.
32CICs CMP-
I. I NTRODUCTION CIC CIC CIC CMP+
Transfer
CmpClk
With emerging wireless technologies, the demand for en en en
medium-speed high-resolution low-power ADCs constantly
increases. In recent years, charge-redistribution SAR-ADCs
have become the choice for achieving highest conversion effi- CLK Finite State Machine
ciencies. However, the non-reusable nature of a conventional
capacitor DAC during binary search limits the SAR-ADC
from further reducing its area. Additionally, residual settling Fig. 1: Charge-injection cell (CIC) based SAR inspired by [2].
from previous decisions during binary search limits the SAR- The area-efficient CIC-DAC is formed by N reusable unary-
ADC from achieving high resolution. By adding redundancy, weighted cells each deducting a fixed charge from one of
the SAR-ADC is able to recover from false decisions up the sampling capacitors if enabled during binary search. The
to a certain point since a conversion radix less than two is algorithm during binary search is similar to the set and down
used. However, this often implies a power and area hungry capacitor switching presented in [3] as depicted in the transient
digital code converter at the ADC output [1]. To overcome plot.
those limitations, [2] introduced a very power and area-efficent
1 GS/s charge-injection-cell SAR (ciSAR) reusing the unary-
weighted cells in the DAC during binary search. With a
600 mVppd peak-to-peak input voltage an ENOB of 5.46-bit multiple times since they are reset after each step during binary
was achieved. Based on the idea of [2], this paper presents search. This reusability enables a large area-efficiency [2] and
a 8.86-bit ENOB 50 MS/s SAR-ADC suitable for wireless is exemplary illustrated in the transient plot in Fig. 1. The MSB
technologies demanding high resolution medium bandwidth is determined first. Then, all unary-weighted CICs are turned
converters. on two times in a row deducting each time a fixed amount of
charge from the sampling capacitance. Subsequently, MSB-1
II. C HARGE -I NJECTION SAR-ADC ( CI SAR) is resolved. The charge deducted from the sampling capacitor
Fig. 1 depicts the charge-injection SAR-ADC described in for one binary search step is
this paper. First, the differential input voltage is sampled onto
the sampling capacitors CS . Then during binary search, similar QDAC = K · M · QCIC , (1)
to the set-and-down switching scheme presented in [3], charge
is deducted from either one of the sampling capacitors based
on the previous comparator decision. The amount of charge per where K denotes the number of repetitions, M the number of
step is determined by a charge-injection cell DAC employing CICs enabled, and QCIC the LSB charge from one charge-
32 unary-weighted charge-injection cells (CIC). In contrast injection cell. The in this paper presented 10-bit switching
to a conventional capacitor array, the CICs can be reused scheme is depicted in Tab.I.
900
0
DAC- DAC+ 899
20 40 60 80 100
IDAC- IDAC+ CMP+
SW+ G3
M1 G1
Enable 30
SW- G2 G4
M2 CMP- 20
10
Vx
M3 Cu M4 0
VDD Transfer 20 40 60 80 100
1.5
Fig. 2: The charge-injection cell [2] employs two switch
transistors M1/M2, long-channel transisors M3 mainly defining 1
the parasitic capacitance Cu and reset transistor M4. Due to
the transfer pulse, a fixed amount of charge is subtracted from 0.5
either one of the samplings capacitors CS . Major Cu contrib-
utors are CDD,M3 = 420 aF and CWiring = 320 aF (layout 0
extracted) for a reservoir node voltage of Vx = 410 mV. 20 40 60 80 100
1026
1.3 IV. N OISE -A NALYSIS
In order to calculate the SNDR of the presented ADC,
1.25 all noise sources in the ADC are referred to the ADC input,
leading to
1.2
VS,RMS
(12)
Here, νq denotes the quantization noise, νtj the jitter in-
1
0.4 0.6 0.8 1 1.2 duced noise caused by the transfer pulse, νCIC the thermal
noise from the CIC-DAC, νcmp the input-referred thermal
comparator noise, and νkT/C the kT/C sampling capacitor
Fig. 4: LSB voltage across the sampling capacitor voltage noise. Given the reuse of the CICs during binary search,
VDAC+ for the designed CIC seen in Fig. 4. The LSB is CIC non-linearities do not appear as harmonic distortions but
calculated by Eq. 9. Below VDAC+ = 600 mV, the LSB starts spread as spurs across frequency in spectral performance plots.
to degrade significantly. Since transistor M1 enters the triode νq,NL denotes the additional quantization noise caused by CIC
region, net Vx shows data dependency. Subsequently, LSB- non-linearities. Throughout the paper, all noise sources are
defining parameters such as the parasitic capacitance change. assumed uncorrelated. A noise-free transient simulation shows
58.5 dBFS SN DR√ at Vin = −1 dBFS. Given a quantization
noise νq = LSB/ 12 = 339 μV, the additional quantization
noise caused by CIC non-linearities is
search. For a constant LSB charge QCIC , net Vx must not √
follow the common mode voltage as described in Eq. 3. Thus, Vinppd /2/ 2
the transistors M1/M2 have to operate in saturation at the end νq,NL = 58.5 − νq2 = 374 μV (13)
10 10
of the transfer pulse t = tpulse leading to
The comparator used in this design is a strong arm latch includ-
VDAC+ − Vx ≥ VDD − Vx − VTH,M1 . (6) ing a three-stage preamplifier. The input-referred comparator
noise νcmp is determined by the comparators probability
With a switching scheme similar to the monotonic switching density function described in [5], leading to νcmp = 440 μV.
scheme, the common mode voltage at the end of the binary Given a differential sampling capacitor of CS = 1 pF, the kT/C
search is noise is νkT/C = 91 μV which is negligible compared to the
VCM,min = VDD − Vinppd /2, (7) previous calculated noise sources.
In order to evaluate the impact of jitter-induced noise
where Vinppd denotes the differential ADC peak-to-peak input
caused by the transfer pulse, a high-level MATLAB model
voltage. Substituting VDAC+ in Eq. 6 by Eq. 7, the maximum
is designed. Generally speaking, the transfer pulse jitter has
input voltage swing is
to be split into a jitter contribution acting locally within one
Vinppd ≈ 2 · VTH,M1 . (8) CIC and a jitter contribution that is seen by all CICs at the
same time. The local jitter contribution is mainly defined by the
In order to maximize the input voltage swing and simultane- gates G1 and G2, respectively depicted in Fig. 2. However, the
ously minimize leackage current through M1 and M2, high local jitter contribution of 50 fs is significantly smaller than the
threshold voltage (HVT) devices are used. A maximum peak- jitter of 400 fs induced by the global transfer pulse generation
to-peak input voltage of Vinppd = 1.2 V is achieved with the circuit. Thus, the local jitter contribution is neglected in the
presented design as depicted in Fig. 4. Here, the LSB is shown following modeling. The during binary search for one binary
across VDAC+ . First, VDAC+ = 1.2 V is sampled onto the decision subtracted charge QDAC is defined as
positive sampling capacitor CS . Then, one CIC periodically K
discharges the sampling capacitor by QCIC (VDAC+ ). The LSB QDAC = QCIC−DAC (e, tj,pulse ) , (14)
is defined as n=1
LSB (VDAC+ (i)) = VDAC+ (i) − VDAC+ (i + 1) (9) where K depicts the number of repetitions and tj,pulse the
transfer pulse jitter. Each element en in e enables (1) or
CS
= , (10) disables (0) the corresponding CIC
QCIC (VDAC+ )
eT = ( e1 , e2 , . . . , eN ) . (15)
where i denotes the consecutive iteration parameter. For a
Assuming that at the end of the transfer pulse, the CIC current
peak-to-peak input voltage of Vinpp = 600 mV, the LSB
is mainly defined by IDS,M3 as shown in Fig. 3, QCIC−DAC
spreads by about ±5% across voltage. Additionally, the LSB
is defined as
shows a low temperature dependency of only 50 μV across
temperature. QCIC−DAC = eT · 1 · (QCIC + IDS,M3 · rand (tj,pulse )) , (16)
1027
62 0
61 -20
-40
60
-60
59
-80
58
-100
10-13 10-12 0 0.5 1 1.5 2 2.5
107
Fig. 5: Plot showing the SN DR degradation across the trans-
Fig. 6: Spectral performance of full ADC transistor-level sim-
fer pulse jitter tj,pulse . The MATLAB model is introduced in
ulation (1024 samples) with transient noise enabled (fmax =
Eq. 16. The charge depends on the equilibrium current IDS,M 3
40 GHz). 8.86-bit ENOB is achieved. The transfer pulse jitter
as seen in Fig. 3.
is tj,pulse = 400 fs.
from one of the sampling capacitors. With the above described q,NL
12%
26% 2
MATLAB model, the impact of the transfer pulse jitter tj,pulse kT/C
on the SN DR is evaluated in Fig. 5 for different currents 2%
IDS,M3 . For each pair of values, 1024 samples are digitized
per simulation and the obtained SN DR is averaged over 100
simulations. With the through transistor simulations obtained
transfer pulse jitter of tj,pulse = 400 fs and the equilibrium
current at t = tpulse of IDS,M3 ≈ 8 μA, a SN DR degradation
of 1.8 dB is expected. This corresponds to an input-referred 2
2
jitter-induced noise of νtj = 245 μV. To calculate the noise q
cmp
contribution of the CIC-DAC νCIC , a full-transistor simulation 20% 36%
with transient noise enabled is performed. As depicted in
Fig. 6, the 1024 point long simulation shows a spectral Fig. 7: Percentage contribution of calculated uncorrelated noise
performance of SN DR = 55.1 dBFS. Applying Eq. 12 to sources
Eq. 11, resolving for νCIC , and then applying the previously
calculated noise contributors results in a CIC-DAC thermal-
noise contribution of νCIC = 150 μV. Fig. 7 illustrates the contributions were calculated and transferred to the input
percentage contribution of each calulated noise source. revealing performance limiting factors.
V. C ONCLUSION R EFERENCES
In this paper, a 10-bit 50MS/s charge-injection-based SAR- [1] B. Murmann, “Digitally assisted data converter design,” in ESSCIRC
2013 - 39th European Solid State Circuits Conference, pp. 24–31.
ADC (ciSAR) design using 32 unary cells was presented. The
[2] K. D. Choo, J. Bell, and M. P. Flynn, “27.3 Area-efficient 1GS/s 6b SAR
charge-injection DAC allows a reuse of its cells in contrast to a ADC with charge-injection-cell-based DAC,” in 2016 IEEE International
conventional capacitive DAC. While being more area-efficient Solid-State Circuits Conference (ISSCC), pp. 460–461.
than their counterparts, the LSB is defined by an operating- [3] C.-C. L. et al., “A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13um CMOS
point-dependent strong-nonlinear parasitic capacitance. Thus, Process,” in Symp. VLSI Circuits Dig. Tech. Papers, 2009, pp. 236–237.
this paper developed a design strategy to maximize the ciSAR [4] Z. Cao and S. Yan, Low-Power High-Speed ADCs for Nanometer CMOS
input range to 1.2 Vppd and to minimize the non-linearites Integration, ser. Analog Circuits and Signal Processing Series. Springer,
caused by the voltage-dependent LSB. Based on an optimized 2008.
charge-injection cell design, the noise performance was ana- [5] I. E. Opris, “Noise estimation in strobed comparators,” Electronics
lyzed. Due to the pulse-triggered nature of the charge-injection Letters, vol. 33, no. 15, p. 1273, 1997.
cell, a system-level model of the ciSAR was developed tak-
ing into account the pulse width jitter. ADC transistor-level
simulations showed an ENOB of 8.86-bit. Lastly, all noise
1028