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Sample Final Exam EECS388 - Fall 2020
Sample Final Exam EECS388 - Fall 2020
Sample Final Exam EECS388 - Fall 2020
NOTE: the final exam is cumulative. This document only includes sample questions
from the second half of the class.
Exam Guidelines:
10. Interrupts can happen at any time and but they cannot stop the
execution of the processor at any time. (T/F)
14. Process Control Block (PCB) is used for context switches in an OS.
(T/F)
20. L&L bound can prove that a task set is not schedulable with RMS.
(T/F)
21. The exact schedulability test calculates the total interference caused
by higher priority tasks for a lower priority task. (T/F)
5.000 V = Vref
2. Consider the following connection between a microcontroller and a
DAC.
Part 1) Complete the function below to generate a step ramp considering
the resolution of the DAC.
𝐴1 𝐴2 𝐴3 𝐴4
𝑉𝑜𝑢𝑡 = 𝑉𝑟𝑒𝑓 ( + + + )
2 4 8 16
A3 A2 A1
µcontroller DAC
A4
int step_ramp()
{
int i = 0;
unsigned int ramp = 0;
for (i = 0; i < _________________ ; i++ ) {
uint8_t val = *(volatile uint32_t *) (GPIO_CTRL_ADDR +
GPIO_OUTPUT_VAL);
val &= ________________;
val |= ramp;
ramp = (ramp + 1) % 256;
*(______________ *) (GPIO_CTRL_ADDR + GPIO_OUTPUT_VAL)
= val;
}
return 0 ;
}
Part 2) What happens if we remove the line that is highlighted with blue?
2ms
10 V
0
10ms
4. Assume that you have a processor that is connected over a network
adapter to the Internet. The network adapter receives packets with the
following inter-arrival time distribution:
10. Do you advise saving the content of the register file inside the
processor hardware or inside the software when an interrupt occurs?
Justify your choice?
11. Does the following figure show a valid case of handling interrupts
with the following priority levels?
2.5ms 2.5ms
20ms 20ms
1ms 1ms
22ms 22ms
2.5ms 1ms
21ms 21ms
17. What are the possible values of the counter after the execution of the
following threads?
Thread 1 Thread 2
R1 = load (counter); R2 = load (counter);
R1 = R1 + 1; R2 = R2 – 1;