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LAB REPORT

ON

ADVANCED VLSI DESIGN LAB

EC-17203

SUBMITTED BY:

NAME: Divya Singh


REG NO.: 20175012
GROUP: ECE-2
B. TECH: 7TH SEMESTER (2020-21)
SUBMITTED TO:

DR. VIJAYA BHADAURIA

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

MOTILAL NEHRU NATIONAL

INSTITUTE OF TECHNOLOGY

ALLAHABAD-211004
Index

Exp. Experiment Exp. Date Sub. Remarks


No. Date
1. To design and Simulate CMOS Inverter using
SymicaDE Tools. 24/08/2020 02/09/2020

2. To design and simulate CMOS XOR2 using


SymicaDE tool. 02/09/2020 09/09/2020

3. To design and simulate CMOS NAND and NOR


using SymicaDE tool. 09/09/2020 19/09/2020

4. To design and simulate NAND gate using pseudo


NMOS logic using SymicaDE tool. 19/09/2020 23/09/2020

5. To design and simulate Ring Oscillator using


SymicaDE tool. 23/09/2020 30/09/2020

6. To design and simulate 6T RAM using SymicaDE


tool. 30/09/2020 06/10/2020

7. To design and simulate 2:1 MUX using SymicaDE


tool. 06/10/2020 04/11/2020

8. To design and simulate D Flip Flop as Master


slave using SymicaDE tool. 04/11/2020 11/11/2020

9. To design and simulate CS Amplifier SymicaDE


tool. 11/11/2020 18/11/2020

10. To design and simulate Current Mirror Circuit


SymicaDE tool. 18/11/2020 25/11/2020

11. To design and simulate Differential Amplifier 25/11/2020 27/11/2020


using Symica DE.

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