Professional Documents
Culture Documents
Peds 400 PDF
Peds 400 PDF
I. INTRODUCTION
Nowadays, for increasing use in practice and fast developing
of high power devices and related control techniques,
multilevel inverters have become more attractive to
researchers and industrial companies. Two common inverter
topologies are NPC and cascaded multilevel inverters (Fig.1
and 2). In recent days, for reducing hardware construction Figure 2: 3-phase Cascaded multilevel inverter
cost, it has been shown a try to develop prospective hybrid
multilevel inverters. There are basically three PWM schemes The comprehensive correlation between carrier based PWM
for controlling multilevel inverters as: Carrier based PWM, and SVPWM have been derived in the recent work [1],[2].
space vector PWM and selective harmonics elimination Compared to the space vector PWM methods, the carrier
PWM methods. based PWM methods can be advantageously utilised in: 1)
controlling common mode voltage, 2) controlling of
complicated inverter topologies as 4-leg, 5-leg-,... multilevel
inverters, 3) compensation of unbalanced dc sources. It will
be shown that the carrier PWM technique can become a
possible solution for some approximate PWM methods,
which use one or two switching states in a switching state
sequence and produce reference voltages with certain
voltage error. The drawbacks as nonlinear control
characteristics and existence of low-order harmonics of
output voltages will be compensated by reduced number of
switchings in each sampling time period. A common
characteristic of carrier based approximate PWM methods is
that the offset function can be properly designed to control
the PWM performance. Single state space vector PWM
method has been described in some recent paper [3], one of
its drawback is the limitation of output voltage range. The
methods of selecting the voltage vector in Direct torque
control and hysteresis current loop control for AC motor
drive systems are some typical and well-known applications
Fig. 1: a) 4-leg 5-level NPC inverter; b) c) and d) Analysis of inverter of single state PWM technique. In the paper, the carrier
voltages
based single state PWM will be proposed for minimum
voltage error. The only controllable parameter of this method
is the offset voltage, which does not influence on the active where n( x ) = Int (v xref ); x = a, b, c . (7)
voltage but able to set approximately common mode voltage G T
and balance switching losses. In the paper, it will be shown Each components of vector L = [ La , Lb , Lc ] presents
that any PWM scheme of multilevel inverter can be centered possibly a lower level of phase leg voltage in a switching
in a nominal two-level switching state diagram. This makes state sequence.
the PWM study to become more advantageous and Nominal switching time diagram: To investigate
comfortable. The proposed method is explained for NPC commutation process in a triangle period, a vertical shift of
inverters, its proper modifying can be also applied to cascade G T
topologies. coordinates by the vector L = [ La , Lb , Lc ] can be
implemented as shown in Fig.4. Three-phase active PD
II. CIRCUIT DESCRIPTION AND NOMINAL carrier bands are overlapped. The diagram is redrawn in a
SWITCHING DIAGRAM IN MULTILEVEL INVERTER FOR nominal two-level switching time diagram as shown in Fig.5.
BALANCE DC VOLTAGE SOURCES In this nominal diagram, the commutation instants occur
Assumption: each dc voltage cell is constant and equal to a depending on the relative voltage level termed nominal
unit. Define reference leg voltages between output and modulating signals ξ x , x = a, b, c defined as:
dc-neutral point “0”, consisting of active voltages
ξ x = v xref − L( x ) ; 0 ≤ ξ x ≤ 1 ; (8).
v x12 , x = a, b, c and reference common mode
Or
v0 ref (Fig.4) as: G G G
ξ = v ref − L
v xref = v x12 + v0ref . (1) Nominal switching states sequence: The nominal two-level
Or in the vector form as: switching diagram in Fig.5 shown that switching time
G G G digram in multilevel inverters can be explained using that of
v ref = v12 + v 0ref I two-level inverter. Therefore, in nominal switching diagram,
Active voltages, which exist at the three phase load voltages let’s define nominal switching states as :
can be determined from the amplitude and phase angle of
voltage vector as follows:
v a12 = v ref cosθ
vb12 = v ref cos(θ − 2π 3) ; (2)
K 2 + 2K 3 + 3K 4 (K + 2K 3 + 3K 4 )
Or <1− 2
3 3
Table 1: Algorithm for single-state PWM method
G' G
K 14 > K 2 ; K 14 > K 3 v ref = S1
K 2 + 2K 3 + 3K 4 < 1.5
G' G
K 2 > K 3 ; K 2 > K 14 v ref = S2
G' G
K 3 > K 2 ; K 3 > K14 v ref = S3
G' G
Figure 4: a) Switching time diagram deduced in a) new defined coordinates K 14 > K 2 ; K 14 > K 3 v ref = S4
and b) Nominal switching time diagram.
K 2 + 2K 3 + 3K 4 > 1.5
Table 2: Relation between active errors and corresponding selected vectors
VI. CONCLUSIONS
REFERENCES
[1] N.V.Nho, M.J.Youn,” Comprehensive study on Space
vector PWM and carrier based PWM correlation in multilevel
invertors ” , IEE Proceedings Electric Power Applications,
Vol.153, No.1, pp.149-158, Jan. 2006
[2] N.V.Nho,H.H.Lee,” Optimised Discontinuous PWM for
multilevel inverter with variable load power factor”, PESC
2006
[3] Jose Rodríguez, Luis Morán, Pablo Correa and Cesar
Silva,”A Vector Control Technique for Medium-Voltage
Multilevel Inverters’, IEEE TRANSACTIONS ON Figure 18: Five-level inverter. Experimental results. Diagrams of leg
INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST voltage, line-line voltage and Fourier analysis of line-line voltage for
2002 mref=0.85.
Figure 19 : Five-level inverter. Experimental results. Diagrams of leg
voltage, line-line voltage and Fourier analysis of line-line voltage for
mref=1.05