Introduction to VLSI Systems

CSE 441 / EE 309

Lecture #2

MOSFET Basics 1
1
Atomic Structure

+ 2n2
Electrons/orbit

Less energy

More energy
2
 Intrinsic Semiconductors
(Si, Ge)
Silicon /Germanium
atom
(14/32 electrons)

Intrinsic semiconductor
(no carriers at 00 K)
3
Intrinsic Semiconductor
Room Temp

ni = pi
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 Extrinsic (Doped) Semiconductors

Phosphorus
(pentavalent)

Positive
Ion

N type semiconductor
(n >> p at room temp)
5
 N Type Semiconductors

+ + +
+ +
+ n >> p
+ +
+
+ +
+ +
+
+ +
+
+ +
+
+ +

6
 P Type Semiconductors
Boron
+ + +
Trivalent
+
+
+ +
+
p >> n
+
+ + +
+
+ +
+
+ +

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 Intrinsic and extrinsic
Semiconductors

Intrinsic semiconductor
Intrinsic semiconductor N type semiconductor
(no carriers at 00 K)
(ni = pi at room temp ) (ni >> pi at room temp)

+ + + + +
+ + +
+ + + + + + + +
+ + +
+ + +
+
+
+ + + + + +
+ +
+ + + + + + ++
+ +
N type semiconductor P type semiconductor
(n >> p at room temp) (p >> n at room temp)
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 PN Junction
+ + + + + +
+ +
P- + + + + + +
+ + + + + N+
+ + + +
+
+ + + + + + + +
+ + +
+ + + + + +
p >> n n >> p
+ + + + +
+ +
+ + + + +
+
+ + +
P- + + + N+
+ + +
+ + +
+ + + + + + + + +

Depletion Region

P-N Junction
9
 PN Junction – Reverse Biasing
+ + + + + +
+ +
p >> n + + + + + n >> p
+ + +
P- + + + N+
+ + +
+ + +
+ + + + + + + + +

+ + +
+ +
P- + + + + + N+
+
+ + +
+ + + +
+ + +
+ + +
+ + + + + +
+ + +

Depletion Width
Reverse Bias Increases 10
 nMOSFET
Polysilicon SiO2
Gate
Source
Drain

W
tox
n+ n+
L
p- silicon
p+ silicon

Bulk (substrate)

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 pMOSFET
Gate Polysilicon
Drain Source Well

W
p+ p+ n+
L
n well

p-silicon
p+silicon

Bulk (substrate)
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 Objective: to have current flow
between Source and Drain
If this can
+
Vds Vds +
be achieved !!
Ids Ids

Gate Gate

Source Drain Source Drain

- - - - - - - ---
+-- n+ -- + +++++++ -- n+ --- + +-- n+ --- - - - - - - ---- n+ -+
-
+ -- - - - - - - - - - -+ + + - - - -
+ + + + --- --- --- - + -
+ - -- - -- - -- - + + +
-
+ + --- --- --- - +
+ + + ++ + + + ++ L + + + + + + +
+ + + + + + +++ + + + + ++ + + + +
+ + + + + + ++ + + + ++
+ + + + + + ++ +++ + + ++ + + + ++ + + ++++ + ++ +++ + + ++ + + +
+ + + + + + + + + P- + + + + + + + + + + P- +

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NMOS Transistor Gate Substrate
Capacitor
Gate
Polysilicon SiO2
Gate SiO2
Source
Drain tox
W p-
tox
L
substrate
n+ n+
L
Poly
p- silicon + SiO2
+ + +
p+ silicon + +
+ + + +
+ + + p-type
+ +
+ + + +
Bulk
(substrate)

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 Capacitor Charging

_
+ ++ + ++ + _ __
++ _ _
+
+ +
+
_
_
+ ++ + __ _ _ __
_
+
_ _ __ __ _ __ _ +
_ +
+ ++ +

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 The MOS Capacitor
Very Small Positive Voltage to Poly

Poly ++ + + + + + + + + + + + + +
SiO2
+ + + +
+ +
+ + + + + _
+ + + + + + + +
+ + + + + +
+ + + + +
+ Holes are repelled, +
+ +
+
+ +++ +
+
depleting the top +
++ + + + +

Flat Band
Depletion

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 The MOS Capacitor
Small Positive Voltage to Poly

+ + + + + + + + ++ + + + + + + + + + + + +
+ + + + + + + + + ++ + + + + + + + + + + +
SiO2

n << Ions Vgs

+ + + +
+ +
+ _
+ + + + +
+ +
+ + +
+ + + ++
+ + +
+ + + +
+ + +
+ +
+ ++ +
P- silicon

Weak Inversion
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 Threshold Voltage Vth
More Positive Voltage to Poly Vgs = Vth

+ + + + + + + + ++ + + + + + + + + + + + +
+ + + + + + + + + ++ + + + + + + + + + + +
SiO2
n  Ions

+ + + +
+ + _ Vgs
+ + +
+ + + + +
+ + + + +
+ + + + + ++
+ + + + + +
+ + + + +
+ + +
+
+ + +
P- silicon

Moderate Inversion
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 Strong Inversion
Much More Positive Voltage Vgs >> Vth

+ + + + + + + + ++ + + + + + + + + + + + +
+ + + + + + + + + ++ + + + + + + + + + + +
SiO2
n >> Ions
+ + + +
+ + + +
+ + + _
+ + + + + +
+ + Vgs
+ + + + +
+ + +
+ + + ++
+ + + +
+ + + + +
+ + + + +
+ + +
+ + +
+ + + +
P- silicon

Strong Inversion
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 Threshold Voltage Vth
Less Positive More Positive Much More Positive
++ ++ + + + + + + + + + + +++++++ ++++++ ++++ + + +++++ ++++ ++++++++++++++ ++
++++++++++++++++++++
+++++
+ + + +
SiO2

+ + + + + + + + + + + + + + ++ + ++ + ++
+ + + + + + + + + + + + + ++
+ + + + + ++ +
+ ++ + + + + + + + + +
+ + + + + + + + ++
+ + + + + + + + +++ + + + + + + ++ + + + + + ++ + +
+ + + + + +
+ ++ + + + + ++ +++ + + ++ +++ +

Weak Inversion Moderate inversion Strong inversion

n<< Ions n  Ions n >> Ions
V < Vth V = Vth V >> Vth
Vth Minimum Voltage for
Inversion
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 Cutoff: Ids = 0
Vds +
=0
+ Ids = 0
Vgs
=0
Gate D
Ids
Source Drain +
- - - - - - - - -- G
+ -- n+ -- + ++ + + +++ -- n+ --- + Vds =0
+ - - - - - - - - - - - -+ + + - +
+ + + + --------- - +
+ + + ++ + + + ++ L + + + + + + + Vgs =0 -
+ + + + + + + + S
+ + + + + ++ + + + + ++ + + + + + + + -
+ + + + + + + + + P-

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 First Approximation:
Threshold Voltage
Vgs < Vth Vgs > Vth

Gate Gate
Source Drain Source Drain
+ n+ + + + + n+ + + n+ + + + + n+ +
+ + + ++ + + + + + ++ + +
+
+ + + + + +++++ + + L + + + + + + + +
+ + + + + +++++ + + L + + + + + + +
+ + ++ + + + + + + + ++ + + + + +
++ + + +++ + + + + + ++ + + ++ + + +++ + + + + + ++ + +
+ + + + + + + p- + + + + + + +
+
+ + + + + + + p- + + + + + + +
+

No surface electrons Plenty of surface 22

electrons
 Surface Charge with Vgs
Vgs > Vth Vgs > >Vth

Gate Gate

Source Drain Source Drain

+ n+ n+ + + n+ + ++ + n+ +
+ ++ + + + ++ + ++ +
+ + + + ++ + +
+ + + ++ + +++++ + L + ++ + + + + + + + + ++ ++ ++ ++ + L + + + + + + +
+ + ++ + + + + +
+ +
++ + ++ + + ++++ + + + + +
+ + + p- ++ + + + +++ + + + + ++ + +
+ + + + ++ + p- + + + ++ + +
+
+ ++ ++ +++ + +
+
+ + + + ++ +

Enough electrons Much More electrons

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 Cutoff: Vds = 0 Ids = 0
Vds = 0

Vgs > Vth

Ids = 0
D
Ids
Gate G +
+ Vds =0
Source Drain
+ Vgs >Vth S -
+ n+ + + + + n+
+ + + ++ + + -
+ + + + + +++ ++ + + L + + + + + + + +
+ +
+ + + + + + + + +
+ + + + + ++ + + + + p- + + + +
+ + + + + + +
+ + + + + + +

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