Multiple Choice Questions and Answers: -

1. A microprocessor is a _______ chip integrating all the functions of a CPU of a

computer.

A. multiple
B. single
C. double
D. triple

Answer: B

2. Microprocessor is a/an _______ circuit that functions as the CPU of the compute

A. electronic
B. mechanic
C. integrating
D. processing

Answer: A

3. Microprocessor is the ______ of the computer and it perform all the computational
tasks

A. main
B. heart
C. important
D. simple

Answer: B

4. The purpose of the microprocessor is to control ______

A. memory
B. switches
C. processing
D. tasks

Answer: A

5. The first digital electronic computer was built in the year________

A. 1950
B. 1960
C. 1940
D. 1930

Answer: C

6. In 1960's texas institute invented ______

A. integrated circuits
B. microprocessor
C. vacuum tubes
D. transistors

Answer: A

7. The intel 8086 microprocessor is a _______ processor

A. 8 bit
B. 16 bit
C. 32 bit
D. 4 bit

Answer: B

8. The microprocessor can read/write 16 bit data from or to ________

A. memory
B. I /O device
C. processor
D. register

Answer: A

9. In 8086 microprocessor , the address bus is ________ bit wide

A.1
2 bit
B. 10 bit
C. 16 bit
D. 20 bit

Answer: D

10. The work of EU is ________

A. encoding
B. decoding
C. processing
D. calculations

Answer: B

11. The 16 bit flag of 8086 microprocessor is responsible to indicate ___________

A. the condition of result of ALU operation

B. the condition of memory
C. the result of addition
D. the result of subtraction
Answer: A

12. The CF is known as ________

A. carry flag
B. condition flag
C. common flag
D. single flag

Answer: A

13. The SF is called as ________

A. service flag
B. sign flag
C. single flag
D. condition flag

Answer: B

14. The OF is called as _______

A. overflow flag
B. overdue flag
C. one flag
D. over flag

Answer: A

15. The IF is called as _________

A. initial flag
B. indicate flag
C. interrupt flag
D. inter flag

Answer: C

16. The register AX is formed by grouping ________

A. AH & AL
B. BH & BL
C. CH & CL
D. DH & DL

Answer: A

17. The SP is indicated by ________

A. single pointer
B. stack pointer
C. source pointer
D. destination pointer

Answer: B

18. The BP is indicated by _______

A. base pointer
B. binary pointer
C. bit pointer
D. digital pointer

Answer: A

19. The SS is called as ________

A. single stack
B. stack segment
C. sequence stack
D. random stack

Answer: B

20. The index register are used to hold _______

A. memory register
B. offset address
C. segment memory
D. offset memory

Answer: A

21. The BIU contains FIFO register of size __________ bytes

A. 8
B. 6
C. 4
D. 12

Answer: B

22. The BIU prefetches the instruction from memory and store them in ________

A. queue
B. register
C. memory
D. stack

Answer: A

23. The 1 MB byte of memory can be divided into ______ segment

A. 1 Kbyte
B. 64 Kbyte
C. 33 Kbyte
D. 34 Kbyte

Answer: B

24. The DS is called as _______

A. data segment
B. digital segment
C. divide segment
D. decode segment

Answer: A

25. The CS register stores instruction _____________ in code segment

A. stream
B. path
C. codes
D. stream line

Answer: C

26. The IP is ________ bits in length

A. 8 bits
B. 4 bits
C. 16 bits
D. 32 bits

Answer: C
27. The push source copies a word from source to ______

A. stack
B. memory
C. register
D. destination

Answer: A

28. LDs copies to consecutive words from memory to register and ___________

A. ES
B. DS
C. SS
D. CS

Answer: B

29. INC destination increments the content of destination by _______

A. 1
B. 2
C. 30
D. 41

Answer: A

30. IMUL source is a signed _________

A. multiplication
B. addition
C. subtraction
D. division
Answer: A

31. _________destination inverts each bit of destination

A. NOT
B. NOR
C. AND
D. OR

Answer: A

32. The JS is called as ______

A. jump the signed bit

B. jump single bit
C. jump simple bit
D. jump signal it

Answer: A

33. Instruction providing both segment base and offset address are called _____

A. below type .
B. far type
C. low type
D. high type

Answer: B

34. The conditional branch instruction specify ___________ for branching

A. conditions
B. instruction
C. address
D. memory

Answer: A

35. The microprocessor determines whether the specified condition exists or not by
testing the
______

A. carry flag
B. conditional flag
C. common flag
D. sign flag

Answer: B

36. The LES copies to words from memory to register and __________

A. DS
B. CS
C. ES
D. DS

Answer: C

37. The _________ translates a byte from one code to another code

A. XLAT
B. XCHNG
C. POP
D. PUSH

Answer: A
38. The _______ contains an offset instead of actual address

A. SP
B. IP
C. ES
D. SS

Answer: B

39. The 8086 fetches instruction one after another from __________ of memory

A. code segment
B. IP
C. ES
D. SS

Answer: A

40. The BIU contains FIFO register of size 6 bytes called _____.

A. queue
B. stack
C. segment
D. register

Answer: A

41. The ___________ is required to synchronize the internal operands in the

processor CLK
Signal

A. UR Signal
B. Vcc
C. AIE
D. Ground

Answer: A

42. The pin of minimum mode AD0-AD15 has ____________ address

A. 16 bit
B. 20 bit
C. 32 bit
D. 4 bit

Answer: B

43. The pin of minimum mode AD0- AD15 has _________ data bus

A. 4 bit
B. 20 bit
C. 16 bit
D. 32 bit

Answer: C

44. The address bits are sent out on lines through __________

A. A16-19
B. A0-17
C. D0-D17
D. C0-C17

Answer: A

45. ________ is used to write into memory

A. RD
B. WR
C. RD / WR
D. CLK

Answer: B

46. The functions of Pins from 24 to 31 depend on the mode in which _______ is
operating

A. 8085
B. 8086
C. 80835
D. 80845

Answer: B

47. The RD, WR, M/IO is the heart of control for a __________ mode

A. minimum
B. maximum
C. compatibility mode
D. control mode

Answer: A

48. In a minimum mode there is a ___________ on the system bus

A. single
B. double
C. multiple
D. triple

Answer: A
49. If MN/MX is low the 8086 operates in __________ mode

A. Minimum
B. Maximum
C. both (A) and (B)
D. medium

Answer: B

50. In max mode, control bus signal So,S1 and S2 are sent out in ____________
form

A. decoded
B. encoded
C. shared
D. unshared

Answer: B

51. The ___ bus controller device decodes the signals to produce the control bus
signal

A. internal
B. data
C. external
D. address

Answer: C

52. A _____ Instruction at the end of interrupt service program takes the execution
back to the
interrupted program

A. forward
B. return
C. data
D. line

Answer: B

53. The main concerns of the ___________ are to define a flexible set of commands

A. memory interface
B. peripheral interface
C. both (A) and (B)
D. control interface

Answer: A

54. Primary function of memory interfacing is that the _________ should be able to
read from
and write into register

A. multiprocessor
B. microprocessor
C. dual Processor
D. coprocessor

Answer: B

55. To perform any operations, the Mp should identify the __________

A. register
B. memory
C. interface
D. system

Answer: A
56. The Microprocessor places __________ address on the address bus

A. 4 bit
B. 8 bit
C. 16 bit
D. 32 bit

Answer: C

57. The Microprocessor places 16 bit address on the add lines from that address by
_____
register should be selected

A. address
B. one
C. two
D. three

Answer: B

58. The ________of the memory chip will identify and select the register for the
EPROM

A. internal decoder
B. external decoder
C. address decoder
D. data decoder

Answer: A

59. Microprocessor provides signal like ____ to indicate the read operatio

A. LOW
B. MCMW
C. MCMR
D. MCMWR

Answer: C

60. To interface memory with the microprocessor, connect register the lines of the
address bus
must be added to address lines of the _______ chip.

A. single
B. memory
C. multiple
D. triple

Answer: B

61. The remaining address line of ______ bus is decoded to generate chip select
signal

A. data
B. address
C. control bus
D. both (a) and (b)
Answer: B

62. _______ signal is generated by combining RD and WR signals with IO/M

A. control
B. memory
C. register
D. system

Answer: A
63. Memory is an integral part of a _______ system

A. supercomputer
B. microcomputer
C. mini computer
D. mainframe computer

Answer: B

64. _____ has certain signal requirements write into and read from its registers

A. memory
B. register
C. both (a) and (b)
D. control

Answer: A

65. An _________ is used to fetch one address

A. internal decoder
B. external decoder
C. encoder
D. register

Answer: A

66. The primary function of the _____________ is to accept data from I/P devices

A. multiprocessor
B. microprocessor
C. peripherals
D. interfaces
Answer: B

67. ___________ signal prevent the microprocessor from reading the same data
more than one

A. pipelining
B. handshaking
C. controlling
D. signaling

Answer: B

68. Bits in IRR interrupt are ______

A. reset
B. set
C. stop
D. start

Answer: B

69. __________ generate interrupt signal to microprocessor and receive

acknowledge

A. priority resolver
B. control logic
C. interrupt request register
D. interrupt register

Answer: B

70. The _______ pin is used to select direct command word

A. A0
B. D7-D6
C. A12
D. AD7-AD6

Answer: A

71. The _______ is used to connect more microprocessor

A. peripheral device
B. cascade
C. I/O devices
D. control unit

Answer: B

72. CS connect the output of ______

A. encoder
B. decoder
C. slave program
D. buffer

Answer: B

73. In which year, 8086 was introduced?

A. 1978
B. 1979
C. 1977
D. 1981

Answer: A
74. Expansion for HMOS technology_______

A. high level mode oxygen semiconductor

B. high level metal oxygen semiconductor
C. high performance medium oxide semiconductor
D. high performance metal oxide semiconductor

Answer: D

75. 8086 and 8088 contains _______ transistors

A. 29000
B. 24000
C. 34000
D. 54000

Answer: A

76. ALE stands for ___________

A. address latch enable

B. address level enable
C. address leak enable
D. address leak extension

Answer: A

77. What is DEN?

A. direct enable
B. data entered
C. data enable
D. data encoding
Answer: C

78. In 8086, Example for Non maskable interrupts are ________.

A. TRAP
B. RST6.5
C. INTR
D. RST6.6

Answer: A

79. In 8086 the overflow flag is set when _____________.

A. the sum is more than 16 bits.

B. signed numbers go out of their range after an arithmetic operation.
C. carry and sign flags are set.
D. subtraction

Answer: B

80. In 8086 microprocessor the following has the highest priority among all type
interrupts?

A. NMI
B. DIV 0
C. TYPE 255
D. OVER FLOW

Answer: A

81. In 8086 microprocessor one of the following statements is not true?

A. coprocessor is interfaced in max mode.

B. coprocessor is interfaced in min mode.
C. I /O can be interfaced in max / min mode.
D. supports pipelining

Answer: B

82. Address line for TRAP is?

A. 0023H
B. 0024H
C. 0033H
D. 0099H

Answer: B

83. Access time is faster for _________.

A. ROM
B. SRAM
C. DRAM
D. ERAM

Answer: B

84. The First Microprocessor was__________.

A. Intel 4004
B. 8080
C. 8085
D. 4008

Answer: A

85. Status register is also called as ___________.

A. accumulator
B. stack
C. counter
D. flags

Answer: D

86.Which of the following is not a basic element within the microprocessor?

A.Microcontroller
B. Arithmetic logic unit (ALU)
C. Register array
D. Control unit

Answer: A

87.Which method bypasses the CPU for certain types of data transfer?

A.Software interrupts
B. Interrupt-driven I/O
C. Polled I/O
D. Direct memory access (DMA)

Answer: D

88.Which bus is bidirectional?

A.
Address bus
B. Control bus
C. Data bus
D. None of the above

Answer: C
89.The first microprocessor had a(n)________.

A.1 – bit data bus

B. 2 – bit data bus
C. 4 – bit data bus
D. 8 – bit data bus

Answer: C

90.Which microprocessor has multiplexed data and address lines?

A.8086
B. 80286
C. 80386
D. Pentium

Answer: A

91.Which is not an operand?

A.Variable
B. Register
C. Memory location
D. Assembler

Answer: D

92.Which is not part of the execution unit (EU)?

A.Arithmetic logic unit (ALU)

B. Clock
C. General registers
D. Flags
Answer: B

93.A 20-bit address bus can locate ________.

A.1,048,576 locations
B. 2,097,152 locations
C. 4,194,304 locations
D. 8,388,608 locations

Answer: A

94.Which of the following is not an arithmetic instruction?

A. INC (increment)
B. CMP (compare)
C. DEC (decrement)
D. ROL (rotate left)

Answer: D

95.During a read operation the CPU fetches ________.

A.a program instruction

B. another address
C. data itself
D. all of the above

Answer: D

96.Which of the following is not an 8086/8088 general-purpose register?

A.Code segment (CS)

B. Data segment (DS)
C. Stack segment (SS)
D. Address segment (AS)

Answer: D

97.A 20-bit address bus allows access to a memory of capacity

A.1 MB
B. 2 MB
C. 4 MB
D. 8 MB

Answer: A

98.Which microprocessor accepts the program written for 8086 without any
changes?

A.8085
B. 8086
C. 8087
D. 8088

Answer: D

99.Which group of instructions do not affect the flags?

A.Arithmetic operations
B. Logic operations
C. Data transfer operations
D. Branch operations

Answer: C

100.The result of MOV AL, 65 is to store

A.store 0100 0010 in AL
B. store 42H in AL
C. store 40H in AL
D. store 0100 0001 in AL

Answer: D

101. When the microcontroller executes some arithmetic operations, then the
flag bits of which register are affected?

A. PSW

B. SP

C. DPTR

D. PC

102. How many bytes of bit addressable memory are present in 8051 based
microcontrollers?

A. 8 bytes

B. 32 bytes

C. 16 bytes

D. 128 bytes
103. Find the number of times the following loop will be executed

MOV R6,#200

BACK:MOV R5,#100

HERE:DJNZ R5, HERE

DJNZ R6,BACK

END

A. 100
B. 200

C. 20000

D. 2000

104. To initialize any port as an output port what value is to be given to

it?

A. 0Xff

B. 0x00

C. 0x01

D. A port is by default an output port

105. Which out of the four ports of 8051 needs a pull-up resistor for
using it is as an input or an output port?

A. PORT 0

B. PORT 1

C. PORT 2

D. PORT 3

106. Which addressing mode is used in pushing or popping any

element on or from the stack?

A. Immediate

B. Direct

C. Indirect

D. Register

107. Which operator is the most important while assigning any

instruction as register indirect instruction?

A. $

B. #

C. @

D. &
 108. Which of the following comes under the indexed addressing
mode?

A. MOVX A, @DPTR

B. MOVC @A+DPTR,A

C. MOV A,R0

D. MOV @R0,A

109. When we add two numbers the destination address must always
be.

A. some immediate data

B. any Register

C. Accumulator

D. Memory

110. DAA command adds 6 to the nibble if:

A. CY and AC are necessarily 1

B. either CY or AC is 1

C. no relation with CY or AC

D. CY is 1

111. If SUBB A,R6 is executed, then actually what operation is being

applied?

A. R6+A

B. R6-A

C. A-R6

D. R6+A

112. ANL instruction is used _______

A. to AND the contents of the two registers

B. to mask the status of the bits

C. all of the mentioned

D. none of the mentioned

113. XRL, ORL, ANL commands have _______

A. Accumulator as the destination address and any register, memory or

any immediate data as the source address

B. Accumulator as the destination address and any immediate data as

the source address

C. any register as the destination address and accumulator, memory or

any immediate data as the source address

D. any register as the destination address and any immediate data as

the source address

114. Auto reload mode is allowed in which mode of the timer?

A. Mode 0

B. Mode 1

C. Mode 2

D. Mode 3

115. If Timer 0 is to be used as a counter, then at what particular pin

clock pulse need to be applied?

A. P3.3

B. P3.4

C. P3.5

D. P3.6

116. Which of the following best states the reason that why baud rate is
mentioned in serial communication?

A. to know about the no of bits being transmitted per second

B. to make the two devices compatible with each other, so that the
transmission becomes easy and error free
C. to use Timer 1

D. for wasting memory

117. What should be done if we want to double the baud rate?

A. change a bit of the TMOD register

B. change a bit of the PCON register

C. change a bit of the SCON register

D. change a bit of the SBUF register

118. Which register is used to make the pulse a level or an edge

triggered pulse?

A. TCON

B. IE

C. IP

D. SCON

119. What is the correct order of priority that is set after a controller
gets reset?

A. TxD/RxD > T1 > T0 >EX1 > EX0

B. TxD/RxD < T1 < T0<EX1 < EX0

C. EX0 > T0 > EX1 >T1> TxD/RxD

D. EX0 < T0 < EX1 < T1 < TxD/RxD

120. After reset, SP register is initialized to address________.

A. 8H

B. 9H

C. 7H

D. 6H
121. The 8051 microcontroller is of ___pin package as a ______
processor.
A. 30, 1byte

B. 20, 1 byte

C. 40, 8 bit

D. 40, 8 byte
122. What is the address range of SFR Register bank?

A. 00H-77H

B. 40H-80H

C. 80H-7FH

D. 80H-FFH
123. Match the following:

1) TCON i) contains status information

2) SBUF ii) timer / counter control register.

3) TMOD iii) idle bit, power down bit

4) PSW iv) serial data buffer for Tx and Rx.

5) PCON v) timer/ counter modes of operation.

A. 1-ii, 2-iv, 3-v, 4-i, 5-iii.

B. 1-i, 2-v, 3-iv, 4-iii, 5-ii.

C. 1-v, 2-iii, 3-ii, 4-iv, 5-i.

D. 1-iii, 2-ii, 3-i, 4-v, 5-iv

124. Serial port interrupt is generated, if ____ bits are set

A. IE

B. RI, IE

C. IP, TI

D. RI, TI

125. The instruction, MOV AX, 1234H is an example of

A. Register addressing mode

B. Direct addressing mode

C. Immediate addressing mode

D. Based indexed addressing mode

126. The instruction that is used to transfer the data from source
operand to destination operand is

A. data copy/transfer instruction

B. branch instruction

C. arithmetic/logical instruction

D. string instruction

127. Which of the following instruction is not valid?

A. MOV AX, BX

B. MOV DS, 5000H

C. MOV AX, 5000H

D. PUSH AX

128. In 8086 Microprocessor in POP instruction, after each execution of

the instruction, the stack pointer is

A. incremented by 1

B. decremented by 1

C. incremented by 2

D. decremented by 2

129. The instruction that is used for finding out the codes in case of
code conversion problems is

A. XCHG

B. XLAT

C. XOR
D. JCXZ

130. The instruction that loads the AH register with the lower byte of the
flag register is

A. SAHF

B. AH

C. LAHF

D. PUSHF

131. The flag that acts as Borrow flag in the instruction SBB is

A. Direction flag

B. Carry flag

C. Parity flag

D. Trap flag

132. During comparison operation, the result of comparing or

subtraction is stored in ________.

A. Memory

B. Registers

C. Stack

D. No where

133. The instruction in which adjustment is made before performing

the operation is

A. AAA

B. AAS

C. AAM

D. AAD

134. The directive used to inform the assembler, the names of the
logical segments to be assumed for different segments used in the
program is
A. ASSUME

B. SEGMENT

C. SHORT

D. DB

135. The recurrence/repeating of the numerical values or constants in

a program code is reduced by

A. ASSUME

B. LOCAL

C. LABEL

D. EQU
136. Base Pointer (BP) contains offset address of ________ segment.

A. Data segment

B. Code segment

C. Stack segment

D. Extra segment
137. The size of each segment in 8086 microprocessor is

A. 32 Kbytes

B. 64 byte

C. 64 Kbytes

D. 16 Kbytes
138. If segment address = 1005 H, offset address = 5555 H, then the
physical address is_____.

A. 655A H

B. 155A5 H

C. 4550 H

D. 56555
 139. The BIU prefetches the instruction from memory and store them
in _____.

A. Queue

B. Register

C. Memory

D. Stack
140. If MN/MX in 8086 microprocessor is low then it operates in

A. 8-bit mode

B. Minimum mode

C. Maximum mode

D. 32-bit mode

141. In 8086 microprocessor, _____ signal is sent out by the CPU to

prevent Bus Masters getting the System Bus.

A. HOLD

B. LOCK(bar)

C. HLDA

D. RESET

142. BHE of 8086 microprocessor signal is used to interface the

A. Even bank memory

B. Odd bank memory

C. I/O

D. DMA

143. In 8086 microprocessor, TEST pin is examined by this instruction

A. MUL

B. LOCK

C. LAHF
D. WAIT

144. In 8086 microprocessor, The ACALL instruction uses 11 bits of

address to address within _____ byte range.

A. 64 kb

B. 32 kb

C. 16 kb

D. 2 kb

145. In keyboard interfacing, if we need to operate a key of a

keyboard in an interrupt mode, then it will generate what kind of
interrupt?

A. ES

B. EX0/EX1

C. T0/T1

D. RESET

146. The unit that executes all the numeric processor instructions in
8087 is

A. Control unit

B. ALU

C. Numeric extension unit

D. None of the mentioned

147. In 8087, When the numeric extension unit (NEU) begins its
execution, then the signal that is active is

A. BUSY (active high)

B. BUSY (active low)

C. READY (active low)

D. RESET (active high)

 148. In 8087, The instruction that multiplies the content of the stack
top by 2n is

A. FMUL

B. FPREM

C. FSCAL

D. FCSH
149. Why 8087 is referred to as Coprocessor?

i) Because 8087 is used in parallel with main processor in a system, rather

than serving as a main processor itself.

ii) Because 8087 is used in serial with main processor in a system, rather than
serving as a main processor itself.

iii) Because main Microprocessor handles the general program execution and
the 8087 haQndles specialized math computations.

A. i & iii

B. ii & iii

C. iii only.

D. i only
150. One of the following signals belongs to the 8087 coprocessor is

A. HOLD

B. BUSY

C. TEST

D. NMI

151. Which operations are performed by the bit manipulating

instructions of boolean processor?
a. Complement bit
b. Set bit
c. Clear bit
d. All of the above
ANSWER: (d) All of the above
152. Which data memory control and handle the operation of several
peripherals by assigning them in the category of special function
registers?
a. Internal on-chip RAM
b. External off-chip RAM
c. Both a & b
d. None of the above
ANSWER: (a) Internal on-chip RAM
153. Why is the speed accessibility of external data memory slower
than internal on-chip RAM?
a. Due to multiplexing of lower order byte of address-data bus
b. Due to multiplexing of higher order byte of address-data bus
c. Due to demultiplexing of lower order byte of address-data bus
d. Due to demultiplexing of higher order byte of address-data bus
ANSWER: (a) Due to multiplexing of lower order byte of address-data bus
154. Which control signal/s is/are generated by timing and control unit
of 8051 microcontroller in order to access the off-chip devices apart
from the internal timings?
a. ALE
b. PSEN
c. RD & WR
d. All of the above
ANSWER: (d) All of the above
155. Which register usually store the output generated by ALU in
several arithmetic and logical operations?
a. Accumulator
b. Special Function Register
c. Timer Register
d. Stack Pointer
ANSWER: (a) Accumulator
 156. Why is CHMOS technology preferred over HMOS technology for
designing the devices of MCS-51 family?
a. Due to higher noise immunity
b. Due to lower power consumption
c. Due to higher speed
d. All of the above
ANSWER: (d) All of the above
157. Which condition approve to prefer the EPROM/ROM versions for
mass production in order to prevent the external memory
connections?
a. size of code < size of on-chip program memory
b. size of code > size of on-chip program memory
c. size of code = size of on-chip program memory
d. None of the above
ANSWER: (a) size of code < size of on-chip program memory
158. Which among the below mentioned devices of MCS-51 family
does not possess two 16 -bit timers/counters?
a. 8031
b. 8052
c. 8751
d. All of the above
ANSWER: (b) 8052
159. Which characteristic/s of accumulator is /are of greater
significance in terms of its functionality?
a. Ability to store one of the operands before the execution of an instruction
b. Ability to store the result after the execution of an instruction
c. Both a & b
d. None of the above
ANSWER: (c) Both a & b
160. Which general purpose register holds eight bit divisor and store
the remainder especially after the execution of division operation?
a. A-Register
b. B-Register
c. Registers R0 through R7
d. All of the above
ANSWER: (b) B-Register
161. How many registers can be utilized to write the programs by an
effective selection of register bank in program status word (PSW)?
a. 8
b. 16
c. 32
d. 64
ANSWER: (c) 32
162. Which operations are performed by stack pointer during its
incremental phase?
a. Push
b. Pop
c. Return
d. All of the above
ANSWER: (a) Push
163. Which is the only register without internal on-chip RAM address
in MCS-51?
a. Stack Pointer
b. Program Counter
c. Data Pointer
d. Timer Register
ANSWER: (b) Program Counter
164. What kind of instructions usually affect the program counter?
a. Call & Jump
b. Call & Return
c. Push & Pop
d. Return & Jump
ANSWER: (a) Call & Jump
165. What is the default value of stack once after the system
undergoes the reset condition?
a. 07H
b. 08H
c. 09H
d. 00H
ANSWER:(a) 07H
166. Which bit/s play/s a significant role in the selection of a bank
register of Program Status Word (PSW)?
a. RS1
b. RS0
c. Both a & b
d. None of the above
ANSWER: (c) Both a & b
167. Which flags represent the least significant bit (LSB) and most
significant bit (MSB) of Program Status Word (PSW) respectively?
a. Parity Flag & Carry Flag
b. Parity Flag & Auxiliary Carry Flag
c. Carry Flag & Overflow Flag
d. Carry Flag & Auxiliary Carry Flag
ANSWER: (a) Parity Flag & Carry Flag
168. Which register bank is supposed to get selected if the values of
register bank select bits RS1 & Rs0 are detected to be ‘1’ & ‘0’
respectively?
a. Bank 0
b. Bank 1
c. Bank 2
d. Bank 3
ANSWER: (c) Bank 2
169. It is possible to set the auxiliary carry flag while performing
addition or subtraction operations only when the carry exceeds
_______
a. 1st bit
b. 2nd bit
c. 3rd bit
d. 4th bit
ANSWER: (c) 3rd bit
 170. Which locations of 128 bytes on-chip additional RAM are
generally reserved for special functions?
a. 80H to 0FFH
b. 70H to 0FFH
c. 90H to 0FFH
d. 60H to 0FFH
ANSWER: (a) 80H to 0FFH
171. Which commands are used for addressing the off-chip data and
associated codes respectively by data pointer?
a. MOVX & MOVC
b. MOVY & MOVB
c. MOVZ & MOVA
d. MOVC & MOVY
ANSWER: (a) MOVX & MOVC
172. Which instruction find its utility in loading the data pointer with 16
bits immediate data?
a. MOV
b. INC
c. DEC
d. ADDC
ANSWER: (a) MOV
173. What is the maximum capability of addressing the off-chip data
memory & off-chip program memory in a data pointer?
a. 8K
b. 16K
c. 32K
d. 64K
ANSWER: (d) 64K
174. Which among the below stated registers does not belong to the
category of special function registers?
a. TCON & TMOD
b. TH0 & TL0
c. P0 & P1
d. SP & PC
ANSWER: (d) SP & PC
175. Which timer is attributed to the register pair of RCAP2H &
RCAP2L for capture mode operation?
a. Timer 0
b. Timer 1
c. Timer 2
d. Timer 3
ANSWER:(c) Timer 2
176. Which registers are supposed to get copied into RCAP2H &
RCAP2L respectively due to the transition at 8052 T2EX pin in the
capture mode operation?
a. TH0 & TH1
b. TH1 & TH1
c. TH2 & TH2
d. All of the above
ANSWER: (c) TH2 & TH2
177. Which mode of timer 2 allow to hold the reload values with an
assistance of RCAP2H & RCAP2L register pair?
a. 8 bit auto-reload mode
b. 16 bit auto reload mode
c. 8 bit capture mode
d. 16 bit capture mode
ANSWER: (b) 16 bit auto reload mode
178. Where should the pin 19 (XTAL1), acting as an input of inverting
amplifier as well as part of an oscillator circuit, be connected under
the application of external clock?
a. to XTAL2
b. to Vcc
c. to GND
d. to ALE
ANSWER: (c) to GND
179. Which port does not represent quasi-bidirectional nature of I/O
ports in accordance to the pin configuration of 8051 microcontroller?
a. Port 0 (Pins 32-39)
b. Port 1 (Pins 1-8)
c. Port 2 (Pins 21-28)
d. Port 3 (Pins 10-17)
ANSWER: (a) Port 0 (Pins 32-39)
180. What is the required baud rate for an efficient operation of serial
port devices in 8051 microcontroller?
a. 1200
b. 2400
c. 4800
d. 9600
ANSWER: (d) 9600
181. Which among the below mentioned functions does not belong to
the category of alternate functions usually performed by Port 3 (Pins
10-17)?
a. External Interrupts
b. Internal Interrupts
c. Serial Ports
d. Read / Write Control signals
ANSWER: (b) Internal Interrupts
182. What is the constant activation rate of ALE that is optimized
periodically in terms of an oscillator frequency?
a. 1 / 8
b. 1 / 6
c. 1 / 4
d. 1 / 2
ANSWER:(b) 1 / 6
183. Which output control signal is activated after every six oscillator
periods while fetching the external program memory and almost
remains high during internal program execution?
a. ALE
b. PSEN
c. EA
d. All of the above
ANSWER: (b) PSEN
184. Which memory allow the execution of instructions till the address
limit of 0FFFH especially when the External Access (EA) pin is held
high?
a. Internal Program Memory
b. External Program Memory
c. Both a & b
d. None of the above
ANSWER: (a) Internal Program Memory
185. Which value of disc capacitors is preferred or recommended
especially when the quartz crystal is connected externally in an
oscillator circuit of 8051?
a. 10 pF
b. 20 pF
c. 30 pF
d. 40 pF
ANSWER: (c) 30 pF
186. Why are the resonators not preferred for an oscillator circuit of
8051?
a. Because they do not avail for 12 MHz higher order frequencies
b. Because they are unstable as compared to quartz crystals
c. Because cost reduction due to its utility is almost negligible in comparison to total
cost of microcontroller board
d. All of the above
ANSWER: (d) All of the above
187. Which version of MCS-51 requires the necessary connection of
external clock source to XTAL2 in addition to the XTAL1 connectivity
to ground level?
a. HMOS
b. CHMOS
c. CMOS
d. All of the abov
ANSWER: (a) HMOS
 188. Which signal from CPU has an ability to respond the clocking
value of D- flipflop (bit latch) from the internal bus?
a. Write-to-Read Signal
b. Write-to-Latch Signal
c. Read-to-Write Signal
d. Read-to-Latch Signal
ANSWER: (b) Write-to-Latch Signal
189. Which among the below mentioned statements are precisely
related to quasi-bidirectional port?
a. Fixed high pull-up resistors are internally connected
b. Configuration in the form of input pulls the port at higher position whereas they get
pulled lower when configured as a source current
c. It is possible to drive the pin as output at any duration when FET gets turned OFF
for an input function
d. Upper pull-up FET is always OFF with the provision of ‘open-drain’ output pin for
normal operation of port

a. A, B, C, D
b. A, B & C
c. A & B
d. C & D
ANSWER: (b) A, B & C
190. What happens when the pins of port 0 & port 2 are switched to
internal ADDR and ADDR / DATA bus respectively while accessing an
external memory?
a. Ports cannot be used as general-purpose Inputs/Outputs
b. Ports start sinking more current than sourcing
c. Ports cannot be further used as high impedance input
d. All of the above
ANSWER: (a) Ports cannot be used as general-purpose Inputs/Outputs
191. The upper 128 bytes of an internal data memory from 80H through
FFH usually represent _______.
a. general-purpose registers
b. special function registers
c. stack pointers
d. program counters
ANSWER: (b) special function registers
192. What is the bit addressing range of addressable individual bits
over the on-chip RAM?
a. 00H to FFH
b. 01H to 7FH
c. 00H to 7FH
d. 80H to FFH
ANSWER: (c) 00H to 7FH
193. What is the divisional range of program memory for internal and
external memory portions respectively when enable access pin is
held high (unity)?
a. 0000H – 0FFFH & 1000H – FFFFH
b. 0000H – 1000H & 0FFFH – FFFFH
c. 0001H – 0FFFH & 01FFH – FFFFH
d. None of the above
ANSWER: (a) 0000H – 0FFFH & 1000H – FFFFH
194. Consider the following statements. Which of them is/are correct in
case of program execution related to program memory?
a. External Program memory execution takes place from 1000H through 0FFFFH
only when the status of EA pin is high (1)
b. External Program memory execution takes place from 0000H through 0FFFH only
when the status of EA pin is low (0)
c. Internal Program execution occurs from 0000H through 0FFFH only when the
status of EA pin is held low (0)
d. Internal program memory execution occurs from 0000H through 0FFFH only when
EA pin is held high (1)

a. A & C
b. B & D
c. A & B
d. Only A
ANSWER: (b) B & D
 195. How does the processor respond to an occurrence of the
interrupt?
a. By Interrupt Service Subroutine
b. By Interrupt Status Subroutine
c. By Interrupt Structure Subroutine
d. By Interrupt System Subroutine
ANSWER: (a) By Interrupt Service Subroutine
196. Which address/location in the program memory is supposed to
get occupied when CPU jump and execute instantaneously during
the occurrence of an interrupt?
a. Scalar
b. Vector
c. Register
d. All of the above
ANSWER: (b) Vector
197. Which location specify the storage/loading of vector address
during the interrupt generation?
a. Stack Pointer
b. Program Counter
c. Data Pointer
d. All of the above
ANSWER: (b) Program Counter
198. Match the following :
a. ISS —————————– 1. Monitors the status of interrupt pin
b. IER —————————– 2. Allows the termination of ISS
c. RETI ————————— 3. MCS-51 Interrupts Initialization
d. INTO ————————– 4. Occurrence of high to low transition level

a. A-1, B-2, C-3, D-4

b. A-3, B-2, C-4, D-1
c. A-1, B-3, C-2, D-4
d. A-4, B-3, C-2, D-1
ANSWER:(c) A-1, B-3, C-2, D-4
 199. What kind of triggering configuration of external interrupt intimate
the signal to stay low until the generation of subsequent interrupt?
a. Edge-Triggering
b. Level Triggering
c. Both a & b
d. None of the above
ANSWER: (b) Level Triggering
200. Which among the below mentioned reasons is/are responsible for
the generation of Serial Port Interrupt?
a. Overflow of timer/counter 1
b. High to low transition on pin INT1
c. High to low transition on pin INT0
d. Setting of either TI or RI flag

a. A & B
b. Only B
c. C & D
d. Only D
ANSWER: (d) Only D
201. What is the counting rate of a machine cycle in correlation to the
oscillator frequency for timers?
a. 1 / 10
b. 1 / 12
c. 1 / 15
d. 1 / 20
ANSWER: (b) 1 / 12
202. Which special function register play a vital role in the
timer/counter mode selection process by allocating the bits in it?
a. TMOD
b. TCON
c. SCON
d. PCON
ANSWER:(a) TMOD
 203. How many machine cycle/s is/are executed by the counters in
8051 in order to detect ‘1’ to ‘0’ transition at the external pin?
a. One
b. Two
c. Four
d. Eight
ANSWER: (b) Two
204. Which bit must be set in TCON register in order to start the ‘Timer
0’ while operating in ‘Mode 0’?
a. TR0
b. TF0
c. IT0
d. IE0
ANSWER: (a) TR0
205. Which among the following control/s the timer1 especially when it
is configured as a timer in mode’0′, where gate and TR1 bits are
attributed to be ‘1” in TMOD register?
a. TR1
b. External input at (INT1)
c. TF1
d. All of the above
ANSWER: (b) External input at (INT1)
206. Which timer mode exhibit the necessity to generate the interrupt
by setting EA bit in IE enhancing the program counter to jump to
another vector location?
a. Mode 0
b. Mode 1
c. Mode 2
d. Mode 3
ANSWER: (b) Mode 1
207. Consider the below generated program segment for initializing
Timer 1 in Mode 1 operation :
MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SET C ET1
SETC TR0
SJMP $

208. Which among the below mentioned program segments represent

the correct code?
a. MOV SP, # 54 H
MOV TCON ,# 0010 0000 C
SETC ET1
SETC TR0
SJMP $
b. MOV SP, # 54H
MOV TMOD ,# 0010 0000 C
SETC ET0
SETC TR0
SJMP $
c. MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET1
SETC TR1
SETC EA
SJMP $
d. MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET0
SETC TR1
SETC EA
SJMP $
ANSWER: (c)
MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C
SETC ET1
SETC TR1
SETC EA
SJMP $
209. What is the maximum delay generated by the 12 MHz clock
frequency in accordance to an auto-reload mode (Mode 2) operation
of the timer?
a. 125 μs
b. 250 μs
c. 256 μs
d. 1200 μs
ANSWER: (c) 256 μs
210. Which among the below mentioned sequence of program
instructions represent the correct chronological order for the
generation of 2kHz square wave frequency?
1. MOV TMOD, 0000 0010 B

2. MOV TL0, # 06H

3. MOV TH0, # 06H

4. SETB TR0

5. CPL p1.0

6. ORG 0000H

a. 6, 5, 2, 4, 1, 3
b. 6, 1, 3, 2, 4, 5
c. 6, 5, 4, 3, 2, 1
d. 6, 2, 4, 5, 1, 3
ANSWER: (b) 6, 1, 3, 2, 4, 5
211. Why is it not necessary to specify the baud rate to be equal to the
number of bits per second?
a. Because each bit is preceded by a start bit & followed by one stop bit
b. Because each byte is preceded by a start byte & followed by one stop byte
c. Because each byte is preceded by a start bit & followed by one stop bit
d. Because each bit is preceded by a start byte &followed by one stop byte
ANSWER: (c) Because each byte is preceded by a start bit & followed by one
stop bit