Track-Micro/ Nano System

Day2 Date:08/12/18 Time:1:00 PM to 4:00 PM

Paper
Sr.No Title of the paper: Author(s):
ID:
Analytical Study For Development Of Fuel
1 7 Ankita Harkare
Adulteration Detection System
FPAA based design of assistive listening Dr. Sudhir B. Lande,Dr.Suresh S. Balpande,
2 54
device for hearing disorders people Dr. J.A. Shrawankar
Recent Development in Applications of
3 17 Poorvi K. Joshi
Optical MEMS: A Review
Performance Enhancement of
4 110E Polycrystalline Silicon based solar cell Sharmik Admane,Divya Chopde
using Ba2SiO4:Eu2+-Nd3+ phosphor

Track-Embedded System Design

Day2 Date:08/12/18 Time:1:00 PM to 4:00 PM

Paper
Sr.No Title of the paper: Author(s):
ID:
Development of Energy Management Archana Talhar,Sanjay Bodkhe,
1 33
System for Residential Load in India Anjali Chandane
Generation of SPWM Control Pulses for Punam c Moundekar,Gaurav Goyal ,
2 62
ZSI using dsPIC33EP256MU810 Dr. M.M.Renge
Pick and Place Automation machine Using Shubham Anjankar,Dr. Parag Jawarkar,
3 35
PLC and Ladder Programming Lokesh Heda,Vidya Dahake
Self Responding train detection and
4 109E Hasan Raza,Dewal Ande,Aslam Khan
wildlife alert system
Power aware Multiprocessor System on Mitali Patel, Jitendra B Zalke ,
5 122E Chip (MPSOC) based on Dynamic Sandeep Kumar Pandey,Anuradha D Verma,
frequency scaling of soft core processors Ruchir V. Nandanwar
Signaling approached based NoC
6 23 architecture for improving Quality of Jaya R. Surywanshi,Dr. Swati S. Godbole
Service
SOC-ASIC (State-of-Charge-Application
Specific Integrated Circuit)- a Battery
Nakul Pathak,Prasad Pande, Lokesh M.
7 120E Voltage Monitoring System for Series-
Heda,Parag Jawarkar
Connected Battery cells in Electric Vehicle
for State-of-Charge estimation
 Track-Analog /Mixed circuits and system

Day2 Date:08/12/18 Time:1:00 PM to 4:00 PM

Paper
Sr.No Title of the paper: Author(s):
ID:
Investigation of ROPUF with improved
1 12 Aman Pandey,Sandeepkumar Pandey
Temperature Performance on FPGA

Performance Improvement of Montgomery

2 52 Multiplier Architecture Using Pre-Computation Prafulani Gajbhiye,Pankaj Joshi
and Unfolding Technique
gm based CMOS LNA Linearization Techniques Sumeet R. Wawarkar,Rupali
3 118E
– A Comparison Tawari,Mayank Thakkar,D.J.Dahigaokar
True Random Number Generator through Beat
4 28 Gouri Morankar
Frequency Oscillators in FPGA
Performance Analysis of N-Type Gated Diode
5 32 Yogesh N. Thakare,Sujata N. Kale
Three-Transistor DRAM in 180nm Technology