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2010 Silva Power Grid Simulation (15132)
2010 Silva Power Grid Simulation (15132)
2010 Silva Power Grid Simulation (15132)
Abstract—Modern deep sub-micron ultra-large scale inte- The simulation of power distribution networks is a difficult
gration designs with hundreds of millions of devices require task owing to the huge number of elements in such circuits [2],
huge grids for power distribution. Such grids, operating with
[3]. Much research and development has been devoted to this
decreasing power supply voltages, are a design limiting factor and
accurate analysis of their behavior is of paramount importance problem, both in the modeling and simulation phases. In this
as any voltage drops can seriously impact performance or paper, we concentrate on the analysis or simulation part of
functionality. As power grid models have millions of unknowns, the problem. We will assume a typical model of a power grid
highly optimized special-purpose simulation tools are required to consist of an extremely large RC network, sometimes with
to handle the time and memory complexity of solving for their
millions of nodes, with a complex set of excitation sources
dynamic behavior. In this paper, we propose a hierarchical matrix
representation of the power grid model that is both space and and drains. Inductance is sometimes also included in the
time efficient. With this representation, reduced storage matrix model, typically to model wire bonding, but by comparison
factors are efficiently computed and applied in the analysis at it represents a very small subset of the overall model. In
every time-step of the simulation. Results show an almost linear this paper we will restrict ourselves to the RC portion of the
complexity growth, namely O(n loga (n)), for some small constant
model as its analysis is always necessary even if inductance is
a, in both space and time, when using this matrix representation.
Comparisons of our academic implementation with production- included. Block techniques can be used to handle the coupling
quality code prove this method to be very efficient when dealing between the large RC block and the inductance-modeled
with the simulation of large power grid models. packaging/wiring sub-circuit. The network excitations usually
Index Terms—Power-grid analysis, power-grid simulation, hi- consist of the biasing sources, generally modeled as constant
erarchical matrices, power-grid-modeling, Cholesky decomposi- voltage sources, and the connection to the designed-in devices,
tion. which act as sources or drains depending on their electrical
state. A simplified model for such sources is to consider
I. Introduction them as time-varying independent current sources, but more
complex models that take into account loading and feedback
I N RECENT years, the relentless trend for high-
performance circuits with low-power consumption has
raised new challenges to designers. Higher performance has
into the network are sometimes used. This simplified modeling
approach has the important implication that the grid model
becomes a linear system, thus much easier to simulate. Com-
meant increased functionality fueled often by technology
mercial large scale power grid simulators in use nowadays
scaling. Achieving lower power has been met by special-
typically assume a model as described.
ized design techniques together with supply voltage scaling.
From a simulation standpoint, there are two families of
However, adding more functionality implies that more devices
techniques for the time domain analysis of the linear descrip-
must be powered, and thus huge power distribution networks
tion of the power grid: iterative or direct methods. For DC-
are now deployed throughout the design. Moreover, lower
type problems that require a single system solution, iterative
supply voltage makes potential voltage drops a more serious
methods are preferred. However, robust verification techniques
concern, as they may impact performance or functionality
require that dynamic analysis be performed, which implies
of the whole design by reducing noise margins and slowing
solving for the time evolution of the system along a given
down devices [1]. Therefore, it has become clear that in
simulation interval.
modern circuits proper design and behavior of power grids
Taking advantage of the problem structure and inspired
is a performance limiting factor. The efficient verification of
by knowledge gained in solving similar problems resulting
such grids is thus seen as an essential step in predicting and
from discretized elliptic partial-differential equations (PDE),
ensuring correct behavior and performance.
efficient algorithms have been proposed based on precondi-
Manuscript received July 24, 2009; revised March 4, 2010; accepted April tioned conjugate gradient [4] or multigrid methods [5], [6].
15, 2010. Date of current version September 22, 2010. This work was These methods show good convergence ratios, but require
supported in part by FCT (INESC-ID Multiannual Funding) through the
PIDDAC Program funds. This paper was recommended by Associate Editor several iterations for recomputing the solution of the system
R. Suaya. for each time-point (in essence the dynamic problem is similar
J. M. S. Silva is with Synopsys, Mountain View, CA 94043 USA (e-mail: to solving the same system with multiple right-hand sides).
joao.m.santos.silva@gmail.com).
J. R. Phillips is with Cadence Design Systems, Berkeley, CA 95134 USA Since a few hundred time points are usually employed in
(e-mail: jrp@cadence.com). the analysis, the potential advantages of iterative methods are
L. M. Silveira is with INESC ID, the Systems and Computers Engineering quickly lost. Direct methods, on the other hand, find an a
Institute, Research and Development/Instituto Superior Técnico, Technical
University of Lisbon, Lisbon 1000-029, Portugal (e-mail: lms@inesc-id.pt). priori system matrix decomposition which can then be used
Digital Object Identifier 10.1109/TCAD.2010.2061512 in accelerating the solution at each time-step. Even though the
0278-0070/$26.00
c 2010 IEEE
1524 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 10, OCTOBER 2010
B. Problem Complexity If, for instance, B11 and B22 are fairly dense (large number of
The trivial solution to (2) is v = A−1 b. Unfortunately, nonzero entries) and full rank, they should be represented by
although A is sparse, A−1 is full and therefore computing full matrices. On the other hand, if B12 and B21 are low rank
the inverse is prohibitive. Iterative methods, such as conjugate they can be represented in a factorized form
gradient (CG), preconditioned CG (e.g., incomplete Cholesky
BIJ ≈ MN T (4)
preconditioned CG (ICCG) [4]) or multigrid (MG) can be used
to solve (2). Given that the system matrix, A, is symmetric and where M ∈ R#I×k , N ∈ R#J×k and k is the rank of the block
positive-definite, CG-type methods appear to be prime tech- up to some accuracy, eps (#I and #J represent, respectively,
niques for this problem. Furthermore their convergence rates the number of rows and columns of matrix block BIJ ). This
grow slowly with problem size, their memory requirements representation will be most efficient if k #I, #J. Obviously,
are minimal, and the cost per iteration is quite low. However, not all blocks will allow such a representation.
the need for a good preconditioner which requires non-trivial The goal of finding a H-Matrix representation is akin
effort to generate, and the fact that solutions at multiple time to determining the right reordering and blocking of nodes
points along a pre-defined time interval are required, end (rows/columns), that maximizes the number of blocks that can
up dwarfing increased usage of such techniques. Multigrid- be represented in factorized form. Note that the low-rank block
type algorithms are interesting in that they possess optimal representation in (4) is approximate. Using a pre-specified
theoretical complexity properties. However, in practice, the accuracy parameter eps, we can control the rank-k used to
setup costs, the need for multiple time point solutions, and represent the low-rank blocks in factorized form [7], [11].
the constant terms associated with the complexity estimates Error bounds for the low rank approximation of matrix blocks
seem to cast a shadow on the advantages, as discussed in [5]. can be derived and are available in many cases [7]. If a block
For dynamic analysis of power grid systems, direct methods is not represented in factorized form, it may be further split
are still the methods of choice, as the cost of computing matrix and its sub-blocks recursively tested for such a representation.
factors is amortized over all time-step solutions. So, H-Matrices are matrices which result from the recursive
multilevel splitting of matrix blocks, until low-rank blocks are
found and represented in factorized form, or no further sparsity
III. Hierarchical Matrices is available and full matrices must be used. Of course, the
Hierarchical Matrices, or H-Matrices [8], [9], enable matrix optimum storage scheme for a sparse stiffness matrix such as
operations in almost linear complexity, where “almost linear” A in (2) is well known, with only nonzero elements being
means linear up to logarithmic factors. H-Matrices are the stored in an efficient way. The more interesting question is
algebraic counterpart of panel clustering techniques [10] for how to represent the corresponding LU or Cholesky factors.
integral operators. Due to the existence of Green’s function While a matrix resulting from an FD discretization in 1-D
for elliptic problems, these techniques can be extended to yields no LU or Cholesky fill-in, the same does not apply to
inverses [11] and factorizations [12], [13] of finite-element 2-D matrices and certainly not to 3-D matrices, whose factors
and finite-difference type matrices. Given the already noted tend to fill up.
structural similarity between the power grid formulation and
those resulting from elliptic PDEs [5], this implies that effi- B. H-Matrix Splitting Approaches
cient representations exist for the inverse and the LU/Cholesky
In this paper, we use H-Matrices to represent the Cholesky
factors of the underlying matrix describing the power grid
factors of power grid models. This can be achieved through
model. Once that representation is formed, efficient, almost
one of two distinct approaches: geometrically or algebraically.
linear computations are within grasp. Theoretical and practical
results indicate both storage and computational complexity to 1) H-Matrix Geometric Splitting: In the geometric ap-
grow as O(n × loga (n)), for some small constant a [7], [14], proach, the criteria to decide whether a block allows a low-
when using H-Matrices. In this section, we discuss how to rank approximation is based on the geometry of the underlying
generate and operate with such a representation. medium discretization. This criteria is also called admissibil-
ity [9], [14], meaning whether the block admits a represen-
tation by a low-rank factorization or not. The admissibility
A. H-Matrix Fundamentals
check procedure, and therefore the reordering and clustering
H-Matrices are efficient data-sparse representations of cer- of nodes, must be such that blocks are obtained that allow
tain densely populated matrices. The basic idea is to split a for a low-rank factorization in terms of the LU or Cholesky
given matrix into a hierarchy of blocks and approximate each factors, not on the original sparse matrix.
of the blocks by a low-rank matrix. H-Matrices are super- Consider two sets of nodes in the physical domain, which
matrices (in the sense that they may contain either full, low- we term as clusters, and assume that each cluster has a radius
rank, and other super-matrices) with an inherent hierarchy of corresponding to a bounding box that includes all nodes in
block splitting. the cluster. If the physical distance between clusters is much
Consider a splitting of B = A−1 from (2), which we know larger than the cluster radius, it is likely that the interaction
to be full, in 2 × 2 blocks between nodes in separate clusters can be represented by a
B11 B12 low-rank approximation (this type of reasoning is akin to a
B= . (3)
B21 B22 multipole-type approximation [15], [16]). If the cluster size
1526 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 10, OCTOBER 2010
is too large to satisfy the admissibility criteria, it is split and from the finest graph which represents the matrix and build
each resulting sub-cluster is then checked. clusters over its nodes, then build a coarse graph by merging
Therefore, in order to represent the matrix block AIJ , which the nodes in the same cluster, and repeat this process on
relates the nodes in I to the nodes in J in the domain of the LU the coarsened graphs until we reach a single cluster. This
or Cholesky factors, by a low-rank sub-matrix, an admissibility procedure uses the edge weights from the coarse graphs to
condition such as the following must be observed [7]: make decisions on the merging of nodes.
In essence, the cluster tree is a format to represent and
min{diam(XI ), diam(XJ )} ≤ η × dist(XI , XJ ) (5) store the matrix. The H-Matrix representation has the same
hierarchy or tree structure as the cluster tree. The matrix
where XI and XJ are the supports of the local basis functions
row/column indexes are in fact the leaves of the cluster tree.
of I and J, respectively, diam(·) is the Euclidean diameter of
the bounding boxes, dist(·) is the Euclidean distance between D. H-Matrices Arithmetic and Complexity
the bounding boxes, and η is an admissibility parameter (used
to relax or restrict the admissibility criteria). See [7] for details. As discussed, our goal is to directly compute a hierarchical
The splitting process is repeated until a minimal block size LLT Cholesky factorization of the symmetric matrix A in
is reached, nmin , or the blocks can be approximated in a low- (2) in an efficient manner and then proceed with forward
rank sense. Large blocks are inefficiently approximated by (4) and backward solves at each time-step (for non-symmetric
and must be split whenever possible in order to give origin formulations, an LU factorization is generated and used in
to smaller low rank blocks. This approach is the right one a similar fashion).
when handling regular structures where geometrical distance In terms of complexity, the storage of a rank k factorized
is a good criteria for estimating (electrical) influence. n × n matrix requires 2 × k × n (instead of n2 ) elements. For
2) H-Matrix Algebraic Splitting: An alternative approach the H-Matrix, the storage is O(n × log(n) × k), in which k is
is based on the algebraic information of the matrix. This is the worst-case rank of the sub-matrices of the H-Matrix [14].
the technique of choice for irregular structures and likely the The Cholesky decomposition in the H-Matrix format requires
best one for common power grids. Whenever two nodes in the O(n × log2 (n) × k2 ) operations and the evaluation of the LLT
conductance matrix are “connected” by an entry exhibiting a factors in each time-step requires O(n×log(n)×k) operations,
large magnitude, this means that the nodes are indeed tightly which is proportional to the storage requirements of the H-
connected and should be kept together in the splitting process. Matrix representation of the Cholesky factors (for details,
This approach is akin to the standard heavy edge matching see [14]).
(HEM) algorithm [17]. In these methods, used for instance
in the publicly available graph partitioning tool Metis [17], IV. Implementation Framework
nodes connected by a large conductance and/or capacitance
The goal of this paper is to ascertain whether H-Matrix
are favored to be clustered together through the multilevel
representations of power grid models can enable its efficient
splitting process. The advantage of this method over the
space and time analysis and verification. In order to achieve
previous one is that no geometric information on the problem
this, we should be able to compress the power grid model
is required, since the structure of the H-Matrix relies solely
representation by efficiently computing reduced storage matrix
on the matrix entries. On the other hand, being able to follow
factors which in turn must be efficiently applied in the analysis
geometric admissibility conditions leads to a slightly better
at every time-step of the simulation.
approximation of the representation. The duality between
We must then convert the existing information regarding
geometric and algebraic splitting is quite similar to that found
the power grid structure into a representation leading to a
when considering multigrid and algebraic multigrid methods.
hierarchical Cholesky factorization of the system matrix. Ad-
ditionally, we require the ability to operate with matrices in H-
C. H-Matrix Representation Matrix representation in order to compute the system solution
To build an H-Matrix corresponding to a sparse matrix, we at each time point of the simulation interval. In this paper, the
first need to build what is known as a cluster tree over the factorization as well as all the required algebraic operations are
matrix index set. This cluster tree describes the hierarchical performed with the proper arithmetic functionality provided by
clustering of the nodes of the matrix (from bottom to top) that the H-Matrices library, HLib [14].
yields the hierarchical partitioning of the matrix. Note that the The current release of the HLib package [18] is freely
clusters are composed of nodes which may not be adjacent, available for research purposes under a simplified agreement.
which implies row-column reordering may be required. It consists of a set of routines for constructing and operating
The difference between the algebraic and the geometric with hierarchical matrix structures, i.e., cluster trees, block
approaches for building the cluster tree is that in the geo- cluster trees, low-rank factorized matrices, super-matrices, and
metric approach we use geometric conditions (admissibility so on. It also provides discretization functions for basic FEM
conditions) to determine whether or not a block of the matrix and BEM operators, as well as arithmetic functionality for per-
will be partitioned further. On the other hand, in the algebraic forming basic matrix operations like addition, multiplication,
approach the construction of the cluster tree is based on factorizations, and inversion. The library also contains routines
multilevel clustering methods which are widely used in graph that allow conversion of sparse and dense matrices into H-
partitioning. The basic idea of multilevel clustering is to start Matrices as well as a set of additional functionality relevant in
SILVA et al.: EFFICIENT SIMULATION OF POWER GRIDS 1527
TABLE V
Statistics for IBM Power Grid Benchmarks
Benchmark n1 v n2 r r/n2 i d
ibmpg1 30 635 14 308 16 327 30 027 1.84 10 874 5
ibmpg2 127 235 330 126 905 208 325 1.64 38 046 2
ibmpg3 851 581 955 850 626 1 401 572 1.65 201 548 3
ibmpg4 953 580 962 952 618 1 560 645 1.64 277 288 2
ibmpg5 1 079 307 539 087 540 220 1 076 848 1.99 540 900 5
ibmpg6 1 670 491 836 239 834 252 1 649 002 1.98 761 616 2
n1 is the original number of nodes, n2 is the number of nodes after computing the Norton equivalent of all voltage sources and removing short-circuits, r is
the number of resistors, i is the number of current sources (ports) after computing the Norton equivalent, and d is the number of disconnects.
TABLE VI
Results for ibmpg2 and ibmpg4 with Cholmod and HLib [Raw Results and Ratios Between Results (HLib/Cholmod)]
Benchmark Method Setup Time Ratio Solve Time Ratio Space Ratio Max. Rel. Err.
(s) (HL/Ch) (s) (HL/Ch) (MB) (HL/Ch)
Cholmod 1.57 19.54 0.08 2.63 69 2.93 –
ibmpg2
HLib 30.68 0.21 202 4.897e-04
Cholmod 111.62 5.20 1.04 2.40 996 2.44 –
ibmpg4
HLib 579.92 2.50 2432 7.506e-03
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1532 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 10, OCTOBER 2010
João M. S. Silva (M’02) was born in Lisbon, Dr. Phillips was an Associate Editor of the IEEE TRANSACTIONS ON
Portugal. He received the Licenciatura, M.S., and COMPUTER-AIDED DESIGN from 2005 to 2009, and has served on the
Ph.D. degrees in electrical and computer engineering Executive Committee of the International Conference on Computer-Aided
from Instituto Superior Técnico, Technical Univer- Design (ICCAD), as well as the technical program committees of numerous
sity of Lisbon, Lisbon, in 2000, 2003, and 2008, conferences including DATE, DAC, and ICCAD.
respectively.
He was a Researcher with INESC ID, the Systems
and Computers Engineering Institute, Research and Luı́s Miguel Silveira (S’85–M’95–SM’00) was
Development. He is currently a CAD Engineer with born in Lisbon, Portugal. He received the Engineers
Synopsys, Mountain View, CA. His current research (summa cum laude) and Masters degrees in electrical
interests include computer-aided design algorithms and computer engineering from the Instituto Supe-
for electronics, physical design of very large scale integration circuits, and rior Técnico (IST), Technical University of Lisbon,
computer architectures. Lisbon, in 1986 and 1989, respectively, and the M.S.,
E.E., and Ph.D. degrees from the Massachusetts
Institute of Technology, Cambridge, in 1990, 1991,
Joel R. Phillips (S’91–M’97–SM’05–F’09) received and 1994, respectively.
the S.B., M.S., and Ph.D. degrees from the Mas- He is currently a Professor of electrical and com-
sachusetts Institute of Technology, Cambridge, in puter engineering with IST, Technical University of
1991, 1993, and 1997, respectively. Lisbon, a Senior Researcher with INESC ID, the Systems and Computers
Since 1997, he has been with Cadence Design Engineering Institute, Research and Development, and a founding member of
Systems, Berkeley, CA. the Lisbon Center of the Cadence Research Laboratories. His current research
His current research interests include the applica- interests include various aspects of computer-aided design of integrated
tion of numerical simulation techniques to problems circuits, with emphasis on interconnect modeling and simulation, parallel
in electronic design automation. He received notable computer algorithms, and the theoretical and practical issues concerning
paper citations from the Design Automation Con- numerical simulation methods for circuit design problems.
ference (DAC) 2000, DAC 2002, the Proceedings Dr. Silveira is an Associate Editor of the IEEE Transactions on
of the 15th Symposium on Integrated Circuits and Systems Design, Design, Computer-Aided Design and has served on the technical program commit-
Automation and Test in Europe (DATE) 2004, the 2006 International Con- tees of numerous conferences, including DATE and ICCAD. He has received
ference on Very Large Scale Integration of System-on-Chip, and the 1995 notable paper citations at various conferences, including ECTC, ICCAD,
Copper Mountain Conference on Multigrid Methods. DAC, DATE, and SBCCI. He is a member of Sigma Xi.