IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 67, NO.
11, NOVEMBER 2020 3693
Multi-Channel Analog-to-Digital Conversion
Techniques Using a Continuous-Time
Delta-Sigma Modulator Without Reset
R. S. Ashwin Kumar , Member, IEEE, and Nagendra Krishnapura , Senior Member, IEEE
Abstract— Two methods are presented for implementing
a multi-channel ADC using a continuous-time delta-sigma
modulator (CTDSM) without resetting its states. The first is
adapted from a method used with a discrete-time delta-sigma
modulator. It uses a sample-and-hold (S/H) at the Nyquist rate
before the modulator and an adaptive equalizer at the Nyquist
rate after the modulator for flattening the equivalent frequency
response and eliminate memory. The newly proposed π-shifted
filter, instead of flattening the equivalent discrete-time frequency
response, merely ensures that the equivalent frequency response
is symmetric about ω = π/2. In the time domain, this means
that the equivalent impulse response at the Nyquist rate has
zero-valued odd samples ensuring no cross-talk between two
multiplexed inputs. Compared to the adaptive equalizer used
for flattening the frequency response, this filter consumes three
times lower power while occupying half the area. A two-channel
ADC is demonstrated using both the adaptive equalizer & the
π-shifted filter. The ADC uses a CTDSM running at 6.144 MHz
with an oversampling ratio (OSR) of 64, yielding a per-channel
bandwidth of 24 kHz. The prototype in 180 nm achieves a peak
SNR/SNDR/DR of 91.7 dB/84.9 dB/98 dB and consumes 1.33 mW
per channel with adaptive equalizer. The SNR/SNDR/DR is
90.5 dB/83.7 dB/97 dB with a power consumption of 0.86 mW per
channel with the π-shifted filter.
Index Terms— Analog-digital conversion, multi-channel
analog-to-digital converter (ADC), delta sigma modula-
tion (DSM), crosstalk, equalizers.
I. I NTRODUCTION
I N MANY sensor applications, multiple analog signals need
to be digitized with a wide dynamic range (DR). In such
scenarios, a multi-channel analog-to-digital converter (ADC)
is required. Such an ADC is typically realized by
time-multiplexing the different inputs, using a single ADC to
digitize this multiplexed input, and demultiplexing its output
to obtain the digitized version of the inputs. ADCs used
with multiplexed inputs must be memoryless. In other words,
the ADC must provide a digital output that depends only on
the current input sample and has no dependence on the past
inputs. Otherwise, there will be cross-talk among the channels.
Manuscript received February 28, 2020; revised June 2, 2020 and July 22,
2020; accepted July 27, 2020. Date of publication August 17, 2020; date of
current version October 30, 2020. This work was supported by the Ministry of
Electronics and Information Technology, Government of India. This paper was
recommended by Associate Editor T. Siriburanon. (Corresponding author:
R. S. Ashwin Kumar.)
The authors are with the Department of Electrical Engineering, IIT Madras,
Chennai 600036, India (e-mail: rsashwinkumar@gmail.com).
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2020.3013691
1549-8328 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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Oversampled ADCs using delta-sigma modulators (DSM)
are the popular choice for realizing high-resolutions. But,
the signal transfer functions of the modulator and the sharp
decimation filter add memory to the system. As a result,
the output of a delta-sigma ADC1 (DS-ADC) at any given
instant of time depends not only on the input at that particular
instant but also on several past input samples. This prevents
the deployment of DS-ADCs in multiplexed environments.
Using a DS-ADC in the incremental mode is the commonly
used solution to overcome this problem. In this, the memory
elements such as capacitors in the loop filter of the DSM
and the registers in the decimation filter are reset before
every conversion. Therefore, the system “forgets” the previous
input samples and performs memoryless A/D conversion. But
the signal-to-quantization-noise ratio (SQNR) and the signal-
to-thermal-noise ratio (SNR) are lower than what one would
obtain from a regular DS-ADC [1]. Also, when a multi-bit
DAC is used in an incremental DSM with an order higher than
one, the conventional mismatch shaping algorithms like the
data-weighted averaging (DWA) do not work well and more
complicated algorithms like the smart-DEM [2] are required.
Techniques using an equalizer to remove the memory
in a discrete-time DS-ADC so that it can be used with
multi-channel inputs were proposed in [3] and [4]. In this
work, we explore two techniques to realize a multi-channel
ADC using a continuous-time DSM (CTDSM). One of them
uses an inverse filter as the equalizer to flatten the frequency
response as done in [4]. Another one uses the newly proposed
“π-shifted filter” to eliminate cross-talk. The latter turns out to
have a lower order than the former. It also eliminates the need
for LMS adaptation that is required with the former. Thus,
the power and area of the digital filter are greatly reduced.
The rest of the paper is organized as follows. Section II
describes techniques that can be used to avoid cross-talk
in a two-channel system. A new filter termed the π-shifted
filter is proposed for this purpose. Section III summarizes the
equalizer-based techniques proposed in [3] and [4]. Section IV
describes multi-channel CTDSM implementations using the
techniques in [4] as well as using the proposed π-shifted filter.
Section IV-C describes a two-channel ADC using a CTDSM
and a π-shifted filter. Section V describes the implemented
1 We define the combination of a DSM, decimation filter with the down-
sampler as the delta-sigma ADC (DS-ADC).
 3694 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 67, NO. 11, NOVEMBER 2020

prototype and discusses the design choices. The proposed

multi-channel CTDSM is compared against SAR and incre-
mental delta-sigma ADCs in Section VI. The measured results
are shown in Section VII, followed by the conclusion. The idea
of the π-shifted filter is generalized to an arbitrary number of
channels in the appendix.

II. C ROSS -TALK IN A M ULTIPLEXED S YSTEM

Consider the two-channel system in Fig. 1(a) in which two
inputs u 1 (t) and u 2 (t) are sampled at the rate f N /2 to obtain
u 1 [n] and u 2 [n]. They are multiplexed to form a single stream
u[n] at f N . u[n] is then demultiplexed to get v 1 [n] and v 2 [n].
Since the multiplexer (MUX) and the demultiplexer (DMUX)
operate in tandem, it is clear that v 1 [n] = u 1 [n] and v 2 [n] =
u 2 [n]. There is no cross-talk, i.e., a component of u 1 [n] in
v 2 [n] or vice versa.
Now, consider Fig. 1(b) in which a filter Heff (z) is intro-
duced between the MUX and the DMUX. The output of the
filter is denoted by v[n]. This is a system with two inputs and
two outputs. We define the following four transfer functions
between them. H12(z) and H21(z) are the cross-talk transfer
functions from u 2 to v 1 and u 1 to v 2 , respectively. H11(z) and
H22(z) are the signal transfer functions from u 1 to v 1 and u 2
to v 2 , respectively. To prevent cross-talk, we need to ensure
that H12(z) = H21(z) = 0.
To derive the constraint on Heff (z) for zero cross-talk,
we use Fig. 1(c) which is the signal processing equivalent
of Fig. 1(b). The multiplexer is replaced by a combination
of upsamplers, a delay, and an adder. Similarly, the demulti-
plexer is replaced by a combination of a time-advance block2
and downsamplers. The impulse responses h 11 [n], h 22 [n],
h 12 [n], h 22 [n] (at f N /2), corresponding to H11(z), H22(z),
H12(z), H22(z), respectively, can be related to h eff [n] (at f N ),
the impulse response of Heff (z), as follows:
Fig. 1. (a) A multiplexer followed by a demultiplexer, (b) transfer function
h 11 [n] = h 22 [n] = h eff [n]↓2 (1) Heff (z) introduced between the two, (c) signal processing equivalent of (b),
h 12 [n] = h eff [n − 1]↓2 ; h 21 [n] = h eff [n + 1]↓2 (2) (d) impulse responses in (c), (e) impulse responses for the special case of
(a) where Heff (z) = 1, (f) ADC with an effective transfer function of unity
at f N , (g) ADC with G 0 (z)  = 1 being equalized by Heq (z).
where h[n]↓2 denotes 2× downsampling by selecting the even
samples of h[n]. The cross-talk impulse responses consist
of only the odd samples of h eff [n] and the signal impulse It also forces the individual signal transfer functions to unity,
responses consist of only the even samples of h eff [n]. Fig. 1(d) i.e., H11(z) = H22(z) = 1.
shows an example. To have zero cross-talk, it is necessary to In our context, an ADC is placed between the MUX and
make h 12 [n] = h 21 [n] = 0, i.e., for h eff [n] to have zero-valued DMUX for multi-channel operation. The impulse response of
odd samples. If only the even samples of h eff [n] are non-zero, the linear model of a Nyquist ADC (e.g., SAR or pipelined)
its discrete-time Fourier transform Heff (ω) will be periodic or an incremental delta-sigma ADC is δ[n]. Such ADCs can
with a period of π, i.e. Heff (ω − π) = Heff (ω) [5]. be placed between the MUX and DMUX without further
We now revisit Fig. 1(a) which has zero cross-talk. In this modification, and the system works as in Fig. 1(a). When
case, Heff (z) = 1 and h eff [n] = δ[n]. Fig. 1(e) shows the the transfer function of the ADC G 0 (z) = 1, as is the
corresponding signal and cross-talk impulse responses. h 12 [n] case with a continuously running delta-sigma ADC1 , the odd
and h 21 [n] and indeed zero as required for zero cross-talk, but, samples of its impulse response g0 [n] are not necessarily
additionally, h 11 [n] = h 22 [n] = δ[n]. Heff (z) = 1 is therefore zero. One possible way to use such an ADC in a multiplexed
a sufficient but not a necessary constraint for zero cross-talk. system without cross-talk is to mimic the case of a Nyquist
ADC and force Heff (z) to be unity. There are two alterna-
2 A 2× downsampler picks only the even samples (v [0], v [2], . . .). So, tives to accomplish this. The first is to choose the transfer
eq eq
to get v 2 [n] (the odd samples of v eq [n]), the data is advanced in time by functions of the modulator and the decimation filter so that
one sample by the time-advance block z. The output of this block will be
{v eq [1], v eq [2], . . .}. This when downsampled by two, i.e., selecting every sec- G 0 (z) turns out to be unity. This is shown in Fig. 1(f).
ond sample will give the odd samples of v eq [n], i.e., {v eq [1], v eq [3], . . .}. The second is to use an inverse equalizer Heq (z) = 1/G 0 (z)

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 ASHWIN KUMAR AND KRISHNAPURA: MULTI-CHANNEL ANALOG-TO-DIGITAL CONVERSION TECHNIQUES USING A CTDSM 3695

Fig. 2. (a) A discrete-time delta-sigma ADC. H (z) represents the decimation

filter, (b) delta-sigma modulator replaced by its signal transfer function Fig. 3. (a) Sample-and-hold operating at f s /M to be used at the input of
STF(z). Quantization noise is not shown. the delta-sigma ADC in Fig. 2, (b) equivalent model using a zero-order hold
S(z).
such that Heff (z) = Heq (z)G 0 (z) = 1. This is shown
in Fig. 1(g). These two approaches are demonstrated in [3]
and [4], respectively. These techniques are described in the
next section. In Section IV, it is shown that the first technique
is not practical with a CTDSM whereas the second one can
be adapted satisfactorily.
Instead of forcing Heff (z) to be unity, we can use only the
necessary condition, i.e., have zero-valued odd samples for
h eff [n], or, equivalently, Heff (ω − π) = Heff (ω). Therefore,
in Fig. 1(g), we can use an equalizer Heq (z) such that
the overall transfer function Heff (z) = Heq (z)G 0 (z) obeys
the zero cross-talk property, i.e., Heq (ω − π)G 0 (ω − π) = Fig. 4. DTDSM in Fig. 2 preceded by the sample-and-hold in Fig. 3. G(z) is
Heq (ω)G 0 (ω). By inspection, we can see that using Heq (ω) = the LTI system at f s from u u [n] to v f [n]. G 0 (z) is the LTI system at f s /M
from u[n] to v[n].
G 0 (ω − π) satisfies the constraint. Given this relationship,
the equalizer is termed as the π-shifted filter Hπ (ω) =
transfer function operating at f s /M. Therefore, it cannot be
G 0 (ω−π). Its impulse response and transfer function are given
used straightforwardly as shown in Fig. 1(f, g).
by h π [n] = (−1)n g0 [n] and Hπ (z) = G 0 (−z), respectively.
In earlier work ( [3], [4]), a sample-and-hold (S/H) operating
Details of a π-shifted equalizer for a two-channel CTDSM
at f s /M is used before the discrete-time delta-sigma ADC as
without reset are given in Section IV-C. It is shown that the
shown in Fig. 3(a). The held output u h (t) is sampled at f s
π-shifted filter has a significantly smaller area and power
by the input capacitors of the DTDSM. u h [n], the samples of
dissipation than an inverse equalizer.
u h (t) at f s is the input to the discrete-time delta-sigma ADC.
It is easy to see that the system in Fig. 1(a), which
Fig. 3(a) is equivalent to Fig. 3(b) in which u[n], the samples
corresponds to Heff (z) = 1, works without cross-talk for
of the input u(t) at a rate f s /M are upsampled by M and
any number of input and output channels. This means that
passed through a zero-order hold transfer function S(z) = (1−
the inverse filter required to equalize a given ADC transfer
z −M )/(1 − z −1 ) to obtain u h [n].
function G 0 (z) is independent of the number of channels. The
Fig. 4 shows the discrete-time delta-sigma ADC in Fig. 2
π-shifted filter described above is specific to two channels. Its
with the equivalent model of the S/H in Fig. 3(b) at its
generalization to N channels is described in the appendix.
input. We now have an LTI system G(z) = S(z)STF(z)H (z)
operating at f s between an upsampler and a downsampler.
III. M ULTI -C HANNEL DTDSM U SING Heff (z) = 1 It can be shown that the system from u[n] to v[n] is equivalent
Fig. 2(a) shows a discrete-time delta-sigma ADC operating to a single LTI system G 0 (z) operating at f s /M, where G 0 (z)
at an oversampled rate f s . The input u(t) is sampled at f s is the first term in the M-path polyphase decomposition of
to get u fs [n]. The loop filter L(z), the ADC, and the DAC G(z) [4], [7]. This transfer function can be used in the form
form the delta-sigma modulator loop. A feed-forward path of Fig. 1(f) [3] or Fig. 1(g) [4] to realize the multi-channel
from the input to the output of the loop filter is typically ADC shown in Fig. 1(b). These are described below.
used to reduce distortion [6] and to realize a signal transfer
function of unity. H (z) is the decimation filter, and its output is
downsampled by M, the oversampling ratio. This delta-sigma A. Using Unity STF DSM With Raised-Cosine Decimation
ADC has an equivalent Nyquist sampling rate of f N = f s /M. Filter and Inverse-Sinc Equalizer
Fig. 2(b) shows the linear model of the delta-sigma ADC, Fig. 5 shows a technique in which equalization at f s is
which will be used henceforth. The delta-sigma modulator is used to eliminate cross-talk. STF(z) is made unity by using a
modeled by its signal transfer function STF(z), operating at DTDSM with an input feed-forward path [6]. An inverse-sinc
f s . The quantization noise is not shown. Due to the presence equalizer HIS (z) realizes the inverse of the sample-and-hold
of downsampler, this is not a linear-time-invariant (LTI) sys- transfer function in the signal bandwidth. A raised-cosine [8]
tem [7] from u fs [n] to v[n] and cannot be represented by a decimation filter HRC (z) ensures that the effective impulse

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 3696 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 67, NO. 11, NOVEMBER 2020

Fig. 5. A two-channel ADC using a front-end S/H, a delta-sigma modulator with unity STF, a raised cosine decimation filter and an inverse sinc equalizer (RC-
IS) [3].

Fig. 6. A two-channel ADC using a front-end S/H, a delta-sigma modulator, a conventional decimation filter, and an equalizer at f s /M [4]. The equalizer
can be made adaptive to account for variations in S(z) and ST F(z).

response from u[n] to v[n] is δ[n], i.e., G 0 (z) = 1. A multi-

channel ADC using this principle is demonstrated in [3].
This technique, however, is sensitive to the realized transfer
functions of S(z) and ST F(z). Any deviation from the ideal
transfer functions will make the effective transfer function
Heff (z) = 1, and will, in turn, result in cross-talk. Moreover,
the choice of the decimation filter is now fixed and restricts
us from using conventional multi-rate decimation filters [9].
Besides, since the equalizer runs at the oversampled rate fs ,
it will consume a significant amount of power. Fig. 7. Realizing a signal transfer function of unity by sampling the input
at f s and shaping it by p(t).

B. Using an Inverse Equalizer at the Downsampled Rate

The second approach is to use (the FIR approximation
of) an inverse filter 1/G 0 (z) as the equalizer Heq (z) at the
downsampled rate. This is shown in Fig. 6. The effective
transfer function Heff (z) = 1 and there is no cross-talk. In this
technique, the decimation filter can be a conventional multi-
rate decimation filter. Because the equalizer is now running
at the downsampled rate, it is expected to consume lesser
power than in the previous technique. The equalizer can be
made adaptive to track the variations in the analog transfer
functions [4].
IV. M ULTI -C HANNEL CTDSM I MPLEMENTATIONS
In this work, we intend to use a CTDSM in a multiplexed
environment. The following reasons motivate us to do so.
In the system implemented in [3], [4] (Fig. 5 and 6), the
S/H has to drive the DTDSM. Since the DTDSM presents
a switched capacitor load at its input, it requires a high
current from the S/H opamp to ensure a linear operation.
As a result, in [4], the S/H accounted for ∼40% of the total
power. Besides, a CTDSM is more power-efficient than a
DTDSM [10]. Hence, by replacing the DTDSM by a CTDSM,
the overall power consumption of the system could be reduced
significantly. We discuss the different equalization approaches
in the context of a CTDSM in the rest of this section. The
prototype considered is a third-order CTDSM with an OSR
of 64 with a decimation filter with an equivalent order of
347 at fs .
A. S/H, Unity STF CTDSM, and the RC-IS Filter
To realize Fig. 5, the CTDSM needs an STF of unity.
Though an STF of unity is easily realizable in a DTDSM
with an input feed-forward path [6], it is not straightforward
in a CTDSM [11]. In principle, it can be done by sampling
the input at f s and shaping it by p(t), the same pulse shape
used for the feedback, as shown in Fig. 7. In this system,
if u fs [n] is a unit impulse, it is converted to a pulse by p(t),
and this pulse appears directly at v(t). Sampling this pulse
gives an impulse at v[n]. The DAC converts it to a pulse that
is identical to the one at the input. Therefore, the input and
the output of the loop filter L(s) are zero. Thus, v[n] = δ[n]
when the input u fs [n] = δ[n], implying a transfer function
of unity. In principle, this system can be used in place of the
DTDSM in Fig. 5 with a raised-cosine decimation filter and an
inverse-sinc equalizer (RC-IS filter) to realize a memoryless
ADC.

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 ASHWIN KUMAR AND KRISHNAPURA: MULTI-CHANNEL ANALOG-TO-DIGITAL CONVERSION TECHNIQUES USING A CTDSM
Fig. 8. (a) A continuous-time delta-sigma ADC driven by a sample and hold
at f s /M, (b) equivalent model.
In practice however, it would be hard to match the pulse
shapes p(t) in the input and the feedback paths exactly
because they would be implemented differently. From circuit
simulations, it was observed that cross-talk could not be
suppressed below −80 dBc. Besides these, any other variations
in the transfer functions of the S/H or the STF due to the
spread in component values lead to increased cross-talk.
B. S/H, CTDSM, and an Inverse Equalizer at f s /M
The architecture in Fig. 6 is more amenable for use with
a continuous-time delta-sigma modulator. Fig. 8(a) shows a
continuous-time delta-sigma ADC driven by a sample and hold
at fs /M. Fig. 8(b) shows the equivalent model. In this case,
the discrete-time transfer function STF(z) is the combined
response of the NRZ rectangular pulse and the sampled
response of the CTDSM, as shown in Fig. 8(b). Since an
adaptive equalizer can be used in Fig. 6, STF(z) need not
be known precisely.
The adaptive equalizer needs to be trained to realize the
inverse of G 0 (z). Fig. 9 shows the scheme used for adaptation.
An impulse train with a period of 128 samples (at f s /M) is
used as the input. Since the equalizer Heq (z) must realize
the inverse response 1/G 0 (z), the output of the equalizer
v eq [n] must be the same as the input u[n]. So the coefficients
of Heq (z) are varied so as to minimize the mean-squared
error between v eq [n] and delayed version of u[n]. The coef-
ficients are updated according to the following least-mean-
squares (LMS) recursion [12].
w[k + 1] = w[k] − μe[k]v[k] (3)
Here, w is the vector of filter coefficients and v is the
vector formed from v[k] such that v eq = w T v, and e[k] =
v eq [k] − u d [k], where u d [k] is the delayed version of the input
u[k]. To compute the error e[k], both v eq and u d need to be
known. To avoid the need to generate the digital version of
u d , the coefficients are updated only when the input is zero
(for 127 samples) and left unchanged when it is non-zero [4].
C. S/H, CTDSM, and the π-Shifted Equalizer at f s /M
Instead of the equalizer to invert G 0 (z), we can use the
π-shifted filter proposed in Section II. As in the previous
case, we have to contend with an unknown STF(z). But LMS
adaptation is not required in this case. The impulse response
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3697
Fig. 9. Training the equalizer with an impulse train. Adaptation is carried
out only when u d [n] = 0, and the grayed-out part with u d [n] is not required.
of the π-shifted filter is h π [n] = (−1)n g0 [n]. The input signal
used in Fig. 9 for adaptation is an impulse train, and it directly
yields g0 [n]. The output of the downsampler is averaged over
many periods of the impulse train to improve the accuracy in
determining g0 [n]. h π [n] can then be computed directly from
the measured g0 [n]. This is a more straightforward process
than finding the inverse using the LMS algorithm, which is
slower and requires additional computation.
The order of h π [n] is the same as that of g0 [n]. Since G 0 (z)
is the first term in the M-path polyphase implementation of
G(z), its order is NG0 = NG /M, where NG is the order of
G(z). Recall that G(z) = S(z)STF(z)H (z), where S(z) is the
S/H transfer function, STF(z) is the sampled pulse response of
the CTDSM, and H (z) is the decimation filter. So, NG will be
the sum of the respective orders, i.e., NG = NSH + NSTF + N H .
In our design, M = 64, which means the order of S(z) will
be NSH = 63. The decimation filter has an order N H = 347.
It was found from simulations that the sampled pulse response
of the CTDSM was restricted to less than 20 samples, and so
NSTF = 19. Thus, the order of h π is only seven. Besides, it was
found that three of these coefficients were very small and were
truncated to zero, resulting in only a fourth-order filter. On the
other hand, simulations showed that for the adaptive equalizer,
the order required is at least 24. Thus, with the proposed π-
shifted filter Hπ (z), there will be significant savings in power
and area of the digital section.
V. T WO -C HANNEL P ROTOTYPE
A two-channel ADC is designed and fabricated in a 180 nm
CMOS process. The CTDSM runs at 6.144 MHz with an
oversampling ratio of M = 64, so that each channel can
accommodate a bandwidth of 24 kHz. Fig. 10 shows the
implemented two-channel ADC. Due to the limited silicon area
available, only the adaptive equalizer was fabricated and the
π-shifted filter is realized off-chip. The coefficients for h π [n]
were obtained from the measured decimation filter output
during the training phase. The design choices and tradeoffs
involved with each sub-block are discussed next.
A. Sample-and-Hold
A flip-around sample-and-hold [13] circuit is used, in which
the input is sampled across a capacitor in one phase, and, in the
other phase, the same capacitor is flipped around the opamp
to form a negative feedback. By ping-pong sampling the two
 3698 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 67, NO. 11, NOVEMBER 2020
Fig. 10. Block diagram of the implemented 2-channel ADC. The sampling rate f s = 6.144 MHz.
Fig. 11. (a) Schematic of the flip-around S/H (single-ended version).
(b) Timing diagram of the clocks.
inputs across two separate capacitors, multiplexing operation
is also combined in the same circuit. Fig. 11(a) shows the
schematic of the S/H, and Fig. 11(b) shows the timing diagram.
Although a total of 64Ts is available for each channel, four
cycles (at f s ) at the start are dedicated to resetting the S/H so
that any residual memory of previous inputs is nulled (φ1,2z ).
After this, four more cycles are allotted for the S/H output to
settle. So during each phase (φ1,2 lasting for 64Ts ), for the
first 8Ts (φ1,2a ), the CTDSM input is connected to ground,
and for the remaining 56Ts (φ1,2b ), it feeds from the S/H.
During the training phase, an impulse train with a period
of 128 samples (at the rate fs /64) is needed. For this,
channel 1 is connected to a DC input once in 128 cycles (at
f s /64), and for the rest of the time, it is connected to ground.
Channel 2, on the other hand, is always shorted to ground.
Sampling these two channels alternately at f s /64 feeds the
impulse train to the system.
Since the S/H has to drive the CTDSM, it has to sup-
port the full input swing at its output. So, a two-stage
Miller-compensated opamp is used. It consumes 88 μA of
current and has a unity gain bandwidth (UGB) of 6 MHz.
Fig. 12 shows the schematic of the opamp.
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Fig. 12. Schematic of the two-stage Miller-compensated opamp used in the
S/H.
It can be shown that the in-band noise power added by the
S/H is
kT
NS = 2 + 8kT γ G m1 f b (4)
C
C is the input sampling capacitor, G m1 is the transconductance
of the first stage, and f b is the signal bandwidth of the
CTDSM. The Miller-compensation capacitor Cc used is 8 pF,
and the input sampling capacitor is chosen to be 120 pF.
B. CTDSM
1) Loop Filter: There are two choices for implement-
ing the continuous-time loop filter: i) cascade-of-integrators-
in-feed-forward (CIFF), and, ii) cascade-of-integrators-in-
feedback (CIFB). With a CIFF loop filter, it can be ensured
that there are almost no signal swings at the integrator outputs.
Therefore, the opamps can work with lower bias currents for
the same linearity specification. On the downside, the STF will
have out-of-band peaking. In a CIFB loop filter, each integrator
output will have signal swings, and therefore the opamps in the
integrators need higher currents to ensure a sufficiently linear
operation. On the other hand, a CIFB loop filter guarantees
a monotonically decreasing STF. In this work, a CIFF loop
filter is used since a low-power design is targeted.
2) Quantizer: A single-bit quantizer would have been the
ideal choice for a low-power design as the (a) loop filter output
can be scaled down to save power, (b) flash ADC requires only
one comparator, and (c) since a single-bit DAC is inherently
linear, no extra circuitry is needed to tackle DAC non-linearity.
However, a single-bit quantizer makes the modulator more
 ASHWIN KUMAR AND KRISHNAPURA: MULTI-CHANNEL ANALOG-TO-DIGITAL CONVERSION TECHNIQUES USING A CTDSM
Fig. 13. Schematic of the CTDSM with a CIFF-B loop filter, 3-bit quantizer,
and a 2-tap FIR DAC.
susceptible to clock-jitter [14], thereby reducing the SQNR.
To combat this, a finite-impulse-response (FIR) filter can be
added in the feedback path to reduce the jumps in the feedback
signal [14]. However, using an FIR DAC results in out-of-band
STF peaking [14], and this out-of-band peaking increases with
the order of the FIR filter. For our choice of the loop filter and
the targeted resolution, at least a 12-tap FIR filter is required.
This results in an STF peaking of more than 15 dB. This is
undesirable in our system because of the following reason.
The CTDSM processes the output of the S/H. Since the
S/H also multiplexes u 1 and u 2 , its output will have spectral
replicas of the inputs around the harmonics of the multiplexing
frequency. As a result, if the inputs u 1 and u 2 contain sinusoids
of frequencies f 1 and f 2 respectively, at the output of the S/H,
there will be tones at k f s /2M ± f 1 and k f s /2M ± f 2 . Because
of the presence of these strong out-of-band signals, any
peaking in the out-of-band STF could saturate the quantizer,
thereby limiting the maximum stable amplitude (MSA). It was
found that, in our case, using a single-bit modulator with a
12-tap FIR filter, the MSA was reduced by more than 12 dB.
This could be solved by adding appropriate feed-forward paths
to flatten the STF as in [11] but at the cost of increased loading
at the virtual ground nodes of the opamps in the loop filter.
Hence in this work, a 3-bit quantizer is used so that
clock-jitter does not severely degrade the performance. To get
further immunity from clock-jitter, a 2-tap FIR filter is used
in feedback. To compensate for the delay added by this FIR
filter, another 2-tap FIR DAC is added to the output of the 2nd
integrator, resulting in a CIFF-B structure, as shown in Fig. 13.
With these design choices (CIFF-B loop filter, 3-bit quantizer,
and a two-tap FIR DAC), the STF peaking was limited to 3 dB,
ensuring that there is no degradation in the MSA.
3) Opamps: For the first integrator, a two-stage
feed-forward opamp is used, with the currents shared between
the second-stage and the feed-forward transconductor,
as shown in Fig. 14 [14]. It consumes 160 μA of current. The
same opamp is scaled down and used in the second integrator.
The loop filter output is scaled by a factor of 3, to reduce the
current required in the third integrator. This allowed the use
of the same scaled-down opamp in the third integrator.
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3699
Fig. 14. Two-stage feed-forward opamp with current reuse used in the
CTDSM.
C. Flash ADC & DAC
The flash ADC is similar to the one in [15]. Since the loop
filter output is scaled down by a factor of three, the flash
ADC references also need to be scaled by the same factor in
order to ensure that the overall loop filter transfer function is
not changed. The reduced amplitude increases the comparator
delay, but for the chosen clock frequency of 6.144MHz, this
ELD is less than 4 percent of the clock-period and hence
does not affect the loop stability. Incremental data weighted
averaging (IDWA) [16] is used to shape out DAC non-linearity.
D. Digital Filters
1) The decimation filter is implemented as a cascade of a
fourth-order cascade of integrators and comb (CIC) and
a seventh-order half-band filter.
2) The adaptive equalizer is realized as a 24th order FIR
filter. Since the coefficients of the adaptive equalizer
need to be computed on the run, the equalizer requires
a dedicated multiplier. Instead of implementing 25 sep-
arate multipliers that would occupy a large area, only
one multiplier is implemented to realize a multiply-
accumulate (MAC) module. Operating this MAC at f s /2
ensures that at the end of 25 clocks cycles (at f s /2),
the MAC register will contain the filter output. At the
end of the 32nd cycle (at f s /2), the MAC register is
reset and is ready to compute the next output sample.
This ensures that the filter output is computed within one
clock cycle of f s /64. The decimation filter and the adap-
tive equalizer together occupy a total area of 0.58 mm2.
3) The π-shifted filter is realized as a seventh order FIR
filter. Again, since the coefficients of h π [n] will be
computed on the run, each tap requires a multiplier.
A single MAC unit is used and is run at f s /4, so that
the output will be available at the end of eight clocks
cycles (at f s /4). The decimation filter and Hπ (z) are
synthesized, and the area estimate after place & route is
only 0.24 mm2, which is more than 2× smaller than the
adaptive equalizer.
VI. C OMPARISON W ITH SAR AND
I NCREMENTAL D ELTA -S IGMA ADC S
The proposed two-channel ADC uses an S/H at its input.
So one might think that an anti-alias filter is required upfront
 3700 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 67, NO. 11, NOVEMBER 2020
TABLE I
P OWER C ONSUMED BY VARIOUS B LOCKS
and that the proposed system does not exploit the inherent
anti-aliasing property of an NRZ-DAC based CTDSM [10].
However, it should be noted that, even in a CT-incremental
DSM, an anti-alias filter will be required. This is because when
N inputs are multiplexed and fed to an ADC with a conversion
rate f N , each channel is equivalent to a Nyquist rate ADC at
f N /N. Thus, for each channel, an anti-alias filter that rejects
all frequency components beyond f N /(2N) is required in a
multiplexed ADC. Also, in applications where simultaneous
sampling of the analog signals is needed, each input signal
needs a separate S/H [17].
Since the input of the proposed multi-channel ADC has
a capacitor switching at the Nyquist rate, in terms of the
input impedance, it is identical to a Nyquist rate SAR ADC.
But the proposed system can outperform a Nyquist rate SAR
in terms of the achievable SNR, thanks to oversampling and
noise-shaping in the CTDSM.
The proposed system is also more efficient than an incre-
mental DSM. To understand this, we consider the designed
stand-alone CTDSM and find how much the power must
be increased to ensure that the corresponding incremental
DSM has the same SQNR, and SNR. The same calculation
is repeated for the proposed technique as well.
For an incremental ADC with a third-order loop filter,
the OSR must be increased by a factor of 1.8 to ensure that
the SQNR is the same as the stand-alone DSM. This factor
is even higher for a fourth-order loop filter. The degradation
in the signal-to-thermal-noise ratio in an incremental DSM
can be shown to be 2.6 dB for a third-order loop filter and
3.6 dB for a fourth-order one. This means that the impedances
in the CTDSM must be scaled by a factor of 1.8 (for third-
order loop filter) and by 2.3 (for a fourth-order loop filter).
This results in an increase in the power consumption by a
factor 1.8 × 1.8 = 3.24 (for a third-order loop filter), and
1.8 × 2.3 = 4.1 (for a fourth-order loop filter), compared to
the stand-alone CTDSM. These numbers are still optimistic as
the extra power consumed by the complicated DEM techniques
(such as the smart DEM [2]) required for the incremental ADC
has not been considered.
With the proposed technique, there are two extra blocks:
1) the π-shifted filter, which as shown in Table I consumes
210 μW (but will scale with process), and 2) the sample-
and-hold, which consumes 225 μW (though in simultaneous
sampling this will be needed and so might not be an extra
power in those applications). The CTDSM alone consumes
1.276 mW (including the decimation filter). The extra power
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Fig. 15. Chip layout and photo of the test board.
consumed by the S/H & the π-shifted filter is 435 μW. Thus,
the power consumed increases by a factor 1.3. The S/H in
this prototype has been designed to have equal thermal noise
contribution as the CTDSM. Thus, the total thermal noise
power increases by a factor of two, implying that the power
needs to be increased two-fold to ensure the same SNR. Thus,
the total power will increase by a factor of 2.6. This is at least
1.2× lower, when compared to a third-order incremental DSM,
and at least 1.6× lower compared to a fourth-order incremental
DSM.
VII. M EASUREMENT R ESULTS
Fig. 15 shows the snapshot of the chip layout and the
test-board used. The chip occupies an area of 2.7 mm×1.4 mm.
The power split-up is as shown in Table I.
In total, the ADC consumes 1.33 mW/channel when the
adaptive equalizer is used and 0.86 mW/channel when the
π-shifted filter is used. From Table I, it is clear that using
π-shifted filter offers more than 3× reduction in digital power.
Though an on-chip adaptive equalizer was present, the adap-
tive filtering was done off-chip in the measurements presented
in this section due to the following reason. When an impulse
train is applied during the training phase, both the channels
are shorted to ground for the duration (say Tz ) when the
impulse train is zero. The S/H then samples the two channels
alternately. But due to the different offsets in the two channels,
the actual training signal that is fed during Tz consists of
an extra DC term and a tone at ω = π. Hence, to extract
the response due to the impulse train, we need to extract gdc
and gπ (response due to the extra DC term and the tone at
ω = π respectively) and subtract it from the total response.
The average of the output during Tz gives gdc , and the average
of alternate samples during Tz after subtracting gdc from the
output gives gπ . Although the gdc -correction procedure was
included on the chip, the procedure for gπ correction was not.
So, the on-chip decimation filter output was taken out and
processed off-chip.
Fig. 16 shows the frequency response of the inverse filter
after adaptation and the π-shifted filter.
To characterize the chip as a two-channel ADC, two sinu-
soids at different frequencies 2.5 and 6 kHz at −6 dBFS
(Full-scale: 3.6 Vppd) were given to the two channels. Fig. 17
shows the spectrum of the demultiplexed outputs when the
adaptive equalizer is used. It can be seen that the cross-talk
here is below −83.6 dBc. Fig. 18 shows the spectrum when
the π-shifted filter is used, and the cross-talk is <−86.8 dBc. If
the decimation filter output is demultiplexed without applying
any of the proposed filtering techniques, then the cross-talk is
 ASHWIN KUMAR AND KRISHNAPURA: MULTI-CHANNEL ANALOG-TO-DIGITAL CONVERSION TECHNIQUES USING A CTDSM
Fig. 16. Frequency response of the adaptive equalizer and the π -shifted
filter Hπ (z).
Fig. 17. Spectrum of the demultiplexed outputs with the adaptive equalizer.
Fig. 18. Spectrum of the demultiplexed outputs with the π -shifted filter.
as high as −10 dBc. Thus, the proposed techniques improve
the cross-talk by more than 70 dB.
Fig. 19 shows the variation of cross-talk vs. the input
frequency with the adaptive equalizer and with the π-shifted
filter, when channel 2 was given a 6 kHz tone at −6 dBFS,
while channel 1 was given a sinusoid of different frequencies
at −6 dBFS. Cross-talk is measured in channel 2 as the
relative strength of the tone leaked in channel 2 with respect
to the applied tone in channel 1. Measured cross-talk is
below −77.8 dBc with the adaptive equalizer and is less than
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3701
Fig. 19. Variation of cross-talk (from channel 1 to channel 2) with frequency
with the adaptive equalizer and the π -shifted filter.
Fig. 20. Measured SNR and SNDR with the adaptive equalizer (DR is
computed from 0 dB SNR).
−80.1 dBc with the π-shifted filter across the full bandwidth
of 24 kHz. When the roles of the channels are reversed,
the cross-talk measured in channel 1 is less than −80.5 dBc
with the adaptive equalizer, and it improves to less than
−83.9 dBc with the π−shifted filter. The π-shifted filter
achieves a better cross-talk suppression than the adaptive
equalizer. This is because the π−shifted filter requires only the
impulse response g0 [n] of the equivalent LTI system G 0 (z).
On the other hand, the adaptive equalizer uses g0 [n] and then
estimates h eq [n] that realizes the inverse response 1/G 0 (z).
The extra error incurred in this estimation process of h eq [n] is
responsible for the slightly worse cross-talk suppression of the
adaptive equalizer. The difference in the cross-talk in the two
directions could be due to asymmetrical coupling between the
channels before multiplexing, which cannot be corrected by an
equalizer placed between the MUX and the DMUX in Fig. 1.
Fig. 20 & Fig. 21 show the variation of SNR and SNDR
versus input amplitude with the adaptive equalizer and the
π-shifted filter. For this experiment, 6 kHz tone at −6 dBFS
was applied to channel 1, and channel 2 was given a 2.5 kHz
tone at varying amplitudes; SNR is measured in channel 2.
The peak SNR and the dynamic range are 91.7 dB and 98 dB
respectively with the adaptive filter and 90.5 dB and 97 dB
respectively with the π-shifted filter. The output of channel
2 contains harmonics of the input to channel 2 as well
as the second harmonic of the input to channel 1, which
leaks into channel 2 (as shown in Fig. 17 and 18). SNDR
computed with and without this HD2 leakage are 90.3 dB &
84.9 dB respectively with the adaptive equalizer, and 89.2 dB
& 83.7 dB with the π-shifted filter. The HD2 leakage from
 3702 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 67, NO. 11, NOVEMBER 2020
TABLE II
P ERFORMANCE S UMMARY AND C OMPARISON
Fig. 21. Measured SNR and SNDR with the π - shifted filter (DR is computed
from 0 dB SNR).
channel 1 to channel 2 is about 7 dB above the noise floor.
This is reflected in the difference between SNDR including
this leakage and the SNR. The measured peak SNR in channel
1 is 92.2 dB with the adaptive equalizer, and 90.9 dB with
the π-shifted filter. The SNDR measured in channel 1 with
and without the HD2 leakage from channel 2 are 88.8 dB &
90.8 dB with the adaptive equalizer, and 87.6 dB & 89.7 dB
with the π-shifted filter.
Table II summarizes the performance of our system and
compares it with similar works in the literature. The dynamic
range FoM is comparable to other DSM based ADCs. SAR
ADC has the best Walden FoM, but the effective resolution
is only 11 bits, whereas the DSM based works easily achieve
more than 14 bits resolution.
VIII. C ONCLUSION
Techniques for realizing a multi-channel delta-sigma ADC
using a CTDSM are discussed. First, it was shown that,
by adding an S/H (operating at the Nyquist rate) before
a CTDSM, the overall system could be made linear time-
invariant. As a result, an adaptive equalizer can be used
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at the output of the ADC to ensure that the overall fre-
quency response is flat. This can then be used to realize a
multi-channel ADC. It was then shown that, to avoid cross-talk
in a two-channel system, it is both necessary and sufficient to
ensure that the overall frequency response is symmetric about
π/2. This condition can be satisfied by using a π-shifted filter,
whose frequency response is the same as that of the equivalent
LTI system but shifted in frequency by π-radians. Compared
to using an adaptive equalizer, the proposed technique of using
the π-shifted filter simplifies the digital filter design, thereby
giving a 3× savings in power and 2× savings in the area of
the digital section. Using these two techniques, a two-channel
ADC using a CTDSM with a wide dynamic range (> 96 dB) is
demonstrated in a 180 nm CMOS process. Although the input
impedance is similar to that of a Nyquist rate SAR ADC,
the proposed system can realize higher resolutions, since the
underlying ADC is a CTDSM. Also, since the modulator runs
continuously without reset, the proposed system can achieve
higher SNR than an incremental DSM, for the same power.
A PPENDIX A
Z ERO C ROSS -TALK E QUALIZER FOR N C HANNELS
The constraint for zero cross-talk described in Section II
for the two-channel case can be easily generalized to any
number of channels. In an N-channel system, for zero cross-
talk, the effective impulse response h eff [n] must be non-zero
only for integer multiples of N and zero otherwise. That is,
h eff [n] = 0 ; n = m N, m ∈ Z (5)
In this case, Heff (ω) is periodic with a period 2π/N [5].
In other words, Heff (ω) is symmetric about mπ/N, m =
1, 2, . . . , N − 1. i.e., Heff (ω − mπ/N) = Heff (ω + mπ/N).
To reduce cross-talk to zero, the filter Heq (z) that follows
G 0 (z) in Fig. 1(g) should make the total response periodic
with a period 2π/N. To achieve this, we use the following
principle, which combines shifted periodic functions to realize
a fraction of the original period. Since G 0 (ω) is periodic with
a period 2π, we construct a new function F2π/N (ω) as the
 ASHWIN KUMAR AND KRISHNAPURA: MULTI-CHANNEL ANALOG-TO-DIGITAL CONVERSION TECHNIQUES USING A CTDSM 3703

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