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ITSE305

Emu8086 LAB HANDOUT

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 8086 Programs
Practical Appendix
Index
Sno Program

1 8-Bit addition using Immediate Addressing mode

2 8-Bit addition using Direct Addressing mode

3 8-Bit addition using Indirect Addressing mode

4 8-Bit subtraction using Immediate Addressing mode

5 8-Bit subtraction using Direct Addressing mode

6 8-Bit subtraction using Indirect Addressing mode

7 8-Bit multiplication using Immediate Addressing mode

8 8-Bit multiplication using Direct Addressing mode

9 8-Bit multiplication using Indirect Addressing mode

10 8-Bit division using Immediate Addressing mode

11 8-Bit division using Direct Addressing mode

12 8-Bit division using Indirect Addressing mode

13 16-Bit addition using Immediate Addressing mode

14 16-Bit addition using Direct Addressing mode

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 15 16-Bit addition using Indirect Addressing mode

16 16-Bit subtraction using Immediate Addressing mode

17 16-Bit subtraction using Direct Addressing mode

18 16-Bit subtraction using Indirect Addressing mode

19 16-Bit multiplication using Immediate Addressing mode

20 16-Bit multiplication using Direct Addressing mode

21 16-Bit multiplication using Indirect Addressing mode

22 16-Bit division using Immediate Addressing mode

23 16-Bit division using Direct Addressing mode

24 16-Bit division using Indirect Addressing mode

25 Addition of 8-Bit array elements

26 Check if the given value is positive, negative or zero

27 Addition of 8-Bit array elements

28 Addition of series 1 + 2 + 3 +…… + n (8- bit hexadecimal values)

Printing / Generating series on memory locations ( 0, 1, 2, 3 … UPTO
29
N TERMS)
Printing / Generating series on memory locations ( 0, 2, 4, 6 …
30
UPTO N TERMS)
31 Finding Largest value from array

32 Finding Smallest value from array

33 Block Move (Moving a block of data from one location to another)

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 Steps to execute an assembly program
using EMU8086
Step 1: Select empty work space and type the program

Step 2: Compile the program

Step 3: Run the program

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Step 4: Observe the changes in the registers during program execution

Step 5: Observe the changes in the memory locations during program execution

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Step 6: Observe the changes in the flag register during program execution

Step 7: Run till program halts and note the values in registers and memory
locations

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 8-

ORG 100H

1. Bit addition using Immediate Addressing mode

MOV AL, 05DH

MOV BL, 0A3H
ADD AL, BL
HLT

Input is already hard coded in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL

5D 3A

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL

00 3A

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 8-

Output
ZF SF AF PF CF
Flags

1 1 1 1

2. Bit addition using Direct Addressing mode

ORG 100H

MOV AL, V1
MOV BL, V2
ADD AL, BL
MOV V3, AL
HLT

V1 DB 05DH V2
DB 0A1H
V3 DB 000H

Inputs are given using vectors V1, V2 mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL

5D A1

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 8-

ORG 100H

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL

FE A1

Output
ZF SF AF PF CF
Flags

3. Bit addition using Indirect Addressing mode

LEA SI, V1
LEA BX, V2
LEA DI, V3

MOV AL, [SI]

MOV BL, [BX]
ADD AL, BL
MOV [DI], AL
HLT

V1 DB 05DH V2
DB 0A2H
V3 DB 000H

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 8-

Inputs are given using vectors V1, V2 mentioned in t

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

5D A1

AX BX CX DX ZF SF AF PF CF
Output
Registers AH AL BH BL CH CL DH DL 1

FE A1

Output
Memory None

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 8-

ORG 100H

4. Bit subtraction using Immediate Addressing mode

MOV AL, 0FDH

MOV BL, 0A3H
SUB AL, BL
HLT

Input is already hard coded in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL

FD A3

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL

5A 3A

Output
ZF SF AF PF CF
Flags

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 8-

ORG 100H

5. Bit subtraction using Direct Addressing mode

MOV AL, V1
MOV BL, V2 SUB
AL, BL
MOV V3, AL
HLT

V1 DB 0EDH V2
DB 0A1H
V3 DB 000H

Inputs are given using vectors V1, V2 mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL

ED A1

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL

4C A1

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 8-

ORG 100H

Output
ZF SF AF PF CF
Flags

6. Bit subtraction using Indirect Addressing mode

LEA SI, V1
LEA BX, V2
LEA DI, V3

MOV AL, [SI]

MOV BL, [BX]
SUB AL, BL
MOV [DI], AL
HLT

V1 DB 0E4H
V2 DB 0A2H
V3 DB 000H

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 8-

ORG 100H

Inputs are given using vectors V1, V2 mentioned in t

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

E4 A2

AX BX CX DX ZF SF AF PF CF
Output
Registers AH AL BH BL CH CL DH DL 1

42 A2

Output
Memory None

7. Bit multiplication using Immediate Addressing mode

MOV AL, 011H

MOV BL, 003H
MUL BL
HLT

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 8-

ORG 100H

Inputs are given using Immediate addressing mentioned

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

11 03

AX BX CX DX ZF SF AF PF CF
Output
Registers AH AL BH BL CH CL DH DL

33 03

Output
Memory None

8. Bit multiplication using Direct Addressing mode

MOV AL, V1
MOV BL, V2 MUL
BL
MOV V3, AL
HLT

V1 DB 022H

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 8-

ORG 100H

V2 DB 004H
V3 DB 000H

Inputs are given using vectors V1, V2, V3 mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

22 04

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL ZF SF AF PF CF

88 04

Output
Memory None

9. Bit multiplication using Indirect Addressing mode

LEA SI, V1
LEA BX, V2
LEA DI, V3

MOV AL, [SI]

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 8-

ORG 100H

MOV BL, [BX]

MUL BL
MOV [DI], AL
HLT

V1 DB 033H
V2 DB 003H
V3 DB 000H

Inputs are given using vectors V1, V2, V3 mentioned in

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

33 03

AX BX CX DX ZF SF AF PF CF
Output
Registers AH AL BH BL CH CL DH DL

99 03

Output
Memory None

10. Bit division using Immediate Addressing mode

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 8-

ORG 100H

MOV AL, 00EH

MOV BL, 003H
DIV BL
HLT

Inputs are given using immediate data mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

0E 03

AX BX CX DX ZF SF AF PF CF

AH AL BH BL CH CL DH DL
Output
Registers AH remainder, AL Quotient
02 04 03

Output
Memory None

11. Bit division using Direct Addressing mode

MOV AL, V1
MOV BL, V2
DIV BL
MOV V3, AX

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 8-

ORG 100H

HLT

V1 DB 019H
V2 DB 004H
V3 DW 0000H

Inputs are given using vectors V1, V2 data mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

19 04

AX BX CX DX
Output ZF SF AF PF CF
Registers AH AL BH BL CH CL DH DL

01 06 04
AH remainder, AL Quotient

Output
Memory None

12. Bit division using Indirect Addressing mode

LEA SI, V1
LEA BX, V2

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 8-

ORG 100H

LEA DI, V3

MOV AL, [SI]

MOV BL, [BX]
DIV BL
MOV [DI], AX
HLT

V1 DB 019H
V2 DB 007H
V3 DW 000H

Inputs are given using vectors V1, V2 data mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

19 07

AX BX CX DX ZF SF AF PF CF

Output AH AL BH BL CH CL DH DL
Registers AH remainder, AL Quotient
04 03 07

Output
Memory None

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 16-

ORG 100H

13. Bit addition using Immediate Addressing mode

MOV AX, 0E15DH

MOV BX, 017A3H
ADD AX, BX
HLT

Inputs are given using immediate data mentioned in

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

E1 15 17 A3

AX BX CX DX ZF SF AF PF CF
Output
Registers AH AL BH BL CH CL DH DL 1 1 1

F9 00 17 A3

Output
Memory None

14. Bit addition using Direct Addressing mode

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 16-

ORG 100H

MOV AX, V1
MOV BX, V2
ADD AX, BX
MOV V3, AX
HLT

V1 DW 04A5DH
V2 DW 0A231H
V3 DW 00000H

Inputs are given using vectors V1, V2 mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

4A 5D A2 31

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL ZF SF AF PF CF

EC 8E A2 31 1 1

Output
Memory None

15. Bit addition using Indirect Addressing mode

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 16-

ORG 100H

LEA SI, V1
LEA BX, V2
LEA DI, V3

MOV AX, [SI]

MOV BX, [BX]
ADD AX, BX
MOV [DI], AX
HLT

V1 DW 0EEEEH
V2 DW 01111H
V3 DW 00000H

Inputs are given using vectors V1, V2 mentioned in t

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

EE EE 11 11

AX BX CX DX ZF SF AF PF CF
Output
Registers AH AL BH BL CH CL DH DL 1 1

FF FF 11 11

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 16-

ORG 100H

Output
Memory None

16. Bit subtraction using Immediate Addressing mode

MOV AX, 0E15DH

MOV BX, 017A3H
SUB AX, BX
HLT

Inputs are given using immediate data mentioned in

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

E1 5D 17 A3

AX BX CX DX ZF SF AF PF CF
Output
Registers AH AL BH BL CH CL DH DL 1

C9 BA 17 A3

Output
Memory None

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 16-

ORG 100H

17. Bit subtraction using Direct Addressing mode

MOV AX, V1
MOV BX, V2 SUB
AX, BX
MOV V3, AX
HLT

V1 DW 04A5DH
V2 DW 0A231H
V3 DW 00000H

Inputs are given using vectors V1, V2 mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

4A 5D A2 31

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL ZF SF AF PF CF

A8 2C A2 31 1

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 16-

ORG 100H

Output
Memory None

18. Bit subtraction using Indirect Addressing mode

LEA SI, V1
LEA BX, V2
LEA DI, V3

MOV AX, [SI]

MOV BX, [BX]
SUB AX, BX
MOV [DI], AX
HLT

V1 DW 0EEEEH
V2 DW 01111H
V3 DW 00000H

Inputs are given using vectors V1, V2 mentioned in t

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

EE EE 11 11

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 16-

ORG 100H

AX BX CX DX ZF SF AF PF CF
Output
Registers AH AL BH BL CH CL DH DL 1 1

DD DD 11 11

Output
Memory None

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 16-
ORG 100H

19. Bit multiplication using Immediate Addressing mode

MOV AX, 0FFFFH

MOV BX, 0FFFFH
MUL BX
HLT

Inputs are given using immediate data mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

FF FF FF FF

AX BX CX DX
Output ZF SF AF PF CF
Registers AH AL BH BL CH CL DH DL
1
00 01 FF FF FF FE
DX, AX carries the result

Output
Memory None

20. Bit multiplication using Direct Addressing mode

MOV AX, V1
MOV BX, V2
MUL BX
MOV V3, DX

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 16-
ORG 100H

MOV V4, AX
HLT

V1 DW 0EEEEH
V2 DW 0EEEEH
V3 DW 00000H
V4 DW 00000H

Inputs are given using vectors V1, V2 mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

EE EE EE EE

AX BX CX DX
Output ZF SF AF PF CF
Registers AH AL BH BL CH CL DH DL
1
65 44 EE EE DE FF
DX, AX carries the result

Output
Memory None

21. Bit multiplication using Indirect Addressing mode

LEA SI, V1
LEA BX, V2
LEA DI, V3

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 16-
ORG 100H

MOV AX, [SI]

MOV BX, [BX]
MUL BX
MOV [DI], DX
INC DI
INC DI
MOV [DI], AX
HLT

V1 DW 0EEFFH
V2 DW 0EEFFH
V3 DW DUP(0)

Inputs are given using vectors V1, V2 mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

EE FF EE FF

AX BX CX DX
Output ZF SF AF PF CF
Registers AH AL BH BL CH CL DH DL
1
22 01 EE FF DF 1F
DX, AX carries the result

Output
Memory None

22. Bit division using Immediate Addressing mode

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 16-
ORG 100H

MOV AX, 0FFFFH

MOV BX, 00009H
DIV BX
HLT

Inputs are given using immediate values mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

FF FF 00 09

AX BX CX DX
Output ZF SF AF PF CF
Registers AH AL BH BL CH CL DH DL

1C 71 00 09 00 06
DX, AX carries the result

Output
Memory None

23. Bit division using Direct Addressing mode

MOV AX, V1
MOV BX, V2 DIV
BX
MOV V3, AX
MOV V4, DX
HLT

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 16-
ORG 100H

V1 DW 0EEEEH
V2 DW 00009H
V3 DW 00000H
V4 DW 00000H

Inputs are given using vectors V1, V2 mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

EE EE 00 09

AX BX CX DX
Output ZF SF AF PF CF
Registers AH AL BH BL CH CL DH DL

1A 8C 00 09 00 02
DX, AX carries the result

Output
Memory None

24. Bit division using Indirect Addressing mode

LEA SI, V1
LEA BX, V2
MOV DI, V3

MOV AX, [SI]

MOV BX, [BX]
DIV BX

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 16-
ORG 100H

MOV [DI], DX INC

DI
MOV [DI], AX
HLT

V1 DW 0FEEFH
V2 DW 00008H
V3 DW 05000H

Inputs are given using vectors V1, V2 mentioned in the program.

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

FE EF 00 08 5000

AX BX CX DX ZF SF AF PF CF

AH AL BH BL CH CL DH DL
Output
Registers DX, AX carries the result
1F DD 00 08 00 07

Output 4FFF 5000 5001 5002 5003

Memory
07 DD 1F

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 ORG 100H
25. Addition of 8-Bit array elements.

MOV CX, 05H

MOV AX, 00000H MOV
BX, 00000H MOV DI,
06000H NEXT:
ADD AL, ARRAY[BX]
JC CARRY
LOOP NEXT

CARRY:
INC AH
LOOP NEXT

MOV [DI], AX
HLT
ARRAY DB 0FFH, 0FFH, 0FFH, 0FFH, 0FFH

Inputs are given using vectors array mentioned in th

AX BX CX DX

Input
AH AL BH BL CH CL DH DL SI DI

00 00 00 00 00 05 6000

AX BX CX DX ZF SF AF PF CF
Output
Registers AH AL BH BL CH CL DH DL 1

04 FB 00 00 00 00

Output 5FFF 6000 6001 6002 6003 ….

Memory
04 FD

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 26. Check if the given value is positive, negative or zero
ORG 100H

MOV AH, 011H ; IF AH IS 11H THEN WE ASSUME POSITIVE

MOV AL, VALUE
CMP AL, 000H
JZ ZERO
ROL AL, 001H
JC NEGETIVE
JMP STOP ZERO:
MOV AH, 00H ; IF AH IS 00H THEN WE ASSUME ZERO
JMP STOP NEGETIVE:
MOV AH, 0FFH ; IF AH IS FFH THEN WE ASSUME NEGETIVE
JMP STOP STOP:
HLT
VALUE DB 84H

Inputs are given using vector “VALUE” mentioned in the program.

AX BX CX DX

Input AH AL BH BL CH CL DH DL SI DI

11 84

AX BX CX DX
Output
Registers ZF SF AF PF CF
AH AL BH BL CH CL DH DL

FF 09 1 1 1

Output
None
Memory

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 27. Addition of 8-Bit array elements.
ORG 100H
MOV CX, 05H
MOV AX, 00H
MOV BX, 04000H MOV
DI, 05500H NEXT:
ADD AL, [BX]
JC CARRY
INC BX
LOOP NEXT
JMP STOP CARRY:
INC AH
INC BX
LOOP NEXT STOP:
MOV [DI], AX
HLT

Inputs are given using to specified memory locations mentioned in the program.
AX BX CX DX

Input AH AL BH BL CH CL DH DL SI DI

00 00 40 00 00 05 5500

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL ZF SF AF PF CF

03 3D 40 05 1 1

Input Memory Output Memory

Input /
4000 4001 4002 4003 4004 …. 54FF 5500 5501 5502 5503 ….
Output
Memory
AA 91 69 FC 9D 3D 03

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 28. Addition of series 1 + 2 + 3 +…… + n (8- bit hexadecimal values)

ORG 100H
MOV AX, 0000H
MOV CX, 000FH
MOV BX, 1111H

AGAIN:
ADD AX, CX
LOOP AGAIN
MOV [BX], AX

HLT

Inputs are given using to specified register 5 terms locations mentioned in the program.
AX BX CX DX

Input AH AL BH BL CH CL DH DL SI DI

00 00 11 11 00 0F

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL ZF SF AF PF CF

00 78 11 11 00 00 1 1

Output Memory
Input /
Input Memory 1110 1111 1112 1113 1114 ….
Output
none
Memory
78

29. Printing / Generating series on memory locations ( 0, 1, 2, 3 … N)

ORG 100H

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 MOV AX, 0000H
MOV CX, 0009H
MOV BX, 1111H ; STARTING LOCATION TO PRINT SERIES

AGAIN:
MOV [BX], AX
INC AX
INC BX
LOOP AGAIN
HLT

Inputs are given using to specified register 9 terms locations mentioned in the program.
AX BX CX DX

Input AH AL BH BL CH CL DH DL SI DI

00 00 11 11 00 09

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL ZF SF AF PF CF

00 09 11 1A 00 00

Output Memory
Input /
Input Memory 1111 1112 1113 1114 1115 1116 1117 1118 1119
Output
none
Memory
00 01 02 03 04 05 06 07 08

30. Printing / Generating series on memory locations ( 0, 2, 4, 6 … UPTO

N TERMS)

ORG 100H
MOV AX, 0000H

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 MOV CX, 0009H
MOV BX, 1111H ; STARTING LOCATION TO PRINT SERIES

AGAIN:
MOV [BX], AX
INC AX
INC AX
INC BX
LOOP AGAIN
HLT

Inputs are given using to specified register 9 terms locations me

AX BX CX DX

Input AH AL BH BL CH CL DH DL SI DI

00 00 11 11 00 09

AX BX CX DX ZF SF AF PF CF
Output
Registers AH AL BH BL CH CL DH DL

00 09 11 1A 00 00

Output Me
Input /
1111 1112 1113 1114 1115 1116 1117 1118 1119
Output Input Memory none
Memory
00 02 04 06 08 0A 0C 0E 10

31. Finding Largest value from array

ORG 100H
MOV CX, 00009H
MOV SI, 02000H
MOV DI, 03000H
MOV AL, 00H

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 LOOP: CMP AL, [SI]
JC SWAP
INC SI
DEC CX
JNZ LOOP
JMP STOP
SWAP: MOV AL, [SI]
INC SI
DEC CX
JNZ LOOP
STOP: MOV [DI], AL
HLT

Inputs are given using to SI register 10 terms locations mentioned in the program.
AX BX CX DX

Input AH AL BH BL CH CL DH DL SI DI

00 00 09 2000 3000

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL ZF SF AF PF CF

09 00 00 1 1

Input Memory Output Memory

Input /
2000 2001 2002 2003 2004 2005 2006 2007 2008 2FFF 3000 3001
Output
Memory
21 02 AE 06 08 AA BC 9E 9D BC

32. Finding Smallest value from array

ORG 100H
MOV CX, 0000AH
MOV SI, 02000H
MOV DI, 03000H
MOV AL, 0FFH ; ASSUMING THE SMALLEST IS ‘FFH’

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 LOOP: CMP AL, [SI]
JNC SWAP ; THIS INSTRUCTION IS THE ONLY DIFFERENCE
INC SI
DEC CX
JNZ LOOP
JMP STOP
SWAP: MOV AL, [SI]
INC SI
DEC CX
JNZ LOOP
STOP: MOV [DI], AL
HLT

Inputs are given using to SI register 10 terms locations mentioned in the program.
AX BX CX DX

Input AH AL BH BL CH CL DH DL SI DI

00 00 09 2000 3000

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL ZF SF AF PF CF

09 00 00 1 1

Input Memory Output Memory

Input /
2000 2001 2002 2003 2004 2005 2006 2007 2008 2FFF 3000 3001
Output
Memory
21 02 AE 06 08 AA BC 9E 9D 02

33. Block Move (Moving a block of data from one location to another)
ORG 100H
MOV CX, 00005H
MOV SI, 02000H
MOV DI, 03000H

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 LOOP:
MOV AL, [SI]
MOV [DI], AL
INC SI
INC DI
DEC CX
JNZ LOOP

HLT

Inputs are given using to SI register 5 VALUES mentioned in the memory.

AX BX CX DX

Input AH AL BH BL CH CL DH DL SI DI

00 05 2000 3000

AX BX CX DX
Output
Registers AH AL BH BL CH CL DH DL ZF SF AF PF CF

EE 00 00 1 1

Input Memory Output Memory

Input /
2000 2001 2002 2003 2004 3000 3001 3002 3003 3004
Output
Memory
AA BB CC DD EE AA BB CC DD EE

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