Professional Documents
Culture Documents
Datasheet For Irfp240
Datasheet For Irfp240
Packaging
JEDEC STYLE TO-247
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
4-317 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
IRFP240
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
S
Junction to Case RθJC - - 0.83 oC/W
4-318
IRFP240
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 18A, VGS = 0V (Figure 13) - - 2.0 V
Reverse Recovery Time trr TJ = 25oC, ISD = 18A, dISD/dt = 100A/µs 120 250 530 ns
Reverse Recovered Charge QRR TJ = 25oC, ISD = 18A, dISD/dt = 100A/µs 1.3 2.6 5.6 µC
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 50V, starting TJ = 25oC, L = 1.9mH, RGS = 50Ω, peak IAS = 20A.
1.2 20
POWER DISSIPATION MULTIPLIER
1.0
16
ID, DRAIN CURRENT (A)
0.8
12
0.6
8
0.4
4
0.2
0 0
0 50 100 150 25 50 75 100 125 150
TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE
1
ZθJC, NORMALIZED TRANSIENT
0.5
THERMAL IMPEDANCE
0.2
0.1 0.1
0.05
PDM
0.02
0.01
10-2 t1
SINGLE PULSE
t2 t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
10-3 -5
10 10-4 10-3 10-2 0.1 1 10
t1, RECTANGULAR PULSE DURATION (s)
4-319
IRFP240
1000 30
OPERATION IN THIS VGS = 8V PULSE DURATION = 80µs
REGION IS LIMITED DUTY CYCLE = 0.5% MAX
BY rDS(ON) VGS = 10V VGS = 7V
24
100 10µs
18
100µs
10
1ms VGS = 6V
12
10ms
1
DC 6
TC = 25oC
TJ = MAX RATED VGS = 5V
SINGLE PULSE VGS = 4V
0.1 0
1 10 102 103 0 20 40 60 80 100
VDS , DRAIN TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)
30
PULSE DURATION = 80µs 100
VGS = 10V PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX VGS = 8V DUTY CYCLE = 0.5% MAX
24 VDS ≥ 50V
VGS = 7V
ID , DRAIN CURRENT (A)
10
18
12
VGS = 6V TJ = 150oC TJ = 25oC
1
6
VGS = 5V
VGS = 4V
0 0.1
0 1 2 3 4 5 0 2 4 6 8 10
VDS , DRAIN TO SOURCE VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V)
3.0
1.5 PULSE DURATION = 80µs
PULSE DURATION = 2µs DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
1.2
ON RESISTANCE
ON RESISTANCE (Ω)
1.8
0.9
VGS = 10V
1.2
0.6
0.6
0.3
VGS = 20V
0
0 -60 -40 -20 0 20 40 60 80 100 120 140 160
0 15 30 45 60 75
TJ, JUNCTION TEMPERATURE (oC)
ID , DRAIN CURRENT (A)
NOTE: Heating effect of 2µs pulse is minimal. FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE GATE RESISTANCE vs JUNCTION TEMPERATURE
VOLTAGE AND DRAIN CURRENT
4-320
IRFP240
1.25 3000
ID = 250µA VGS = 0V, f = 1MHz
NORMALIZED DRAIN TO SOURCE
C, CAPACITANCE (pF)
BREAKDOWN
0.75 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 1 2 5 10 20 50 100
TJ , JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE
15 100
PULSE DURATION = 80µs
PULSE DURATION = 80µs
ISD , SOURCE TO DRAIN CURRENT (A)
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
gfs , TRANSCONDUCTANCE (S)
12
TJ = 25oC
10
9
TJ = 150oC
6 TJ = 150oC
1
3
TJ = 25oC
0 0.1
0 6 12 18 24 30 0 0.4 0.8 1.2 1.6 2.0
ID , DRAIN CURRENT (A) VSD , SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
ID = 18A
VGS , GATE TO SOURCE VOLTAGE (V)
16
VDS = 40V
12
VDS = 100V
VDS = 160V
8
0
0 12 24 36 48 60
Qg, GATE CHARGE (nC)
4-321
IRFP240
tP
L VDS
IAS
VARY tP TO OBTAIN VDD
+
REQUIRED PEAK IAS RG
VDD
VGS -
DUT
tP
0V IAS 0
0.01Ω tAV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
tON tOFF
td(ON) td(OFF)
tr tf
VDS
RL 90% 90%
+
10% 10%
VDD 0
RG
-
90%
DUT
VGS 50% 50%
PULSE WIDTH
10%
0
VGS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
VDS
CURRENT (ISOLATED
REGULATOR SUPPLY) VDD
Qg(TOT)
VGS
SAME TYPE
Qgd
12V AS DUT
0.2µF 50kΩ Qgs
BATTERY
0.3µF
D VDS
G DUT 0
IG(REF) S IG(REF)
0
VDS
IG CURRENT ID CURRENT
SAMPLING SAMPLING 0
RESISTOR RESISTOR
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
4-322
IRFP240
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-323