A Digitally Controlled Adaptive LDO for Power

Management Unit in Sensor Node 8

Linear

J. Sarma, S. Chatterjee, R. Biswas and S. Roy 7 Exponential

Number of comparators
6
Power management unit (PMU) is the core of the sensor node
SoC to achieve high performance in WBAN. This Letter presents a
digitally controlled low dropout regulator (LDO) targeted for the power 5
management unit (PMU) in a sensor node. A flash-based approach,
substituting the classical error amplifier with an array of dynamic 4
comparators, is employed in order to achieve fast transient response. In
addition, during the load transient, the proposed LDO effectively detects 3
the voltage droop and generates a set of digital control signals to activate
a specific PMOS array for coarse and fine-tuning. The proposed LDO is 2
capable of handling the load step of 10 µA to 1 mA with voltage droop of
290 mV. The LDO is implemented with 180 nm CMOS technology node, 1
producing a regulated output of 0.9 V for input voltage ranges from 1.1 V- 0 0.2 0.4 0.6 0.8 V
ref
1 1.2 1.4 1.6 V =1.8
dd
1.8 V. The current efficiency at 1 mA load current is 99.4%, with settling
time to recover the voltage droop is 80 ns at 50 MHz clock frequency.
Range of voltage droop (V)

Fig. 2 Exponential and linear variation of threshold voltages with required

Introduction: In recent times, wearable sensor nodes show significant number of comparators
improvement due to the integration of low powered circuits. In general,
these sensor nodes are powered from a battery that has very restricted
capacity to drive the sensor node over a longer time period [1]. The
divide the entire voltage range into the respective threshold voltages. The
power management unit (PMU) in sensor nodes plays a crucial part
exponential variation of threshold voltages in the proposed architecture
in increasing the load driving capacity, providing regulated voltage to
holds the advantage over classical flash architecture in maintaining the
different modules within a single chip, incorporating multiple voltage rails.
same dynamic detection range with reduced number of comparators. It
LDOs are preferred and integrated into PMU for providing the regulated
permits the range of droop detection to divide into a coarse tuning and fine
voltages due to its ability to handle noise sensitivity [2]. However, the input
tuning zone. For a resolution of 0.05 V, the linear and exponential variation
voltages in classical analog LDOs are very high with large off-chip load
of threshold voltages around Vref = VDD 2
, can be expressed with Equ. 1
capacitor, making it unsuitable for low voltage application specifically in
and Equ. 2 respectively.
the sensor node. Digital LDOs which has the advantage process scalability
are preferred in sensor node SoC as different functional units of sensor
node operate in the near-threshold region or the sub-threshold region[3]. VDD
y1 = ± 0.05 × Vdd × n1 (1)
Conventional DLDO [4] utilizes a dynamic comparator to compensate the 2
voltage overshoot/ undershoot by triggering an array of PMOS through
a bidirectional shift register. However, with a one-bit control scheme VDD
y2 = ± 0.05 × Vdd × 2n2 (2)
and identically sized PMOS array, it is difficult to achieve fast transient 2
response by a conventional DLDO throughout the admissible load step. In ,where y1 and y2 are the range of threshold voltages covered by ‘n1’ and
order to boost the response time, hybrid LDO i.e. both analog LDO and ‘n2’ number of comparators respectively.
DLDO are coupled together [3]. However, simultaneous control loop for However, to keep same dynamic range of threshold voltages, from Equ. 1
both degrades the performance of analog LDO. Therefore, the expected and Equ. 2, we get
transient response comes with a highly complex design. It is essential
to ensure a fast transient response in the sensor node as load transient y1 = y2
jumps from µA to mA frequently [5]. This transition of load occurs due VDD VDD
to transceiver, the most power-hungry unit of a sensor node, which is duty- ⇒ ± 0.05 × Vdd × n1 = ± 0.05 × Vdd × 2n2
2 2
cycled based on events triggered from Digital Signal Processor (DSP) to
minimize the overall sensor node power consumption [5]. In this Letter, ⇒ n2 = 3.322 × log10 n1 (3)
a digitally controlled LDO for battery-powered sensor node is presented
targeting load transition from µA to mA primarily due to transceiver. For Equ. 3 illustrates the relationship between the number of comparators
fast transient response, it incorporates a modified flash-based architecture corresponding to the linear and exponential variation of threshold voltages
that acts as a wide range of voltage droop detector during different load to maintain a specific dynamic voltage range. It depicts that the proposed
transient steps. Digital control signals are generated based on the respective architecture having exponential variation of threshold voltages can hold
range of voltage droop to trigger a specifically weighted PMOS array. The the same dynamic range with less number of comparators. Fig. 2 shows
distribution of weights for a specific PMOS array is arranged considering the comparison between the two types of variation i.e. exponential
a coarse and fine-tuning approach. The proposed LDO achieves a faster and linear increment/decrement around Vref , illustrating the number of
response within a fewer clock cycle as it can take a decision from digital comparators required in each case for a specific range of voltage droop.
control signals, switching on/off only the required PMOS array. The corresponding threshold voltages evaluated using Equ. 2 are shown in
Fig. 3 depicting the fine tuning and coarse tuning zone.
Architecture and operation of the proposed LDO: The schematic of
the proposed digitally controlled LDO is shown in Fig. 1. Generally,
conventional DLDO [4] utilizes a dynamic comparator for detection of
load transient. Referring to Fig. 1, the proposed architecture reshapes the Fine tuning
conventional DLDO, substituting the dynamic comparator with a series zone
Coarse tuning zone Coarse tuning zone
Vdd

of dynamic comparators. This modification upgrades the conventional

0

DLDO architecture by increasing the dynamic range of voltage droop

detection from 0 to Vdd . This array of comparators sense the region
of voltage droop in addition to the error detection as depicted in Fig.
Vth3=0.72V
Vref=Vth4=0.9V
Vth6=1.62V

Vth5=1.08V
Vth6=1.26V

Vth2=0.54V

Vth1=0.18V

2, thus enabling the architecture to achieve fast transient response by

supplying current based on the region of voltage droop. The architecture
aided an exponential variation of threshold voltages from Vth1 to Vth7
around the desired reference voltage, Vref = V2dd , covering wide dynamic
detection range (0 to Vdd). A resistive ladder supports the architecture to

Fig. 3. Coarse and fine tuning zone with different threshold voltages

ELECTRONICS LETTERS 12th December 2011 Vol. 00 No. 00

 1 0

Vdd
Digital Coarse
control Control Driving Tuned
block logic
R1
Vth7 +
block
I1
C7 I2 <M8:M1>
‒ I3 VIN
Exponentially I4 Fine
increase Coarse tuning zone
Clk IN Fine tuning zone Tuned
Digital Control IN
+ D1 D2 D7 D8 D2 D7
Vref=0.9 V control D1 D8
C4
‒ signal VIN
generator M1 M2 M7 M8
Exponentially N1 N2 N7 N8 <N8:N1>
decrease Clk D1 Array 1 Array 2 Array 3 Array 4
D2
+ D3
Vth1 C1 D4
‒ IL1 IL2
R8

Clk
ClkIN (i) Vout

RL CL

Fig. 1. Schematic of the proposed digitally controlled LDO

These voltages, represented by Vthk , where k=1, 2,.......7 are supplied when any one of the control signal from pair (Ii, Di), i∈ 1,2,3,4 is high. For
through a resistive ladder as shown in Fig. 1. In the coarse tuning zone, a particular array when ‘Clkin i’ is activated, ‘IN’ signal carrying logic
more current are forced through an array of D flip-flops compared to fine ‘1’ or ‘0’ drives the corresponding PMOSs turning it on or off through D
tuning zone to achieve fast transient response. The change in Vout during flip-flops. The logic of ‘IN’ signal, i.e. whether it is high or low depends
load change due to the association of transceiver is sensed through the whether current Vout value is above or below Vref . Four sets of PMOSs
dynamic comparator array resulting in generation of thermometric code, are utilized corresponding to four control signal pairs (Ip, Dp) including
C1, C2,.......,C7. The digital control block shown in Fig. 1 produces digital coarse and fine tuning zone. Each set consist of 8 PMOSs, specifically
weighted, accommodating the requirement of IL in coarse and fine tuning.
Table 1: Digital control signal corresponding to thermometric code The 8 PMOSs for 3 arrays in coarse tuned zone are weighted in the ratios
k× < 20 : 27 >, where ‘k’ represents the array number whereas each of
Range of output Thermometric code Digital control the 8 PMOSs for array 4 are linearly weighted. Fig. 5 demonstrates the
voltage, Vout (V) C7 C6 C5 C4 C3 C2 C1 signals, control timing diagram depicting a sample coarse and fine tuning operation with
Vout˃1.62 1 1 1 1 1 1 1 D1=C7 respect to input clock, ‘Clk’. Immediately after a transient occurs, voltage
1.62 ˂Vout ˂ 1.26 0 1 1 1 1 1 1 D2= C7⊕C6 undershoot or overshoot takes place shifting Vout from Vref as shown
1.26 ˂Vout ˂1.08 0 0 1 1 1 1 1 D3= C6⊕C5 in Fig. 5. Assuming Vout drops to 0.6 V from the initial state due to
1.08 ˂Vout ˂ 0.9 0 0 0 1 1 1 1 D4= C5⊕C4 sudden increase in IL , the digital control block will set control signal ‘I3’
0.9 ˂Vout ˂ 0.72 0 0 0 0 1 1 1 I4= C4⊕C3 to logic ‘1’ activating the clock, ClkIN 3 for array 3. Array 3 will trigger
0.72 ˂Vout ˂ 0.54 0 0 0 0 0 1 1 I3= C3⊕C2 its corresponding 8 PMOSs shifting Vout to fine tuning zone near Vref .
0.54 ˂Vout ˂ 0.18 0 0 0 0 0 0 1 I2=C2⊕C1 In this region, control signal ‘D4’ runs clock, ClkIN 4, adjusting Vout to
Vout ˂0.18 0 0 0 0 0 0 0 I1=𝑪𝟏
settle down around Vref .

Array 3 Array 4
1V
control signal corresponding to each thermometric code which eventually
Vref
depends on the zone of Vout . Table 1 illustrates different digital control Vout
signals, ‘control’ generated for a specific thermometric code with its 0.6V
combinational logic. The logic value i.e.‘1’ or ‘0’ is fetched through a 2:1
mux based on ‘control’. Four arrays i.e. array1, array2, array3 and array4
ClkIN 4
are employed to trigger a specifically weighted PMOS array selected by a
control signal pair (Ip, Dp), where ‘p’ represents the array number. Thus,
‘IN’ signal produced from the mux is used by the driving logic block to
D4
trigger one of the arrays. Array1, array2 and array3 represents the coarse
tuning zone while array4 represent fine tuning zone representing Vout near
Vref . In Fig. 1, one array representing The schematic of the driving logic
ClkIN 3
block is given in Fig. 4. The clock of each array, ‘ClkIN i’ is activated only

OUTi I3

Clk
1
INi
Mi D1 Q1 D2 Q2 D7 Q7 D8 Q8
0 Fig. 5. Coarse and fine tuning zone with different threshold voltages

Ii
Arrayi
Results and performance evaluation: The proposed digitally controlled
Clk
ClkIN(i) LDO is implemented in 180 nm CMOS process. With the exponential
flash-based architecture, the proposed LDO provide a regulated output
Di
voltage, Vout of 0.9 V for different input voltage variation ranging from
1.1 V to 1.8 V. The quiescent current measured is found to be 6 µA with
a sampling clock frequency of 50 MHz. Thus, the peak current efficiency
Fig. 4. Clock gating with digital control signal at 1 mA is measured to be 99.4%. The designed LDO adopts a maximum

2
and minimum load current of 1 mA and 10 µA respectively, where load 1
current changes in 100 ps edge time. The capability of the proposed LDO
to achieve a regulated voltage is demonstrated with transient response 0.9

Vout (V)
profile in Fig. 6 incorporating load change from 10 µA to 1 mA at input VIN=1.1 V
0.8
voltage, Vin = 1.8 V. For better illustration of voltage undershoot during VIN=1.3 V
load change, the zoom-in view of the transient plot in Fig. 6 annotated with 0.7 VIN=1.5 V
blue circle is shown in Fig. 7.
0.6
0 250 350 450 550 650 750 850
1.5 Time (ns)
Voltage (V)

1
1.2

IL (mA)
0.5
50 170 290 410 530 650 770 890 1010 1130 1250
Time (ns) 0.6
1.2
IL(mA)

0.6 0.01
0 250 350 450 550 650 750 850
0.01 Time (ns)
50 170 290 410 530 650 770 890 1010 1130 1250
Time (ns) Fig. 8. Coarse and fine tuning zone with different threshold voltages
2
Voltage (V)

1
E-mail: jitusarma18@yahoo.com
0
References
50 170 290 410 530 650 770 890 1010 1130 1250
Time (ns) 1 Chen, F., Lu, Y. and Mok, P. K. T. : ‘Fast-Transient 500-mA Digitally
Assisted Analog LDO With 30-µ V/mA Load Regulation and 0.0073-ps
Fig. 6. Coarse and fine tuning zone with different threshold voltages FoM in 65-nm CMOS’, IEEE Journal of Solid-State Circuits, in Early
Access
2 Liu, C. W. and Chang-Chien, L. : ‘Area Efficient High Performance
Digitally Controlled Power Management Unit’, IEEE Trans. on Industrial
Electronics, in Early Access
3 Zhang, Y., Song, H., et al. : ‘A Capacitor-Less Ripple-Less Hybrid LDO
Vout (V)

1
80 ns With Exponential Ratio Array and 4000x Load Current Range’, IEEE Trans.
290 Circuits Syst. II,, 2019, 66, (1), pp. 36-40
mV 4 Okuma, Y., et al. : ‘0.5-V input digital LDO with 98.7% current efficiency
0.5 and 2.7-ÂţA quiescent current in 65nm CMOS’, IEEE Custom Integrated
290 Time (ns) 410 Circuits Conference, Sapporo, San Jose, CA, 2010, pp. 1-4
5 Gweon, S., Lee, J., Kim, K. and Yoo, H.: ‘93.8% Current Efficiency and
1.2 0.672 ns Transient Response Reconfigurable LDO for Wireless Sensor
1 mA
IL(mA)

Network Systems’, IEEE Int. Symp. on Circuits and Systems, Sapporo,

0.6 Japan, 2019, pp. 1-5
0.01
10 7A
290 410
Time (ns)

Fig. 7. Coarse and fine tuning zone with different threshold voltages

It shows that the voltage undershoot and overshoot measured during

load change is measured to be 290 mV and 180 mV respectively. From Fig.
6, the measured load regulation of the LDO is 0.08 V/mA. A comparative
transient waveforms corresponding to different VIN values are given in
Fig. 8. The small relative variation of Vout for different VIN variation
demonstrates that the proposed regulator settles down to the regulated
voltage despite changes in input voltage. The digital control in addition
to coarse and fine tuning capability suggest that the proposed LDO can
incorporate load transient in sensor node, boosting the transient response
irrespective of voltage droop.

Conclusion: A digitally controlled LDO with an exponential flash-based

technique for boosting transient performance in sensor node has been
proposed and implemented in 180 nm CMOS process. The proposed LDO
accommodates load transient from 10 µA to 1 mA with voltage undershoot
and overshoot of 290 mV and 180 mV respectively, making it suitable to
integrate into PMU of a sensor node. The flash architecture with digital
control enables fast computation extending a wide load current range
merging coarse and fine-tuning. The architecture achieves settling time of
80 ns along with 99.4% peak current efficiency. The evaluated result shows
the efficacy of the proposed architecture to achieve a regulated voltage of
0.9 V with fast settling time regardless of the voltage droop.

J. Sarma, S, Chatterjee, R. Biswas and S. Roy Other (Indian Institute of

Information Technology, Guwahati, Assam, India)