CS/EEE/INSTR F 215 Digital Design SEM-I (2020-21)

Topics mark in bold RED have been excluded from the syllabus for comprehensive
examination of Sem-1 (2020-21).

Module Lecture Session Reference Learning outcomes

No.
1 Digital Systems, Digital ICs 1.1; 1.9; 2.9, Introduction to Digital Systems and
10.1,2 Characteristics of Digital ICs.
2-4 Binary codes, K-Maps (4,5 1.7; 2.6; 3.1 Different representation of Digital
variables), QM Method to 3.8 functions and simplification techniques
5-8 Adders, Subtracters, 4.1 - 4-7, R2 Design of Combinational Logic Circuit
Multipliers, Booth Multiplier such as Arithmetic circuits.
9 Hardware Description 3.11 Simulation and synthesis basics using
Languages HDL
10-12 Flip-Flops & Characteristic 5.1 to 5.4 Sequential Logic
tables, Latches.
13-16 TTL, MOS Logic families and 10.3, 10.5, Digital Integrated Circuits
their characteristics 10.7 to 10.9
17-20 Comparators, Decoders, 4.8 to 4.11 MSI Components
Encoders, MUXs, DEMUXs
21 HDL for Combinational Logic 4.12 Simulation of Combinational Logic
Functions.
22-25 Analysis of clocked sequential 5.5, 5.7 Clocked Sequential Circuits
circuits, state diagram and
reduction
26 HDL for Sequential Logic 5.6 Simulation of Sequential Logic
Functions.
27-29 ROM, PLA, PAL 7.1, 7.5 to Memory and PLDs
7.7
30-32 Shift registers, Synchronous & 6.1 to 6.5 Registers & Counters
Asynchronous counters, clock
skew & Clock Jitter
33-35 Algorithmic State Machines R1. Chapter Design of Digital Systems
8
36 Memory Hierarchy R2 Memory Organization
37-40 RTL, HDL description 8.1,8.2, 8.4 Modular approach for CPU Design
to 8.8

Topics mark in bold RED have been eliminated from the syllabus for comprehensive
examination of Sem-1 (2020-21).