Training on


IP & SoC Functional Verification Methodology

Using UVM

LAB3

Scoreboarding

BARRIGA Ponce de Leon Ricardo

GUO Ran
GSE5 TP Verification Circuit BARRIGA_GUO

Objectives:
The goal of this lab is to implement a scoreboard checking mechanism between the register
interface of the UART and the external serial interface of the UART on the TX line.
• Understanding how the scoreboard is connected to multiple monitors
• Understanding data checking mechanisms.

Introduction:
The design under test (DUT) is a UART 16550 from opencores.org.
In this lab we will implement a scoreboard between the APB Register programming interface of
the UART and the Tx data that are actually sent by the DUT. 


Work in the session:

Step 1: Implement a simple assertion to check the protocol
We write an assertion which will check that “after reset, PSEL is 0” in the file platform/
aedvices/uart_tb/uart_ip_tb.sv.

We write an assertion than checks that:

A first cycle of “PSEL” == 1, is followed by PENABLE == 1.

Step 2: Connect the scoreboard

✦ Declare the input analysis port extensions.

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GSE5 TP Verification Circuit BARRIGA_GUO

✦ Add the input analysis port members to the lab_scoreboard class:

✦ Create the 2 associated instances

✦ Connect the scoreboard to the VIP monitors

We need to connect a scoreboard or a reference model when we do the verification, to
realise it we can use UVM Analysis ports.
We connect the monitor with scoreboard in the class lab_test.

Get the instance of the analysis port connect

✦ Add breakpoints to write_apb() .

We add breakpoints before the function do_nothing() which is called by write_apb().

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✦ Recompile and Rerun
Here is our result:

with break point without break point

If we add the break point before do_nothing, we can see the simulation will break in
function do_nothing. Here is the simulation information in console

Step 3: Implement the TX scoreboard

✦ In write_apb:
Set the variable “scoreboard_enable” to 0 when there is a write access to address ==
`UART_LCR with data[7:7] == 1
Set the variable “scoreboard_enable” to 1 when there is a write access to address ==
`UART_LCR with data[7:7] == 0

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✦ Push the transaction data to the queue “tx_scoreboard” when:
• The scoreboard is enable
• There is a write transaction to address 0x00

At first we create a new class which named mytrans, who inherit uvm_transaction, it has
address which is 32 bits and also data 32 bits.
Then we create the class mytrans_queue which inherit uvm_object, it created a table queue
for putting the transactions.

Then in the function write_apb, we add the code for storing the transactions. It begins to
store the data when scoreboard_enable==1.

✦ In write_tx_frame:
Check the previously pushed data is matching the one you are receiving. o
Check the first element of the queue is the received packets, else issue a UVM_ERROR
using the macro: `uvm_error("MESSAGE_ID","SOME ERROR MESSAGE")

Here is our code in write_tx_frame, at first we check whether the queue is empty, if not, we
begin our checking of the coherence of the data by using assert.

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Then we recompile our program and rerun it, here is the result:

Conclusion:
In this lab, we know how to use the assertions, we understand well how scoreboard checking works,
including implementing a scoreboard and connecting a scoreboard with the multiple monitors.
Before we do the checking, we could record data into queues or list. Then we verify the coherence
of the datas one by one. During this lab, it deepened our understanding of data checking
mechanisms.