Pal VAWGA-VAWGB LA-9911P Rev 1 0 Schematics PDF

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1 1
Compal Confidential
VAWGA/B Schematics Document
2 2
AMD "Kabini" Platform

AMD 25W APU With Jaguar Core and Integrated Yangtze FCH + ATI Sun
LA-9911P REV: 1.0

3 2013-04-01 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/04/22 Deciphered Date 2015/04/22 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
COVER PAGE
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
VAWGA/GB
Date: Monday, April 01, 2013 Sheet 1 of 48
A B C D E
A B C D E
Compal Confidential
Model Name : VAWGA/B
1 1
VRAM 1G/2G
256M16 x 4 (2G)
128M16 x 4 (1G) P.16~19
AMD Kabini Memory BUS(DDR3)
DDR3 204pin DDRIII-SO-DIMM X2
Single Channel BANK 0, 1, 2 P.8~P.9
AMD Sun Pro M2
PCIe x 4 Gen2 1.5V DDRIII 1600MHz
GFX
VRAM 1GB/2GB
DDR3 x4 page 10~15
LVDS Conn. P21 DP0

CMOS P.21 WLAN P.26 Card P.30 Touch P.26 S/B P.27
HDMI Conn. P20 DP1 Camera BT Combo Reader Screen 2.0 Conn.
AMD FT3 APU Port 3 Port 5 Port 4 Port 1 Port 0
CRT Conn. P22 DAC
2
GPP Jaguar Core USB USB2.0 2
Port 8 Port 9
GPP2 GPP1
Integrated Yangtze FCH
LAN MB P.27 MB P.27
MINI Card
Atheros BGA 769-balls 3.0 Conn. LP1 3.0 Conn. LP2
(WLAN/BT)
P26 AR8162/8172
P24 Port 0 Port 1
USB
Transformer USB3.0
RJ45 HDA HD Audio
P25
BIOS (4M) SPI
P.5 SATA
LPC Gen3 Port 0 Port 1

Int.KBD P.30 ENE
Audio
KBC9012 HDD ODD
P.28 Conexant
Conn. Conn.
P.23 P.23 CX20757
PS2 P.31
3
P.4~P.7 3
Touch Pad Thermal Sensor

P.30 P.29
Int. MIC Int. Speaker Conn. Audio Combo Jacks

page 31 page 31
HP & MIC
page 31
Sub-borad
15"
14"
IO/B ODD/B
LS9633P LS9634P
page 30 page 23
4 Power/B LED/B 4
LS9631P LS9635P
page 30 page 30
USB/B Security Classification Compal Secret Data Compal Electronics, Inc.

LS9632P
page 27 BLOCK DIAGRAMS
Size
Document Number Rev
B 1.0
VAWGA/GB
Date: Thursday, March 28, 2013 Sheet 2 of 48
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A B C D E
Voltage Rails BOARD ID Table

Board ID PCB Revision SIGNAL
STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
Power Plane Description S0 S3 S5 0 MP
VIN Adapter power supply (19V) ON ON ON 1 PVT Full ON HIGH HIGH ON ON ON ON
B+ AC or battery power rail for power circuit. ON ON ON 2 DVT S1(Power On Suspend) HIGH HIGH ON ON ON LOW
+APU_CORE Core voltage for APU ON OFF OFF 3 EVT
1
+APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF 4 S3 (Suspend to RAM) HIGH HIGH ON ON OFF OFF 1
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF 5 S4 (Suspend to Disk) LOW HIGH ON OFF OFF OFF
+VDDCI 0.95-1.2V switched power rail ON OFF OFF 6
+3VALW 3.3V always on power rail ON ON OFF 7 S5 (Soft OFF) LOW LOW ON OFF OFF OFF
+3VS 3.3V switched power rail ON OFF OFF
+1.8VALW 1.8V always on power rail ON ON ON* Board ID / SKU ID Table for AD channel USB OC MAPPING
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
OC# USB Port
+0.95VALW 0.95V always on power rail ON OFF OFF R1562 100K +/- 5%
+0.95VS 0.95V switched power rail ON OFF OFF Board ID R1564 V AD_BID min V AD_BID typ V AD_BID max 0 USB20 port0
+1.5V 1.5V power rail for APU and DDR ON ON OFF 0 0 0 V 0 V 0 V 1 USB20 port1,2,8,9 USB30 port0,1
+1.5VS 1.5V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 2
+3VGS 3.3V switched power rail for VGA ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V 3
+1.8VGS 1.8V switched power rail for VGA ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+1.5VGS 1.5V switched power rail for VGA ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V BOM Structure Table
+0.95VGS 0.95V switched power rail for VGA ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
BOM Structure BTO Item
+5VALW 5V always on power rail ON ON ON 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
2
+5VS 5V switched power rail ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V 2
A6@ A6 R3 BGA APU
+VSB VSB always on power rail ON ON ON
A4@ A4 R3 BGA APU
+RTC_APU RTC power ON ON ON
E2@ E2 R3 BGA APU
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF
E1@ E1 R3 BGA APU
E1PC@ E1 PC BGA APU
SMBUS Control Table
X4@ X4 ES2 BGA APU
Thermal
SODIMM WLAN Sensor FCH X5@ X5 ES2 BGA APU
SOURCE VGA BATT KB9012 WWAN APU RTD2132 APU PCIE PORT LIST X2@ X2 ES2 BGA APU
SMB_EC_CK1
SMB_EC_DA1 KB9012
+3VALW
X V
+3VALW
X X X X X X X Port Device EMICU@
EMICP@
CardReader EMI Un pop
CardReadear EMI pop
0 EMIUSB2RU@ Right USB2.0 port EMI un pop
1 LAN
EMIUSB2RP@ Right USB2.0 port EMI pop
X X X V V X X X X
APU_SCLK0 2 WLAN
USB2R@ Right USB2.0 port component
APU 3
APU_SDATA0 +3VS +3VS +3VS SUN@ SUN PRO GPU (R3 compal part)
V X X X X V V
MARS@ MARS XT GPU (R1 compal part)
SMB_EC_CK2
3
SMB_EC_DA2
KB9012
+3VS +3VS +3VS
X +3VS
X 14@
15@
for 14" componect
for 15" componect 3
PX@ Common VGA circuit

CMOS@ CMOS Camera part
HDMI@ HDMI part
USB Port Table
EMIGASP@ Gastube
3 External 8162@ Ateros AR8162 LAN Chip
EC SM Bus1 address EC SM Bus2 address USB 2.0 USB 3.0 Port USB Port 8172@ Ateros AR8172 LAN Chip
Device Address HEX Device Address HEX 0 RIGHT USB SWR@ LAN Switching mode
Smart Battery 0001 011X b 16H Thermal Sensor 1001 101X b 9AH 1 Touch Screen LDO@ LAN LDO mode
SB-TSI (APU) 1001 100X b 98H 2 THERMAL@ Lenovo Thermal Sensor
3 Camera ME@ ME part
VGA Internal Thermal 1000 001X b 82H 4 CardReader UMA@ UMA part
5 WLAN/BT Combo @ Unpop
6 LEFT USB (for colay) ZODD@ Zero Power ODD part
7 LEFT USB (for colay) TS@ Touch Screen
APU
0 8 LEFT USB3.0 EMIP@ EMI pop component
4 SM Bus address XHCI
1 9 LEFT USB3.0 EMIU@ EMI Un pop component 4
Device Address HEX ESDP@ ESD pop component

DDR DIMM1 1010 000Xb A0H ESDU@ ESD Un pop component
DDR DIMM2 1010 001Xb A2H
NOTES LIST
Size
Document Number Rev
B 1.0
VAWGA/GB
A B C D E
A B C D E
UAPUA HDMI & LVDS should be reverse in KABINI:

<8,9> DDRAB_SMA[15..0] DDRAB_SDQ[63..0] <8,9>
DDRAB_SMA0 AG38
MEMORY
B30 DDRAB_SDQ0
APU TX0 to Connector TX2 ; APU TX1 to Connector TX1 UAPUC
M_ADD0 M_DATA0
DDRAB_SMA1 W35 M_ADD1 M_DATA1 A32 DDRAB_SDQ1 APU TX2 to Connector TX0 ; APU TX3 to Connector CLK DISPLAY/SVI2/JTAG/TEST
DDRAB_SMA2 W38 M_ADD2 M_DATA2 B35 DDRAB_SDQ2 A9 TDP1_TXP0 DP_150_ZVSS B16 DP_150_ZVSS
<20> DP2_TXP0
DDRAB_SMA3 W34 M_ADD3 M_DATA3 A36 DDRAB_SDQ3 <20>
B9 TDP1_TXN0 DP_2K_ZVSS A21 DP_2K_ZVSS R400 1 2 2K_0402_1%
DDRAB_SMA4 U38 B29 DDRAB_SDQ4 DP2_TXN0 B17
M_ADD4 M_DATA4 DP_BLON
ENBKL <28>
DDRAB_SMA5 U37 M_ADD5 M_DATA5 A30 DDRAB_SDQ5 A10 TDP1_TXP1 DP_DIGON A17
<20> DP2_TXP1 APU_ENVDD <21>
DDRAB_SMA6 U34 M_ADD6 M_DATA6 A34 DDRAB_SDQ6 B10 TDP1_TXN1 DP_VARY_BL A18
<20> DP2_TXN1 APU_INVT_PWM <21>
DDRAB_SMA7 R35 M_ADD7 M_DATA7 B34 DDRAB_SDQ7 HDMI
DDRAB_SMA8 R38 M_ADD8
<20>
A11 TDP1_TXP2
DDRAB_SMA9 N38 B37 DDRAB_SDQ8 DP2_TXP2 B11 D17
M_ADD9 M_DATA8 TDP1_TXN2 TDP1_AUXP
<20> DP2_TXN2 HDMI_CLK <20,22>
DDRAB_SMA10 AG34 M_ADD10 M_DATA9 A38 DDRAB_SDQ9 TDP1_AUXN E17
HDMI_DATA <20,22>
DDRAB_SMA11 R34 M_ADD11 M_DATA10 D40 DDRAB_SDQ10 A12 TDP1_TXP3
<20> DP2_TXP3
DDRAB_SMA12 N37 M_ADD12 M_DATA11 D41 DDRAB_SDQ11 <20>
B12 TDP1_TXN3 TDP1_HPD H19
<20>
1 DDRAB_SMA13 AN34 B36 DDRAB_SDQ12 DP2_TXN3 HDMI_DET 1
M_ADD13 M_DATA12
DDRAB_SMA14 L38 M_ADD14 M_DATA13 A37 DDRAB_SDQ13 A4 LTDP0_TXP0 LTDP0_AUXP D15
<21> LVDS_A2 EDID_CLK <21>
DDRAB_SMA15 L35 M_ADD15 M_DATA14 B41 DDRAB_SDQ14 B4 LTDP0_TXN0 LTDP0_AUXN E15
<21> LVDS_A2# EDID_DATA <21>
M_DATA15 C40 DDRAB_SDQ15
AJ38 M_BANK0 A5 LTDP0_TXP1 LTDP0_HPD H17 R897 1 2 100K_0402_5%
<8,9> DDRAB_SBS0# <21> LVDS_A1 +3VS
AG35 M_BANK1 M_DATA16 F40 DDRAB_SDQ16 B5 LTDP0_TXN1
<8,9> DDRAB_SBS1# <21> LVDS_A1#
N34 M_BANK2 M_DATA17 F41 DDRAB_SDQ17 LVDS DAC_RED B14
<8,9> DDRAB_SBS2# DAC_RED <22>
M_DATA18 K40 DDRAB_SDQ18 A6 LTDP0_TXP2
<8,9> DDRAB_SDM[7..0] <21> LVDS_A0
DDRAB_SDM0 B32 M_DM0 M_DATA19 K41 DDRAB_SDQ19 B6 LTDP0_TXN2 DAC_GREEN A14
<21> LVDS_A0# DAC_GRN <22>
DDRAB_SDM1 B38 M_DM1 M_DATA20 E40 DDRAB_SDQ20 CRT
DDRAB_SDM2 G40 M_DM2 M_DATA21 E41 DDRAB_SDQ21 A7 LTDP0_TXP3 DAC_BLUE B15
<21> LVDS_ACLK DAC_BLU <22>
DDRAB_SDM3 N41 M_DM3 M_DATA22 J40 DDRAB_SDQ22 B7 LTDP0_TXN3
<21> LVDS_ACLK#
DDRAB_SDM4 AG40 M_DM4 M_DATA23 J41 DDRAB_SDQ23
DDRAB_SDM5 AN41 M_DM5 DAC_HSYNC G19 CRT_HSYNC
CRT_HSYNC <22>
DDRAB_SDM6 AY40 M_DM6 M_DATA24 M41 DDRAB_SDQ24 K15 DISP_CLKIN_H DAC_VSYNC E19
CRT_VSYNC <22>
DDRAB_SDM7 AY34 M_DM7 M_DATA25 N40 DDRAB_SDQ25 H15 DISP_CLKIN_L
Y40 M_DM8 M_DATA26 T41 DDRAB_SDQ26 DAC_SCL D19
CRT_DDC_CLK <22>
M_DATA27 U40 DDRAB_SDQ27 APU_SVT G31 SVT DAC_SDA D21
<40> APU_SVT CRT_DDC_DATA <22>
B33 M_DQS_H0 M_DATA28 L40 DDRAB_SDQ28 APU_SVC D27 SVC
<8,9> DDRAB_SDQS0 <40> APU_SVC
A33 M_DQS_L0 M_DATA29 M40 DDRAB_SDQ29 APU_SVD E29 SVD DAC_ZVSS A16 DAC_ZVSS R416 1 2 499_0402_1%
<8,9> DDRAB_SDQS0# <40> APU_SVD
B40 M_DQS_H1 M_DATA30 R40 DDRAB_SDQ30
<8,9> DDRAB_SDQS1 +3VS
A40 M_DQS_L1 M_DATA31 T40 DDRAB_SDQ31 R124 1 @ 2 0_0402_5% APU_SIC B22 SIC H27
THERMDA
<8,9> DDRAB_SDQS1# <11,28,29> EC_SMB_CK2
H41 M_DQS_H2 R127 1 @ 2 0_0402_5% APU_SID B21 SID H29
THERMDC
<8,9> DDRAB_SDQS2 <11,28,29> EC_SMB_DA2
H40 M_DQS_L2 M_DATA32 AF40 DDRAB_SDQ32 DIECRACKMON D25
<8,9> DDRAB_SDQS2# P41 M_DQS_H3 M_DATA33 AF41 DDRAB_SDQ33 APU_RST# B20 APU_RST_L BP0 A27 APU_BP0
<8,9> DDRAB_SDQS3 P40 M_DQS_L3 M_DATA34 AK40 DDRAB_SDQ34 R117 1 @ 2 0_0402_5% LDT_RST# A20 LDT_RST_L BP1 B27 APU_BP1 EDID_CLK R255 2 1 4.7K_0402_5%
<8,9> DDRAB_SDQS3# AH41 M_DQS_H4 M_DATA35 AK41 DDRAB_SDQ35 BP2 A26 APU_BP2 EDID_DATA R256 2 1 4.7K_0402_5%
<8,9> DDRAB_SDQS4 AH40 M_DQS_L4 M_DATA36 AE40 DDRAB_SDQ36 APU_PWRGD B19 APU_PWROK BP3 B26 APU_BP3
<8,9> DDRAB_SDQS4# <40> APU_PWRGD
AP41 M_DQS_H5 M_DATA37 AE41 DDRAB_SDQ37 R118 1 @ 2 0_0402_5% LDT_PWRGD A19 LDT_PWROK PLLTEST1 B28 APU_PLLTEST1
<8,9> DDRAB_SDQS5 AP40 M_DQS_L5 M_DATA38 AJ40 DDRAB_SDQ38 PLLTEST0 A28 APU_PLLTEST0 RP23
<8,9> DDRAB_SDQS5# BA40 M_DQS_H6 M_DATA39 AJ41 DDRAB_SDQ39 R120 1 @ 2 0_0402_5% APU_PROCHOT# A22 PROCHOT_L BYPASSCLK_H B24 APU_BPCLK_H 8 1 DAC_BLU
<8,9> DDRAB_SDQS6 <28,34,40,6> H_PROCHOT#
AY41 M_DQS_L6 APU_ALERT# B18 ALERT_L BYPASSCLK_L A24 APU_BPCLK_L 7 2 DAC_GRN
2 <8,9> DDRAB_SDQS6# 2
AY33 M_DQS_H7 M_DATA40 AM41 DDRAB_SDQ40 PLLCHRZ_H AV35 6 3 DAC_RED
<8,9> DDRAB_SDQS7 T39
BA34 M_DQS_L7 M_DATA41 AN40 DDRAB_SDQ41 APU_TDI D29 TDI PLLCHRZ_L AU35 5 4 DP_150_ZVSS
<8,9> DDRAB_SDQS7# T40
AA40 M_DQS_H8 M_DATA42 AT41 DDRAB_SDQ42 APU_TDO D31 TDO M_TEST E33
T41
Y41 M_DQS_L8 M_DATA43 AU40 DDRAB_SDQ43 APU_TCK D35 TCK 150_0804_8P4R_1%
M_DATA44 AL40 DDRAB_SDQ44 APU_TMS D33 TMS FREE_2 A29
T42
AC35 M_CLK_H0 M_DATA45 AM40 DDRAB_SDQ45 APU_TRST# G27 TRST_L GIO_TSTDTM0_SERIALCLK H21 APU_SCLK
<8> DDRA_CLK0 AC34 M_CLK_L0 M_DATA46 AR40 DDRAB_SDQ46 APU_DBRDY B25 DBRDY GIO_TSTDTM0_CLKINIT H25 APU_CLKINT
<8> DDRA_CLK0# AA34 M_CLK_H1 M_DATA47 AT40 DDRAB_SDQ47 APU_DBREQ# A25 DBREQ_L
<8> DDRA_CLK1 AA32 M_CLK_L1 USB_ATEST0 AJ10
<8> DDRA_CLK1# T45
AE38 M_CLK_H2 M_DATA48 AV41 DDRAB_SDQ48 D23 VDDCR_NB_SENSE USB_ATEST1 AJ8
<9> DDRB_CLK0 <40> APU_VDDNB_SEN T43
AE37 M_CLK_L2 M_DATA49 AW40 DDRAB_SDQ49 G23 VDDCR_CPU_SENSE M_ANALOGIN R32
<9> DDRB_CLK0# <40> APU_VDD_SEN T44
AA37 M_CLK_H3 M_DATA50 BA38 DDRAB_SDQ50 E25 VDDIO_MEM_S_SENSE M_ANALOGOUT N32
<9> DDRB_CLK1 T46
AA38 M_CLK_L3 M_DATA51 AY37 DDRAB_SDQ51 E23 VSS_SENSE TMON_CAL AP29
<9> DDRB_CLK1# <40> APU_VDD_RUN_FB_L T47
M_DATA52 AU41 DDRAB_SDQ52
G38 M_RESET_L M_DATA53 AV40 DDRAB_SDQ53 AV33 VDD_095_FB_H HDMI_EN/DP_STEREOSYNCE21 DP_STEREOSYNC
<8,9> MEM_MAB_RST# MEM_MAB_EVENT# AE34 M_EVENT_L M_DATA54 AY39 DDRAB_SDQ54 UAPU A6@ UAPU A4@ AU33 VDD_095_FB_L
<8,9> MEM_MAB_EVENT#
M_DATA55 AY38 DDRAB_SDQ55
L34 M0_CKE0
<8> DDRA_CKE0 J38 M0_CKE1 M_DATA56 BA36 DDRAB_SDQ56
<8> DDRA_CKE1 J37 M1_CKE0 M_DATA57 AY35 DDRAB_SDQ57
<9> DDRB_CKE0 FT3 REV 0.51
J34 M1_CKE1 M_DATA58 BA32 DDRAB_SDQ58
<9> DDRB_CKE1
M_DATA59 AY31 DDRAB_SDQ59 A6 PR KABINI AM5200IAJ44HM 2G BGA769P APU A4 PR KABINI AM5000IBJ44HM 1.5G BGA 769P APU X4@ FT3_BGA769
<8> DDRA_ODT0
AN38
AU38
M0_ODT0
M0_ODT1
M_DATA60
M_DATA61
BA37
AY36
DDRAB_SDQ60
DDRAB_SDQ61
PU +3VS RP4 +3VS
<8> DDRA_ODT1 AN37 M1_ODT0 M_DATA62 BA33 DDRAB_SDQ62 ESDU@
<9> DDRB_ODT0 +1.8VS +3VS
AR37 M1_ODT1 M_DATA63 AY32 DDRAB_SDQ63 UAPU E1@ APU_PWRGD 1 2 APU_ALERT# 1 8
<9> DDRB_ODT1
C1270 100P_0402_50V8J APU_SID 2 7
AJ34 M0_CS_L0 M_CHECK0 V41 UAPU E2@ APU_PROCHOT# 3 6
<8> DDRA_SCS0# AR38 M0_CS_L1 M_CHECK1 W40 ESDU@ APU_SIC 4 5
<8> DDRA_SCS1#
2
AL38 M1_CS_L0 M_CHECK2 AB40 APU_RST# 1 2
<9> DDRB_SCS0# AN35 M1_CS_L1 M_CHECK3 AC40 C1273 100P_0402_50V8J R114 R113 1K_0804_8P4R_5%
<9> DDRB_SCS1#
M_CHECK4 U41 E1 PR KABINI EM2100ICJ23HM 1G BGA769P APU 1K_0402_5% 1K_0402_5%
3 AJ37 M_RAS_L M_CHECK5 V40 3
<8,9> DDRAB_SRAS# AL34 M_CAS_L M_CHECK6 AA41 E2 PR KABINI EM3000IBJ23HM 1.65G BGA 769P APU
<8,9>
PU +1.8VS
1
DDRAB_SCAS# AL35 AB41
M_WE_L M_CHECK7
<8,9> DDRAB_SWE# +1.8VS
DP_STEREOSYNC RP5 @
AD40 M_VREF UAPU X2@ UAPU E1PC@ CRT_HSYNC
+MEM_VREF 1 2 AC38 AD41 1 2 1 8
M_VREFDQ M_ZVDDIO_MEM_S M_ZVDDIO APU_SVT
+VREF_DQ +1.5V 2 7
R576 @ 0_0402_5% R74 For HDMI Need APU_SVC
FT3 REV 0.51
39.2_0402_1% APU_SVD 3 6
X4@ FT3_BGA769 4 5
UAPU X5@
ZZZ ZZZ X2 ES2 KABINI ZMA5B078J2360 1.65G BGA CPU E1 PC 2M101082J2361 1G BGA 769P 1K_0804_8P4R_5%
APU_RST# R80 1 2 300_0402_5%
HDT+ PU +1.8VS + PD
APU_PWRGD
APU_BPCLK_L
R82
R18
1
1
2 300_0402_5%
2 511_0402_1%
+1.8VS
X5 ES2 ZM201079J4460 2G BGA 769P JHDT2 +1.8VS
LA9911P 14@ LA9911P 15@ 1 2 APU_TCK RP6 RP3 @ +1.8VS
DAZ0Y600101 DAZ0Y700101
2
3
1 2
4 APU_TMS APU_TDI 1 8 APU_SCLK 1 8
PD RP7 @
ESDP@ C195 3 4 APU_TMS 2 7 APU_CLKINT 2 7
+VREF_DQ 0.1U_0402_16V7K 5 6 APU_TDI APU_TCK 3 6 APU_SCLK 3 6 APU_BP2 1 8
1 5 6 APU_DBREQ# 4 5 APU_CLKINT 4 5 APU_BP3 2 7
7 8 APU_TDO APU_BP0 3 6
7 8 1K_0804_8P4R_5% 1K_0804_8P4R_5% APU_BP1 4 5
MEMORY VREF 1
@
2
@ @ RP11
APU_TRST# 9
9 10
10 APU_PWRGD
1K_0804_8P4R_5%
C342 C164 11 12 APU_RST# RP8
1U_0402_6.3V6K 1 8 11 12 +1.8VS
0.1U_0402_16V7K
2 1 2 7 13 14 APU_DBRDY 1 8
3 6 13 14 APU_TRST# 2 7
4 5 15 16 APU_DBREQ# APU_PLLTEST0 3 6
15 16 APU_PLLTEST1 4 5
4 +1.5V RP2 10K_0804_8P4R_5% 17 18 APU_PLLTEST0 4
17 18 1K_0804_8P4R_5%
1 8 +MEM_VREF 19 20 APU_PLLTEST1
RP11, RP6 will @ when MP
2 7 19 20 APU_BPCLK_H R19 1 2 511_0402_1%
3 6 MEM_MAB_EVENT#
4 5 1 2
@ SAMTE_ASP-136446-07-B
1K_0804_8P4R_1% C337 C163
1U_0402_6.3V6K 0.1U_0402_16V7K
2 1
FT3 DDR3/DISP/MISC//HDT+
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VAWGA/GB 1.0
A B C D E
A B C D E
UAPUB
PCIE APU POWER SEQUENCE
R10 P_GPP_RXP0 P_GPP_TXP0 L2
R8 P_GPP_RXN0 P_GPP_TXN0 L1 G-A +RTC
R5 P_GPP_RXP1 P_GPP_TXP1 K2 PCIE_ATX_DRX_P1 C19 1 2 0.1U_0402_16V7K EC_ON
<24> PCIE_DTX_C_ARX_P1 PCIE_ATX_C_DRX_P1 <24>
LAN R4 P_GPP_RXN1 P_GPP_TXN1 K1 PCIE_ATX_DRX_N1 C20 1 2 0.1U_0402_16V7K LAN
<24> PCIE_DTX_C_ARX_N1 PCIE_ATX_C_DRX_N1 <24>
G-B +3VALW/+5VALW
N5 P_GPP_RXP2 P_GPP_TXP2 J2 PCIE_ATX_DRX_P2 C17 1 2 0.1U_0402_16V7K
<26> PCIE_DTX_C_ARX_P2 PCIE_ATX_C_DRX_P2 <26>
WLAN N4 P_GPP_RXN2 P_GPP_TXN2 J1 PCIE_ATX_DRX_N2 C18 1 2 0.1U_0402_16V7K WLAN
<26> PCIE_DTX_C_ARX_N2 PCIE_ATX_C_DRX_N2 <26>
N10 P_GPP_RXP3 P_GPP_TXP3 H2 +1.8VALW
N8 P_GPP_RXN3 P_GPP_TXN3 H1
1 +0.95VALW 1
1 2 P_TX_ZVDD_095 W8 P_TX_ZVDD_095 P_RX_ZVDD_095 W7 P_RX_ZVDD_095 2 1
+0.95VS_APU_GFX +0.95VS_APU_GFX
R404 R73 SYSON
1.69K_0402_1% 1K_0402_1%
G-C +1.5V
L5 P_GFX_RXP0 P_GFX_TXP0 G2 PCIE_ATX_GRX_P0 C1 PX@ 1 2 0.1U_0402_16V7K
<10> PCIE_GTX_C_ARX_P0 PCIE_ATX_C_GRX_P0 <10>
L4 P_GFX_RXN0 P_GFX_TXN0 G1 PCIE_ATX_GRX_N0 C2 PX@ 1 2 0.1U_0402_16V7K SUSP#
<10> PCIE_GTX_C_ARX_N0 PCIE_ATX_C_GRX_N0 <10>
J5 P_GFX_RXP1 P_GFX_TXP1 F2 PCIE_ATX_GRX_P1 C3 PX@ 1 2 0.1U_0402_16V7K G-D +3VS
J4 P_GFX_RXN1 P_GFX_TXN1 F1 PCIE_ATX_GRX_N1 C4 PX@ 1 2 0.1U_0402_16V7K
VGA VGA +1.8VS
G5 P_GFX_RXP2 P_GFX_TXP2 E2 PCIE_ATX_GRX_P2 C5 PX@ 1 2 0.1U_0402_16V7K
G4 P_GFX_RXN2 P_GFX_TXN2 E1 PCIE_ATX_GRX_N2 C6 PX@ 1 2 0.1U_0402_16V7K +1.5VS
D7 P_GFX_RXP3 P_GFX_TXP3 D2 PCIE_ATX_GRX_P3 C7 PX@ 1 2 0.1U_0402_16V7K +0.95VS
E7 P_GFX_RXN3 P_GFX_TXN3 D1 PCIE_ATX_GRX_N3 C8 PX@ 1 2 0.1U_0402_16V7K
VR_ON
G-E +APU_CORE
FT3 REV 0.51
X4@ FT3_BGA769 +APU_CORE_NB
UAPUE
2 2
CLK/SATA/USB/SPI/LPC
BA14 SATA_TX0P W4
USBCLK/14M_25M_48M_OSC
<23> SATA_ATX_DRX_P0
AY14 SATA_TX0N
<23> SATA_ATX_DRX_N0
USB_ZVSS AG4 USB_ZVSS R641 1 2 11.8K_0402_1%
HDD BA16 SATA_RX0N
<23> SATA_DTX_C_ARX_N0
AY16 SATA_RX0P USB_HSD0P AL4
<23> SATA_DTX_C_ARX_P0 USB20_P0 <27>
AL5
USB_HSD0N
USB20_N0 <27>Right USB port
AY19 SATA_TX1P
<23> SATA_ATX_DRX_P1
BA19 SATA_TX1N USB_HSD1P AJ4
<23> SATA_ATX_DRX_N1 USB20_P1 <26>
ODD AJ5
USB_HSD1N
USB20_N1 <26>Touch Screen
AY17 SATA_RX1N
<23> SATA_DTX_C_ARX_N1
BA17 SATA_RX1P USB_HSD2P AG7
<23> SATA_DTX_C_ARX_P1
USB_HSD2N AG8
R90 2 1 1K_0402_1% SATA_ZVSS AR19 SATA_ZVSS
R96 2 1 1K_0402_1% SATA_ZVDD AP19 SATA_ZVDD_095 USB_HSD3P AG1
+0.95VS USB20_P3 <21>
AG2
USB_HSD3N
USB20_N3 <21>CAMERA
BA30 SATA_ACT_L/GPIO67 USB_HSD4P AF1
T48 USB20_P4 <30>
AF2
USB_HSD4N
USB20_N4 <30>CardReader
AY12 SATA_X1
AE1
USB_HSD5P
USB_HSD5N AE2 USB20_P5
USB20_N5
<26>
<26>WLAN/BT combo 48MHz CRYSTAL
BA12 SATA_X2 USB_HSD6P AD1 48M_X2
USB20_P6 <27>
AD2
USB_HSD6N
USB20_N6 <27>USB2.0 LP1
VGA 0_0402_5% R938
<10> R112 1 @ 2 GFX_CLKP U4 GFX_CLKP USB_HSD7P AC1
<27> 1M_0402_5% 48M_X1
CLK_PEG_VGA USB20_P7
<10> R115 1 @ 2 GFX_CLKN U5 GFX_CLKN USB_HSD7N AC2
<27>USB2.0 LP2
CLK_PEG_VGA# USB20_N7
0_0402_5%
AC8 GPP_CLK0P USB_HSD8P AB1
USB30_P8 <27>
AC10 AB2 2 1
GPP_CLK0N USB_HSD8N
USB30_N8 <27>MB USB3.0 port0 2 1
LAN 0_0402_5%
3 R116 1 @ 2 GPP_CLK1P AE4 GPP_CLK1P USB_HSD9P AA1 3
<24> CLK_PCIE_LAN USB30_P9 <27>
<24> R119 1 @ 2 GPP_CLK1N AE5 GPP_CLK1N USB_HSD9N AA2
<27>MB USB3.0 port1
CLK_PCIE_LAN# USB30_N9 3 4
0_0402_5%
R125 1 @ 2 GPP_CLK2P AC4 AE10 USBSS_ZVSS R644 1 2 1K_0402_1% 3 4
GPP_CLK2P USB_SS_ZVSS
<26> CLK_PCIE_WLAN
<26> R126 1 @ 2 GPP_CLK2N AC5 GPP_CLK2N AE8
USB_SS_ZVDD_095_USB3_DUAL USBSS_ZVDD R645 1 2 1K_0402_1%
+0.95VALW
CLK_PCIE_WLAN#
0_0402_5% Y20
WLAN AA5 GPP_CLK3P USB_SS_0TXP T2 48MHZ_8PF_X3S048000D81H-W
<27>
USB30_MTX_C_DRX_P0
AA4 GPP_CLK3N USB_SS_0TXN T1
<27>
USB30_MTX_C_DRX_N0 RP12
1
AP13 X14M_25M_48M_OSC USB_SS_0RXP V2 APU_SPI_AISO 1 8 EC_SPI_AISO C794 C795
USB30_MRX_DTX_P0<27> EC_SPI_AISO <28>
USB_SS_0RXN V1 APU_SPI_AOSI_U 2 7 EC_SPI_AOSI 6P_0402_50V8 6P_0402_50V8
<28>
2
48M_X1 N2 USB30_MRX_DTX_N0<27> APU_SPI_CLK_U 3 6 EC_SPI_CLK EC_SPI_AOSI
X48M_X1
EC_SPI_CLK <28>
USB_SS_1TXP R1 APU_SPI_CS1#_U 4 5 EC_SPI_CS1#
<27>
USB30_MTX_C_DRX_P1 EC_SPI_CS1# <28>
USB_SS_1TXN R2
<27>
USB30_MTX_C_DRX_N1
0_0804_8P4R_5%
48M_X2 N1 X48M_X2 USB_SS_1RXP W1
W2 USB30_MRX_DTX_P1<27>
R103 R104 for EMI USB_SS_1RXN
USB30_MRX_DTX_N1<27>
R103 1 @ 2 0_0402_5% AY2 LPCCLK0

R109,R110,R111 close to APU 4MB SPI ROM
<28,6> LPC_CLK0_EC
R104 1 @ 2 0_0402_5% AW2 AU7 APU_SPI_CLK R110 1 2 33_0402_5% APU_SPI_CLK_U
<6> LPC_CLK1
AT2
LPCCLK1 SPI_CLK/GPIO162
SPI_CS1_L/GPIO165 AW9 APU_SPI_CS1# R111 1 2 33_0402_5% APU_SPI_CS1#_U (Current Share mode) +3VALW
LAD0 SPI_CS2_L/GPIO166 AR4 @
<28> LPC_AD0 T51 +3VALW
AT1 LAD1 SPI_DO/GPIO163 AR11 APU_SPI_AOSI R109 1 2 33_0402_5% APU_SPI_AOSI_U 2 1
<28> LPC_AD1 AR2 LAD2 SPI_DI/GPIO164 AR7 APU_SPI_AISO R614
<28> LPC_AD2 AR1 LAD3 SPI_HOLD_L/GEVENT9_LAU11 APU_SPI_HOLD# 10K_0402_5% U56 C635
<28> LPC_AD3 AP2 LFRAME_L SPI_WP_L/GPIO161 AU9 APU_SPI_WP# 1 2 APU_SPI_CS1#_U 1 8 0.1U_0402_16V4Z
<28,6> LPC_FRAME# CS# VCC
AP1 LDRQ0_L APU_SPI_AISO R108 1 2 33_0402_5% APU_SPI_AISO_U 2 7 APU_SPI_HOLD# 1 2
AV29 1 2 APU_SPI_WP# 3 SO/SIO1 HOLD# 6 APU_SPI_CLK_U
<28> SERIRQ SERIRQ/GPIO48 R108 close to ROM WP# SCLK
R615
AP25 LPC_CLKRUN_L R616 4 5 APU_SPI_AOSI_U 10K_0402_5%
T50 AV2 10K_0402_5% GND SI/SIO0
LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L
FT3 REV 0.51

APU->EC->ROM must route as W25Q32FVSSIG SOIC 8P SPI ROM
4 4
X4@ FT3_BGA769 Daisy Chain for Share ROM quality APU_SPI_CLK_U 1 2 1 2
R617 EMIU@
(RP12 was request to added for the recoverable solution 10_0402_5% C636 EMIU@
10P_0402_50V8J
as original method--backup)
FT3 PCIE/SATA/CLK/USB/SPI
A B C D E
A B C D E
1 2
C615 UAPUD
150P_0402_50V8J ACPI/SD/AZ/GPIO/RTC/MISC
1 2 LPC_RST_A# AY4 LPC_RST_L SD_PWR_CTRL BA23
<28> LPC_RST#
R602 APU_PCIE_RST#_BUF AY9 PCIE_RST_L SD_CLK/GPIO73 AY22
33_0402_5%
EC_RSMRST#_R AY5 RSMRST_L SD_CMD/GPIO74 AY23
SD_CD/GPIO75 AY20
BA8 PWR_BTN_L SD_WP/GPIO76 BA20
<28> PBTN_OUT# PWR_GOOD_APU AM19 PWR_GOOD
T36 AY7 SYS_RESET_L/GEVENT19_L SD_DATA0/GPIO77 BA22 APU_PCIE_RST#_BUF 1 2
APU_PCIE_RST# <10,24,26>
APU_PCIE_WAKE# AW11 WAKE_L/GEVENT8_L SD_DATA1/GPIO78 AY21 R907
<26> APU_PCIE_WAKE#
SD_DATA2/GPIO79 AY24 33_0402_5% 1
AY3 SLP_S3_L SD_DATA3/GPIO80 BA24
1 <28> SLP_S3# 1
BA5 SLP_S5_L C912
<28> SLP_S5#
SD_LED/GPIO45 AY25 150P_0402_50V8J
TEST0 AU13 TEST0
2
CS_JTAG_TMS_TEST1 AY10 TEST1/TMS SCL0/GPIO43 AU25 APU_SCLK0
APU_SCLK0 <26,8,9>
TEST2 AY6 TEST2 SDA0/GPIO47 AV25 APU_SDATA0
APU_SDATA0 <26,8,9>
AR23 KBRST_L SCL1/GPIO227 AY11 APU_SCLK1 If use as SMBUS :
<28> KBRST# +3VS
AR31 GA20IN/GEVENT0_L SDA1/GPIO228 BA11 APU_SDATA1 Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of:
<28> GATEA20 AN5 LPC_PME_L/GEVENT3_L Qty: 1; Value: 2.2 Kȍ; Tol: 5%
<28> EC_SCI# AL7 LPC_SMI_L/GEVENT23_L GPIO49 AP27 If no use :
<28> EC_SMI# Pulled-up to VDD_33(port0) , VDD_33_ALW(port1) with a resistor of:
GPIO50 AY28
BT_OFF# <26>
1
GPIO51 BA28 Qty: 1; Value: 10 Kȍ; Tol: 5%
AP15 AC_PRES/IR_RX0/GEVENT16_L GPIO55 AV23
WL_OFF# <26>
AV13 IR_TX0/GEVENT21_L GPIO57 AP21 UMA@ R911
ODD_EN <23>
BA9 IR_TX1/GEVENT6_L GPIO58 BA26 10K_0402_5%
BA10 IR_RX1/GEVENT20_L GPIO59 AV19 Board_ID1
2
AV15 IR_LED_L/LLB_L/GPIO184 GPIO64 AY27 R122 1 @ 2 0_0402_5%
PXS_RST# <10>
SPKR/GPIO66 BA27 Board_ID1
APU_SPKR <31>
AU29 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60 GPIO68 AU21 PXS_PWREN
PXS_PWREN <12,28,39>
LAN_CLKREQ# AW29 CLK_REQ1_L/GPIO61 GPIO69 AY26 Board_ID1 Function
<24> LAN_CLKREQ#
1
WLAN_CLKREQ# AR27 CLK_REQ2_L/GPIO62 GPIO70 AV21
<26> WLAN_CLKREQ#
T53 AV27 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63 GPIO71 AM21 R661 1 @ 2 0_0402_5%
H_PROCHOT# <28,34,4,40>
1 2 VGA_CLKREQ#_R AY29 CLK_REQG_L/GPIO65/OSCIN GPIO174 BA3 APU_GPIO174 PX@ R912
<11> VGA_CLKREQ#
R578 @ 0_0402_5% 10K_0402_5%
<27>
AY8 USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L GEVENT2_L AV17 GEVENT2# 0 PX5.5
2
USB_OC0# AW1 USB_OC1_L/TDI/GEVENT13_L GEVENT4_L BA4
<27> USB_OC1#
T52 AV1 GEVENT7_L AR15
T54 AY1
USB_OC2_L/TCK/GEVENT14_L
USB_OC3_L/TDO/GEVENT15_L GEVENT10_L AP17
1 UMA
GEVENT11_L AP11
HDA_BITCLK AN2 AZ_BITCLK GEVENT17_L AN8
HDA_SDOUT
HDA_SDIN0
AN1
AK2
AZ_SDOUT
AZ_SDIN0/GPIO167
BLINK/GEVENT18_L AU17
GEVENT22_L BA6 EC_LID_OUT#
32.768KMHz CRYSTAL
2 <31> HDA_SDIN0 EC_LID_OUT# <28> 2
T55 HDA_SDIN1 AK1 AZ_SDIN1/GPIO168
T56 HDA_SDIN2 AM1 AZ_SDIN2/GPIO169 GENINT1_L/GPIO32 BA29 32K_X1
T57 HDA_SDIN3 AL2 AZ_SDIN3/GPIO170 GENINT2_L/GPIO33 AP23 VGA_PWRGD
VGA_PWRGD <39>
HDA_SYNC AM2 AZ_SYNC 1 2 32K_X2
HDA_RST# AL1 AZ_RST_L FANOUT0/GPIO52 AV31
FANIN0/GPIO56 AU31 R914
BT_DISABLE# <26>
20M_0402_5%
32K_X1 AJ2 X32K_X1
Y3
32.768KHZ_12.5P_1TJF125DP1A000D
RTCCLK AV11
RTC_CLK <28>
32K_X2 AJ1 X32K_X2 1 2
FT3 REV 0.51
X4@ FT3_BGA769 1 1
C682 C686
22P_0402_50V8J 18P_0402_50V8J
PU +3VALW + PD 2 2
+3VALW
RP13
R691 1 @ 2 10K_0402_5%
1 8 HDA_RST#
<31>
<31>
HDA_RST#_AUDIO
HDA_SYNC_AUDIO
2
3
7
6
HDA_SYNC STRAPS OF APU
HDA_BITCLK
<31> HDA_BITCLK_AUDIO 4 5 HDA_SDOUT
<31> HDA_SDOUT_AUDIO
33_0804_8P4R_5%
LPC_FRAME# LPC_CLK0_EC LPC_CLK1 GEVENT2_L RTC_CLK
R686 1 2 10K_0402_5% APU_GPIO174
SPI ROM BOOT FAIL TIMER CLKGEN 1.8V SPI ROM NORMAL POWR
3
PU +3VALW
H (DEFAULT) ENABLED ENABLE
(DEFAULT)
UP/RESET TIMING
(DEFAULT)
3
+3VALW EC_RSMRST# , POWER_GOOD +1.8VALW BOOT FAIL TIMER CLKGEN 3.3V SPI ROM FAST POWER
+3VS 1
2
RP14
8
7
APU_SCLK1
APU_SDATA1 follow CRB Must connected to 10 ms RC delay
circuit on +1.8-V S5 power rail.
L LPC ROM DISABLED
(DEFAULT)
DISABLED (DEFAULT) UP/RESET TIMING
FOR SIMULATION
2
3 6 APU_PCIE_WAKE#
4 5
R121
1 @ 2 PXS_PWREN
0_0402_5% (APU side 1.8V power rail) R345
47K_0402_5%
R685
10K_0402_5% +3VALW
10K_0804_8P4R_5%
D3
1
R656 1 @ 2 100K_0402_5% EC_LID_OUT# <28>

1 2 EC_RSMRST#_R
EC_RSMRST#
1
R650 1 2 100K_0402_5% USB_OC0#
R651 1 2 100K_0402_5% USB_OC1# RB751V-40TE17_SOD323-2 @ @
R902 R904 R925 R928 R949
D5
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
1 2 PWR_GOOD_APU
PU +3VS <28>
2
SYS_PWRGD_EC
<28,5> LPC_FRAME#
RB751V-40TE17_SOD323-2 <28,5> LPC_CLK0_EC
1 1 <5> LPC_CLK1
+3VS 1U_0402_6.3V6K 1U_0402_6.3V6K
C209 C212 GEVENT2#
R622 1 @ 2 8.2K_0402_5% WLAN_CLKREQ#
2 2 RTC_CLK
R621 1 @ 2 8.2K_0402_5% LAN_CLKREQ#
R673 1 2 2.2K_0402_5% APU_SCLK0
PU +3VALW + PD
1
R674 1 2 2.2K_0402_5% APU_SDATA0 RP9 @ +3VALW @
@ @ R929 R950
4 R618 1 @ 2 8.2K_0402_5% VGA_CLKREQ#_R 1 8 R903 R926 R927 4
2.2K_0402_5% 2.2K_0402_5%
2 7 2K_0402_5% 2K_0402_5% 2K_0402_5%
3 6
2
4 5
PD R684 1 @ 2 10K_0402_5% HDA_BITCLK 1K_0804_8P4R_5%
RP10 @
R688 1 @ 2 10K_0402_5% HDA_SDIN0 Security Classification Compal Secret Data Compal Electronics, Inc.
TEST0 1 8 2012/04/22 2015/04/22 Title
Issued Date Deciphered Date
R689 1 @ 2 10K_0402_5% VGA_CLKREQ#_R CS_JTAG_TMS_TEST1 2 7
TEST2 3 6
FT3 GPIO/AZ/MISC
4 5 Size Document Number Rev
15K_0804_8P4R_5% MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D E
A B C D E
CORE POWER OF APU RTC OF APU VDDBT_RTC_G

+RTCBATT
+APU_CORE VDDCR_CPU
+RTCBATT_R W=20mils R93 1 2 10K_0402_5%
C179
C180
C181
C182
C183
C184
C186
C187
C188
C189
C190
1 1 1 1 1 1 1 1 1 1 1 1
1
C166 CLRP1 J@ Need OPEN
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
0.22U_0402_10V6K SHORT PADS
2
2 2 2 2 2 2 2 2 2 2 2 2
1 1
for Clear CMOS
INTEGRATED GPU POWER OF APU +3VALW/+3VS OF APU +3VALW
+APU_CORE_NB VDDCR_NB +3VS @

+3VALW_APU 2 1
R582 0_0603_5%
C200
C201
C202
C192
C191
C193
C194
C197
C249
C257
C252
C253
1 1 1 1 1 1 1 1 1 1 1 1
UAPUH
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
1U_0402_6.3V6K
180P_0402_50V8J
1U_0402_6.3V6K
1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2
UAPUF UAPUG
POWER GND GND
J35 VDDIO_MEM_S_1 VDDCR_CPU_1 L21 A8 VSS_1 VSS_63 J3 W29 VSS_125 VSS_187 AL39
+1.5V +APU_CORE
L32 VDDIO_MEM_S_2 VDDCR_CPU_2 L23 A13 VSS_2 VSS_64 J7 W39 VSS_126 VSS_188 AL41
L37 VDDIO_MEM_S_3 VDDCR_CPU_3 L25 A23 VSS_3 VSS_65 J8 W41 VSS_127 VSS_189 AM11
N35 VDDIO_MEM_S_4 VDDCR_CPU_4 L27 A31 VSS_4 VSS_66 J39 Y1 VSS_128 VSS_190 AM27
R31 VDDIO_MEM_S_5 VDDCR_CPU_5 L29 A35 VSS_5 VSS_67 K11 Y2 VSS_129 VSS_191 AM31
2 R37 2
VDDCR_CPU_6 N21 A39 K13 AA3 AN3
VDD_33 VDD_33_ALW U32
VDDIO_MEM_S_6
VDDIO_MEM_S_7 VDDCR_CPU_7 N23 B8
VSS_6
VSS_7
VSS_68
VSS_69 K17 AA7
VSS_130
VSS_131
VSS_192
VSS_193 AN7
U35 VDDIO_MEM_S_8 VDDCR_CPU_8 N27 B13 VSS_8 VSS_70 K19 AA8 VSS_132 VSS_194 AN39
W31 VDDIO_MEM_S_9 VDDCR_CPU_9 R21 B23 VSS_9 VSS_71 K21 AA11 VSS_133 VSS_195 AP31
VDDIO_AZ_ALW W32 VDDCR_CPU_10 R23 B31 K23 AA15 AR3
+1.5V/+1.5VS OF APU (Could be S0 or S5 power rail) W37
AA31
VDDIO_MEM_S_10
VDDIO_MEM_S_11 VDDCR_CPU_11 R27 B39
VSS_10
VSS_11
VSS_72
VSS_73 K25 AA19
VSS_134
VSS_135
VSS_196
VSS_197 AR13
VDDIO_MEM_S_12 VDDCR_CPU_12 U21 C1 VSS_12 VSS_74 K27 AA25 VSS_136 VSS_198 AR17
PLANE SPLIT AA35 VDDIO_MEM_S_13 VDDCR_CPU_13 U23 C2 VSS_13 VSS_75 K29 AA29 VSS_137 VSS_199 AR21
+1.5V +1.5VS AC32 VDDCR_CPU_14 U27 C5 K31 AA39 AR25
VDDIO_MEM_S AC37
VDDIO_MEM_S_14
VDDIO_MEM_S_15 VDDCR_CPU_15 W21 C7
VSS_14
VSS_15
VSS_76
VSS_77 L3 AC3
VSS_138
VSS_139
VSS_200
VSS_201 AR29
AE31 VDDIO_MEM_S_16 VDDCR_CPU_16 W23 C9 VSS_16 VSS_78 L7 AC7 VSS_140 VSS_202 AR39
AE35 VDDIO_MEM_S_17 VDDCR_CPU_17 W27 C11 VSS_17 VSS_79 L8 AC11 VSS_141 VSS_203 AR41
C924
C925
C949
C923
C926
C927
C928
C929
C931
C930
C932
C211
C210
C208
C207
C230
C231
C258
C259
C161
C256
C254
C255
C232
AG32 VDDIO_MEM_S_18 VDDCR_CPU_18 AA21 C13 VSS_18 VSS_80 L10 AC15 VSS_142 VSS_204 AU1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AG37 VDDIO_MEM_S_19 VDDCR_CPU_19 AA23 C15 VSS_19 VSS_81 L11 AC19 VSS_143 VSS_205 AU2
AJ35 VDDIO_MEM_S_20 VDDCR_CPU_20 AA27 C17 VSS_20 VSS_82 L15 AC25 VSS_144 VSS_206 AU3
AL32 VDDIO_MEM_S_21 VDDCR_CPU_21 AC21 C19 VSS_21 VSS_83 L19 AC29 VSS_145 VSS_207 AU15
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
180P_0402_50V8J
4.7U_0603_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
AL37 VDDIO_MEM_S_22 VDDCR_CPU_22 AC23 C21 VSS_22 VSS_84 L31 AC31 VSS_146 VSS_208 AU19
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 AR35 VDDIO_MEM_S_23 VDDCR_CPU_23 AC27 C23 VSS_23 VSS_85 L39 AC39 VSS_147 VSS_209 AU23
VDDCR_CPU_24 AE21 C25 VSS_24 VSS_86 L41 AC41 VSS_148 VSS_210 AU27
VDDCR_CPU_25 AE23 C27 VSS_25 VSS_87 M1 AE3 VSS_149 VSS_211 AU39
VDDCR_CPU_26 AE27 C29 VSS_26 VSS_88 M2 AE7 VSS_150 VSS_212 AV9
C31 VSS_27 VSS_89 N3 AE25 VSS_151 VSS_213 AW3
VDDCR_NB_1 L13 C33 VSS_28 VSS_90 N7 AE29 VSS_152 VSS_214 AW7
+APU_CORE_NB
VDDCR_NB_2 L17 C35 VSS_29 VSS_91 N15 AE32 VSS_153 VSS_215 AW13
VDDCR_NB_3 N11 C37 VSS_30 VSS_92 N19 AE39 VSS_154 VSS_216 AW15
@ @ @ @ @ VDDCR_NB_4 N13 C39 VSS_31 VSS_93 N25 AG3 VSS_155 VSS_217 AW17
VDDCR_NB_5 N17 C41 VSS_32 VSS_94 N29 AG5 VSS_156 VSS_218 AW19
VDDCR_NB_6 R11 D9 VSS_33 VSS_95 N31 AG10 VSS_157 VSS_219 AW21
VDDCR_NB_7 R13 D11 VSS_34 VSS_96 N39 AG11 VSS_158 VSS_220 AW23
VDDCR_NB_8 R17 D13 VSS_35 VSS_97 P1 AG13 VSS_159 VSS_221 AW25
VDDCR_NB_9 U13 E3 P2 AG15 AW27
3
+0.95VALW/+0.95VS OF APU VDD_095_GFX +1.8VALW/+1.8VS OF APU VDDCR_NB_10 U17 E4
VSS_36
VSS_37
VSS_98
VSS_99 R3 AG19
VSS_160
VSS_161
VSS_222
VSS_223 AW31
3
VDDCR_NB_11 W13 E9 VSS_38 VSS_100 R7 AG25 VSS_162 VSS_224 AW33
VDDCR_NB_12 W17 E11 R15 AG29 AW35
+0.95VS +0.95VS_APU_GFX +1.8VS VDD_18 VDDCR_NB_13 AA13 E13
VSS_39 VSS_101
R19 AG31
VSS_163 VSS_225
AW37
VDD_095 L22 VDDCR_NB_14 AA17 E27
VSS_40
VSS_41
VSS_102
VSS_103 R25 AG39
VSS_164
VSS_165
VSS_226
VSS_227 AW39
2 1 VDDCR_NB_15 AC13 E31 VSS_42 VSS_104 R29 AG41 VSS_166 VSS_228 AW41
FBMA-L11-201209-121LMA50T_0805 VDDCR_NB_16 AC17 E35 VSS_43 VSS_105 R39 AH1 VSS_167 VSS_229 AY13
C935
C934
C198
C199
C205
C204
C206
C260
C213
C936
C203
C933
C236
C237
C238
C239
C240
C233
VDDCR_NB_17 AE15 E38 VSS_44 VSS_106 R41 AH2 VSS_168 VSS_230 AY15
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDDCR_NB_18 AE17 E39 VSS_45 VSS_107 U1 AJ3 VSS_169 VSS_231 AY18
VDDCR_NB_19 AE19 G3 VSS_46 VSS_108 U2 AJ7 VSS_170 VSS_232 AY30
VDDCR_NB_20 AG17 G7 VSS_47 VSS_109 U3 AJ15 VSS_171 VSS_233 BA2
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
10U_0603_6.3V6M
1U_0402_6.3V6K
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
AL10 VDDIO_AZ_ALW_1 VDDCR_NB_21 AG21 G11 VSS_48 VSS_110 U7 AJ17 VSS_172 VSS_234 BA7
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 +1.5VS
AL11 VDDIO_AZ_ALW_2 G13 VSS_49 VSS_111 U8 AJ19 VSS_173 VSS_235 BA13
G15 VSS_50 VSS_112 U11 AJ23 VSS_174 VSS_236 BA15
B1 VDD_18_ALW_1 VDD_18_1 A2 G17 VSS_51 VSS_113 U15 AJ25 VSS_175 VSS_237 BA18
+1.8VALW +1.8VS
B2 VDD_18_ALW_2 VDD_18_2 A3 G21 VSS_52 VSS_114 U19 AJ29 VSS_176 VSS_238 BA21
VDD_18_3 B3 G25 VSS_53 VSS_115 U25 AJ31 VSS_177 VSS_239 BA25
VDD_18_4 C3 G29 VSS_54 VSS_116 U29 AJ32 VSS_178 VSS_240 BA31
G35 VSS_55 VSS_117 U31 AJ39 VSS_179 VSS_241 BA35
@ @ AL13 VDD_33_ALW_1 VDD_33_1 AM15 G37 VSS_56 VSS_118 U39 AL3 VSS_180 VSS_242 BA39
+3VALW_APU +3VS
AM13 VDD_33_ALW_2 VDD_33_2 AM17 G39 VSS_57 VSS_119 W3 AL8 VSS_181 VSSBG_DAC A15
+0.95VALW +0.95VALW +1.8VALW G41 VSS_58 VSS_120 W5 AL15 VSS_182 VBURN AL31
AR5 VDD_095_USB3_DUAL_1 VDD_095_1 AG23 H11 VSS_59 VSS_121 W11 AL17 VSS_183 PSEN AM29
+0.95VALW +0.95VS
AU4 VDD_095_USB3_DUAL_2 VDD_095_2 AG27 H13 VSS_60 VSS_122 W15 AL19 VSS_184
AV7 VDD_095_USB3_DUAL_3 VDD_095_3 AJ21 H23 VSS_61 VSS_123 W19 AL25 VSS_185
C937
C938
C216
C214
C221
C218
C220
C217
C219
C222
C160
C244
C250
C246
C248
C245
AW5 VDD_095_USB3_DUAL_4 VDD_095_4 AJ27 H31 VSS_62 VSS_124 W25 AL29 VSS_186
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD_095_5 AL21 FT3 REV 0.51 FT3 REV 0.51

AE11 VDD_095_ALW_1 VDD_095_6 AL23
+0.95VALW
AE13 VDD_095_ALW_2 VDD_095_7 AL27 X4@ FT3_BGA769 X4@ FT3_BGA769
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
180P_0402_50V8J
AJ11 VDD_095_ALW_3 VDD_095_8 AM23

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 AJ13 VDD_095_ALW_4 VDD_095_9 AM25
VDD_095_GFX_1 U10
4 +0.95VS_APU_GFX 4
VDD_095_GFX_2 W10
+RTCBATT_R AN4 VDDBT_RTC_G VDD_095_GFX_3 AA10
FT3 REV 0.51
@ @ X4@ FT3_BGA769
VDD_095_USB3_DUAL
VDD_095_ALW VDD_18_ALW Security Classification Compal Secret Data Compal Electronics, Inc.
FT3 PWR/GND
A B C D E
A B C D E
+VREF_DQ +1.5V +1.5V
15mil JDIMM1
1 2
VREF_DQ VSS1
1000P_0402_50V7K
3 4 DDRAB_SDQ[0..63]
0.1U_0402_16V4Z
DDRAB_SDQ4
VSS2 DQ4 DDRAB_SDQ[0..63] <4,9>
2 1 DDRAB_SDQ0 5 6 DDRAB_SDQ5
DQ0 DQ5
C176
C142
DDRAB_SDQ1 7 8 DDRAB_SDM[0..7]
DQ1 VSS3 DDRAB_SDM[0..7] <4,9>
9 10 DDRAB_SDQS0#
VSS4 DQS#0 DDRAB_SDQS0# <4,9>
DDRAB_SDM0 11 12 DDRAB_SDQS0 DDRAB_SMA[0..15]
1 2 DM0 DQS0 DDRAB_SDQS0 <4,9> DDRAB_SMA[0..15] <4,9>
13 14
DDRAB_SDQ2 15 VSS5 VSS6 16 DDRAB_SDQ6
DDRAB_SDQ3 17 DQ2 DQ6 18 DDRAB_SDQ7
19 DQ3 DQ7 20
1 DDRAB_SDQ8 21 VSS7 VSS8 22 DDRAB_SDQ12 1
25 DQ9 DQ13 26
DDRAB_SDQS1# 27 VSS9 VSS10 28 DDRAB_SDM1
<4,9> DDRAB_SDQS1# DQS#1 DM1
DDRAB_SDQS1 29 30 MEM_MAB_RST#
<4,9> DDRAB_SDQS1 DQS1 RESET# MEM_MAB_RST# <4,9>
31 32
DDRAB_SDQ10 33
35
VSS11
DQ10
VSS12
DQ14
34
36
DDRAB_SDQ14 +1.5V/+0.75VS OF DIMM1
DDRAB_SDQ11 DDRAB_SDQ15
37 DQ11 DQ15 38
DDRAB_SDQ16 39 VSS13 VSS14 40 DDRAB_SDQ20 +1.5V +0.75VS
43 DQ17 DQ21 44
C114
C115
C116
C117
C118
C119
C120
C121
C122
C123
C126
C127
DDRAB_SDQS2 47 48
<4,9> DDRAB_SDQS2 DQS2 VSS17
49 50 DDRAB_SDQ22 1 1 1 1 1 1 1 1 1 1 1 1
DDRAB_SDQ18 51 VSS18 DQ22 52 DDRAB_SDQ23
DDRAB_SDQ19 53 DQ18 DQ23 54
DQ19 VSS19
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
55 56 DDRAB_SDQ28
DDRAB_SDQ24 57 VSS20 DQ28 58 DDRAB_SDQ29 2 2 2 2 2 2 2 2 2 2 2 2
61 DQ25 VSS21 62 DDRAB_SDQS3#
DDRAB_SDM3 63 64 DDRAB_SDQS3
DM3 DQS3 DDRAB_SDQS3 <4,9>
65 66
71 DQ27 DQ31 72 @ @ @ @ @ @
VSS25 VSS26
DDRA_CKE0 73 74 DDRA_CKE1
<4> DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 <4>
75 76
77 VDD1 VDD2 78 DDRAB_SMA15
2
<4,9> DDRAB_SBS2#
DDRAB_SBS2# 79
81
NC1
BA2
A15
A14
80
82
DDRAB_SMA14 VREF for DIMM1,2 2
DDRAB_SMA12 83 VDD3 VDD4 84 DDRAB_SMA11

DDRAB_SMA9 85 A12/BC# A11 86 DDRAB_SMA7 +1.5V +1.5V
87 A9 A7 88
A8 A6
2
DDRAB_SMA5 91 92 DDRAB_SMA4
93 A5 A4 94 R65 R66
DDRAB_SMA3 95 VDD7 VDD8 96 DDRAB_SMA2 1K_0402_1%
A3 A2 20K_0402_1%
DDRAB_SMA1 97 98 DDRAB_SMA0
99 A1 A0 100
1
DDRA_CLK0 101 VDD9 VDD10 102 DDRA_CLK1 +VREF_DQ +VREF_CA
<4> DDRA_CLK0 CK0 CK1 DDRA_CLK1 <4>
DDRA_CLK0# 103 104 DDRA_CLK1#
<4> DDRA_CLK0# CK0# CK1# DDRA_CLK1# <4>
105 106
DDRAB_SMA10 107 VDD11 VDD12 108 DDRAB_SBS1#
A10/AP BA1 DDRAB_SBS1# <4,9>
2
DDRAB_SBS0# 109 110 DDRAB_SRAS#
<4,9> DDRAB_SBS0# BA0 RAS# DDRAB_SRAS# <4,9>
111 112 R67 R68
DDRAB_SWE# 113 VDD13 VDD14 114 DDRA_SCS0# 1K_0402_1%
<4,9> DDRAB_SWE# WE# S0# DDRA_SCS0# <4> 20K_0402_1%
DDRAB_SCAS# 115 116 DDRA_ODT0
<4,9> DDRAB_SCAS# CAS# ODT0 DDRA_ODT0 <4>
117 118
1
DDRAB_SMA13 119 VDD15 VDD16 120 DDRA_ODT1
A13 ODT1 DDRA_ODT1 <4>
DDRA_SCS1# 121 122
<4> DDRA_SCS1# S1# NC2
123 124 15mil
125 VDD17 VDD18 126
NCTEST VREF_CA +VREF_CA
127 128
VSS27 VSS28
1000P_0402_50V7K
0.1U_0402_16V4Z
DDRAB_SDQ32 129 130 DDRAB_SDQ36
DQ33 DQ37 1 2
C134
C167
133 134
DDRAB_SDQS4 137 138
<4,9> DDRAB_SDQS4 DQS4 VSS31 2 1
139 140 DDRAB_SDQ38
3 DDRAB_SDQ35 143 DQ34 DQ39 144 3
145 DQ35 VSS33 146 DDRAB_SDQ44
155 156
161 DQ43 DQ47 162
167 DQ49 DQ53 168
DDRAB_SDQS6 171 172
173 174 DDRAB_SDQ54
189 190
R69 10K_0402_5% 195 DQ59 DQ63 196
1 2 197 VSS51 VSS52 198 MEM_MAB_EVENT#
SA0 EVENT# MEM_MAB_EVENT# <4,9>
199 200
+3VS VDDSPD SDA APU_SDATA0 <26,6,9>
201 202
SA1 SCL APU_SCLK0 <26,6,9>
203 204
VTT1 VTT2 +0.75VS
1
4 R70 205 206 4

G1 G2
+3VS 10K_0402_5% FOX_AS0A626-U8SN-7F
ME@
2
1 1
C135 C136 Security Classification Compal Secret Data Compal Electronics, Inc.
2.2U_0603_6.3V6K 0.1U_0402_16V4Z 2012/04/22 2015/04/22 Title
2 2
DIMM_A H:8mm Issued Date Deciphered Date
DDR3 SODIMM-I Socket
<Address: 00> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
VAWGA/GB
A B C D E
A B C D E
+VREF_DQ +1.5V +1.5V
15mil JDIMM2
1 2
3 VREF_DQ VSS1 4 DDRAB_SDQ4 DDRAB_SDQ[0..63]
VSS2 DQ4 DDRAB_SDQ[0..63] <4,8>
1000P_0402_50V7K
0.1U_0402_16V4Z
DDRAB_SDQ1 7 DQ0 DQ5 8 DDRAB_SDM[0..7]
2 1 DQ1 VSS3 DDRAB_SDM[0..7] <4,8>
C177
C143
9 10 DDRAB_SDQS0#
DDRAB_SDM0 11 12 DDRAB_SDQS0 DDRAB_SMA[0..15]
DM0 DQS0 DDRAB_SDQS0 <4,8> DDRAB_SMA[0..15] <4,8>
13 14
1 2 DDRAB_SDQ2 15 VSS5 VSS6 16 DDRAB_SDQ6
19 DQ3 DQ7 20
1 DDRAB_SDQ8 21 VSS7 VSS8 22 DDRAB_SDQ12 1
25 DQ9 DQ13 26
DDRAB_SDQS1 29 30 MEM_MAB_RST#
<4,8> DDRAB_SDQS1 DQS1 RESET# MEM_MAB_RST# <4,8>
31 32
DDRAB_SDQ10 33
35
VSS11
DQ10
VSS12
DQ14
34
36
DDRAB_SDQ14 +1.5V/+0.75VS OF DIMM2
DDRAB_SDQ11 DDRAB_SDQ15
37 DQ11 DQ15 38
DDRAB_SDQ16 39 VSS13 VSS14 40 DDRAB_SDQ20 +1.5V +0.75VS +1.5V
43 DQ17 DQ21 44
VSS15 VSS16
220U_6.3V_M
DDRAB_SDQS2# 45 46 DDRAB_SDM2 1
C133
C155
C132
C162
C165
C168
C169
C170
C171
C172
C175
C158
DDRAB_SDQS2 47 48
C644
49 50 DDRAB_SDQ22 +
VSS18 DQ22 1 1 1 1 1 1 1 1 1 1 1 1
DQ19 VSS19 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
55 56 DDRAB_SDQ28
DDRAB_SDQ24 57 VSS20 DQ28 58 DDRAB_SDQ29 2 2 2 2 2 2 2 2 2 2 2 2
65 66
71 DQ27 DQ31 72 @ @ @ @
VSS25 VSS26
DDRB_CKE0 73 74 DDRB_CKE1
<4> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <4>
75 76
77 VDD1 VDD2 78 DDRAB_SMA15
2 DDRAB_SBS2# 79 NC1 A15 80 DDRAB_SMA14 2
<4,8> DDRAB_SBS2# BA2 A14
81 82
DDRAB_SMA9 85 A12/BC# A11 86 DDRAB_SMA7
87 A9 A7 88
DDRAB_SMA5 91 A8 A6 92 DDRAB_SMA4
93 A5 A4 94
DDRAB_SMA1 97 A3 A2 98 DDRAB_SMA0
99 A1 A0 100
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1
<4> DDRB_CLK0 CK0 CK1 DDRB_CLK1 <4>
DDRB_CLK0# 103 104 DDRB_CLK1#
<4> DDRB_CLK0# CK0# CK1# DDRB_CLK1# <4>
105 106
DDRAB_SMA10 107 VDD11 VDD12 108 DDRAB_SBS1#
A10/AP BA1 DDRAB_SBS1# <4,8>
DDRAB_SBS0# 109 110 DDRAB_SRAS#
<4,8> DDRAB_SBS0# BA0 RAS# DDRAB_SRAS# <4,8>
111 112
DDRAB_SWE# 113 VDD13 VDD14 114 DDRB_SCS0#
<4,8> DDRAB_SWE# WE# S0# DDRB_SCS0# <4>
DDRAB_SCAS# 115 116 DDRB_ODT0
<4,8> DDRAB_SCAS# CAS# ODT0 DDRB_ODT0 <4>
117 118
DDRAB_SMA13 119 VDD15 VDD16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 <4>
DDRB_SCS1# 121 122
<4> DDRB_SCS1# S1# NC2
123 124 15mil
125 VDD17 VDD18 126
NCTEST VREF_CA +VREF_CA
127 128
VSS27 VSS28
1000P_0402_50V7K
0.1U_0402_16V4Z
DQ33 DQ37 1 2
C139
C174
133 134
DDRAB_SDQS4 137 138
<4,8> DDRAB_SDQS4 DQS4 VSS31 2 1
139 140 DDRAB_SDQ38
3 DDRAB_SDQ35 143 DQ34 DQ39 144 3
155 156
161 DQ43 DQ47 162
167 DQ49 DQ53 168
DDRAB_SDQS6 171 172
173 174 DDRAB_SDQ54
189 190
R71 10K_0402_5% 195 DQ59 DQ63 196
1 2 197 VSS51 VSS52 198 MEM_MAB_EVENT#
SA0 EVENT# MEM_MAB_EVENT# <4,8>
199 200
+3VS VDDSPD SDA APU_SDATA0 <26,6,8>
1 2 201 202
SA1 SCL APU_SCLK0 <26,6,8>
203 204
VTT1 VTT2 +0.75VS
R72 10K_0402_5%
4 205 206 4
G1 G2
FOX_AS0A626-U4SN-7F
ME@

2012/04/22 2015/04/22 Title
DIMM_B H:4mm Issued Date Deciphered Date
DDR3 SODIMM-II Socket
<Address: 10> AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
VAWGA/GB
A B C D E
A B C D E
UV1A
PART 1 0F 9
LVDS Interface
UV1D
1 1
AA38 Y33 PCIE_GTX_ARX_P0 CV1 PX@ 1 2 0.1U_0402_16V7K PART 7 0F 9
<5> PCIE_ATX_C_GRX_P0 PCIE_RX0P PCIE_TX0P PCIE_GTX_C_ARX_P0 <5>
Y37 Y32 PCIE_GTX_ARX_N0 CV2 PX@ 1 2 0.1U_0402_16V7K
<5> PCIE_ATX_C_GRX_N0 PCIE_RX0N PCIE_TX0N PCIE_GTX_C_ARX_N0 <5>
AK27
RSVD/VARY_BL AJ27
Y35 W33 PCIE_GTX_ARX_P1 CV3 PX@ 1 2 0.1U_0402_16V7K RSVD/DIGON
<5> PCIE_ATX_C_GRX_P1 PCIE_RX1P PCIE_TX1P PCIE_GTX_C_ARX_P1 <5> LVDS CONTROL
W36 W32 PCIE_GTX_ARX_N1 CV4 PX@ 1 2 0.1U_0402_16V7K
W38 U33 PCIE_GTX_ARX_P2 CV5 PX@ 1 2 0.1U_0402_16V7K AK35

<5> PCIE_ATX_C_GRX_P2 PCIE_RX2P PCIE_TX2P PCIE_GTX_C_ARX_P2 <5> TXCBP_DPB3P
V37 U32 PCIE_GTX_ARX_N2 CV6 PX@ 1 2 0.1U_0402_16V7K AL36
<5> PCIE_ATX_C_GRX_N2 PCIE_RX2N PCIE_TX2N PCIE_GTX_C_ARX_N2 <5> TXCBM_DPB3N
AJ38
V35 U30 PCIE_GTX_ARX_P3 CV7 PX@ 1 2 0.1U_0402_16V7K TX3P_DPB2P AK37
<5> PCIE_ATX_C_GRX_P3 PCIE_RX3P PCIE_TX3P PCIE_GTX_C_ARX_P3 <5> TX3M_DPB2N
U36 U29 PCIE_GTX_ARX_N3 CV8 PX@ 1 2 0.1U_0402_16V7K
AH35
TX4P_DPB1P AJ36
U38 T33 TX4M_DPB1N
T37 PCIE_RX4P PCIE_TX4P T32 AG38
PCIE_RX4N PCIE_TX4N TX5P_DPB0P AH37
TX5M_DPB0N
T35 T30 AF35
R36 PCIE_RX5P PCIE_TX5P T29 NC#AF35 AG36
SUN NC
PCIE_RX5N PCIE_TX5N NC#AG36
LVTMDP
R38 P33
P37 PCIE_RX6P PCIE_TX6P P32
PCIE_RX6N PCIE_TX6N
AP34
TXCAP_DPA3P AR34
P35 P30 TXCAM_DPA3N
N36 PCIE_RX7P PCIE_TX7P P29 AW37
PCIE_RX7N PCIE_TX7N TX0P_DPA2P AU35
2 TX0M_DPA2N 2
N38 N33 AR37
M37 NC NC N32 TX1P_DPA1P AU39
NC NC TX1M_DPA1N
PCI EXPRESS INTERFACE AP35
M35 N30 TX2P_DPA0P AR35
L36 NC NC N29 TX2M_DPA0N
NC NC
AN36
NC AP37
L38 L33 NC
K37 NC NC L32
NC NC
K35 L30 MARS@ MARS-XT M2_FCBGA962

J36 NC NC L29
NC NC
J38 K33
H37 NC NC K32
NC NC
H35 J33 UV1 SUN@

G36 NC NC J32
NC NC
G38 K30
F37 NC NC K29
NC NC
S IC 216-0841000-00 A0 SUN PRO M2 FCBGA 962P C38
F35 H33
E37 NC NC H32 SA00006BA20
NC NC
3 3
CLOCK +3VGS
CLK_PEG_VGA AB35
<5> CLK_PEG_VGA PCIE_REFCLKP
CLK_PEG_VGA# AA36
<5> CLK_PEG_VGA# PCIE_REFCLKN
5
2
P
CALIBRATION <6> PXS_RST# B 4 GPU_RST#
Y30 RV1 1 PX@ 2 1.69K_0402_1% 1 Y
PCIE_CALR_TX +0.95VGS <24,26,6> APU_PCIE_RST# A
G
PX@
2 PX@ 1 AH16 Y29 RV3 1 PX@ 2 1K_0402_1% UV2
+0.95VGS
3
TEST_PG PCIE_CALR_RX MC74VHC1G08DFT2G SC70 5P
RV2 1K_0402_5%
GPU_RST# AA30
PERSTB
1
PX@ MARS@ MARS-XT M2_FCBGA962

RV4
100K_0402_5%
2
4 4

ATI_MarsXTX_M2_PCIE/LVDS
Custom 1.0
VAWGA/GB
A B C D E
A B C D E
UV1B CONFIGURATION STRAPS RECOMMENDED SETTINGS

PART 2 0F 9 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
MUTI GFX GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
T1 GENLK_CLK AD29 GENLK_CLK AU24 NA = NOT APPLICABLE
AC29 NC AV23
T2 GENLK_VSYNC GENLK_VSYNC NC
AT25 STRAPS STRAPS MLPS DESCRIPTION OF DEFAULT SETTINGS Default Setting
AJ21 NC AR24
SWAPLOCKA DPA NC
AK21 SWAPLOCKB Transmitter Power Savings Enable

AU26 TX_PWRS_ENB PS_1[4] 0:50% Tx output swing
NC
AV25 1:Full Tx output swing
NC
+3VGS
AR8 AT27 PCIE Transmitter De-emphasis Enable
NC NC

AU8 NC AR26 TX_DEEMPH_EN PS_1[5] 0:Tx de-emphasis disabled
AP8 NC 2 1 100K_0402_5%
DBG_CNTL0 GPU_GPIO5 RV5 @ 1:Tx de-emphasis enabled
AW8 NC AR30
1 NC 1
AR3 AT29 PCIE Gen3 Enable
NC NC

AR1 THM_ALERT# RV6 2 @ 1 2.2K_0402_5% BIF_GEN3_EN_A PS_1[1] (NOTE:RESERVED for Thames/Seymour and should
NC
AU1 DBG_DATA0 AV31 be strapped to 0)
AU3 NC AU30
DBG_DATA1 DPB NC
AW3 DBG_DATA2 0:GEN3 not support at power-on
AP6 AR32 1:GEN3 supported at power-on
DBG_DATA3 NC
AW5 AT31
DBG_DATA4 NC
AU5 DBG_DATA5 VGA control

AR6 AT33 BIF_VGA DIS PS_2[4] 0:VGA controller capacity enabled
DBG_DATA6 NC
AW6 DBG_DATA7 AU32 1:VGA controller capacity disabled (for multi-GPU)
NC +3VGS
AU6
DBG_DATA8
AT7 AU14 Serial ROM type or Memory Aperture Size Select
DBG_DATA9 NC
AV7 DBG_DATA10 AV13 JTAG_TRSTB RV7 2 @ 1 10K_0402_5% ROMIDCFG[2:0] PS_0[3..1] If PS_2[3]=0, defines memory aperture size
AN7 NC 2 1 10K_0402_5%
DBG_DATA11 JTAG_TDI RV8 @ If PS_2[3]=1, defines ROM type

AV9 DBG_DATA12 AT15 JTAG_TMS RV9 2 @ 1 10K_0402_5% 100 - 512Kbit M25P05A (ST)
NC
AT9 AR14 101 - 1Mbit M25P10A (ST)
DBG_DATA13 NC
AR10 JTAG_TCK RV10 2 @ 1 10K_0402_5% 101 - 2Mbit M25P20 (ST)
0%
DBG_DATA14 DPC
AW10 DBG_DATA15 AU16 101 - 4Mbit M25P40 (ST)
AU10 NC AV15
DBG_DATA16 NC 101 - 8Mbit M25P80 (ST)
AP10 DBG_DATA17 100 - 512Kbit Pm25LV010 (Chingis)
AV11 AT17 101 - 1Mbit Pm25LV010 (Chingis)
DBG_DATA18 NC
AT11 AR16
DBG_DATA19 NC
AR12 DBG_DATA20
AW12 AU20 Enable external BIOS ROM device
DBG_DATA21 NC

AU12 DBG_DATA22 AT19 BIOS_ROM_EN PS_2[3] 0:Disabled
NC
AP12 1:Enabled
DBG_DATA23
AT21
NC
AR20 00 - No audio function
NC
AUD[1] NA 01 - Audio for DP only
VGA_SMB_CK2 AJ23 DPD AU22 10 - Audio for DP and HDMI if dongle is detected
SMBCLK SMBus NC
1&
VGA_SMB_DA2 AH23 AV21 AUD[0] NA 11 - Audio for both DP and HDMI
SMBDATA NC
AT23 HDMI must only be enabled on systems that are
NC AR22 legally entitled. It isthe responsibility of the system
NC
AK26 SCL designer to ensure that the system is entitled to
AJ26 I2C support this feature.
SDA

2 AD39 VGA_R 2
R AD37
GENERAL PURPOSE I/O T24 CEC_DIS PS_0[4] Reserved for future ASIC
GPU_GPIO0 AH20 AVSSN
<39> GPU_GPIO0
AH18
GPIO_0
AE36 VGA_G
AVDD MarsCRB Design NOTE:ALLOW FOR PULLUP PADS FOR THE
GPIO_1 G
AN16
GPIO_2 AVSSN
AD35 T25 120ohm 1 1 RESERVED STRAPS BUT DO NOT INSTALL
DV1 RESISTOR
RB751V_SOD323 @
B
AF37 VGA_B 0.1u 1 1 IF THESE GPIOS ARE USEED, THEY MUST KEEP
1 2 GPU_GPIO5 AH17 AE38 T26 LOW AND NOT CONFLICT DURING RESET
<28,35> ACIN GPIO_5_AC_BATT AVSSN 1u 1 1

GPU_VID5 AJ17
<39> GPU_VID5 GPIO_6_TACH DAC1
AK17 AC36 HSYNC 10u 1 1 RESERVED PS_1[3] Reserved
GPIO_7_BLON HSYNC

AJ13 GPIO_8_ROMSO AC38 VSYNC T4
AH15 VSYNC T6 RESERVED PS_1[2] Reserved
GPIO_9_ROMSI
1$
AJ16 GPIO_10_ROMSCK
AK16 AB34 RV11 1 PX@ 2 499_0402_1% +AVDD +1.8VGS RESERVED NA Reserved
GPIO_11 RSET
1$
AL16
GPIO_12
AM16 GPIO_13 AD34 +AVDD (1.8V@70mA AVDD) LV1 1 @ 2 0_0402_5% RESERVED NA Reserved (for Thames/Whistler/Seymour only)
AM14 AVDD AE34
GPIO_14_HPD2 AVSSQ
GPU_VID1 AM13
CV17
CV18
CV19
1U_0402_6.3V6K
<39> GPIO_15_PWRCNTL_0
10U_0603_6.3V6M
0.1U_0402_16V7K
GPU_VID1 (1.8V@117mA VDD1DI)
AK14 AC33 +VDD1DI 1 1 1 STRAPS TO INDICATE THE NUMBER OF AUDIO
GPIO_16 VDD1DI
THM_ALERT# AG30 AC34 AUD_PORT_CONN_PINSTRAP[2] PS_3[5] CAPABLE DISPLAY OUTPUTS
GPIO_17_THERMAL_INT VSS1DI
AN14 GPIO_18_HPD3 111 = 0 usable endpoints
@ RV12 1 2 10K_0402_5% AM17
GPIO_19_CTF AUD_PORT_CONN_PINSTRAP[1] PS_3[4] 110 = 1 usable endpoints
2 2 2

@
<39> GPU_VID2 AL13 GPIO_20_PWRCNTL_1 V13 101 = 2 usable endpoints
GPU_VID2 NC
AJ14 U13 AUD_PORT_CONN_PINSTRAP[0] PS_0[5] 100 = 3 usable endpoints
GPIO_21 NC
AK13 AF33 011 = 4 usable endpoints
GPIO_22_ROMCSB NC
<6> VGA_CLKREQ# AN13 CLKREQB AF32 010 = 5 usable endpoints
VGA_CLKREQ# NC AA29
NC 001 = 6 usable endpoints
AG21 +VDD1DI +1.8VGS
NC 000 = all endpoints are usable
GPU_VID3 AG32 AC32
<39> GPU_VID3 GPIO_29 NC
GPU_VID4 AG33 LV2 1 @ 2 0_0402_5%
<39> GPU_VID4 GPIO_30
AC31
AJ19 NC_SVI2 AD30
CV20
CV21
CV22
1U_0402_6.3V6K
GENERICA
10U_0603_6.3V6M
0.1U_0402_16V7K
NC_SVI2
AK19 GENERICB AD32 1 1 1
NC_SVI2
AJ20
GENERICC
AK20
AJ24
GENERICD VDD1DI MarsCRB Design
GENERICE_HPD4 2 2 2
120ohm 1 1
@
@
AH26
GENERICF_HPD5
AH24 GENERICG_HPD6
3
0.1u 1 1 3
PS_0
AM34 PS_0
1u 1 1 MLPS Strap
AC30 10u 1 1
CEC_1
0.60 V level, Please Bits[5:4] Bits[3:1] Capacitor R_pu R_pd
AK24 AD31 PS_1
VREFG Divider ans HPD1 MLPS PS_1
+1.8VGS +VREFG_GPU cap close to ASIC PS_0[5:1] 11 001 NC 8.45K 2K
PX@
2 RV13 1 499_0402_1% +VREFG_GPU AH13 DBG_VREFG PS_2 AG31 PS_2
PX@ PS_1[5:1] 01 010 82 nF 4.53K 2K
2 RV14 1 249_0402_1%
BACO
2 1 0.1U_0402_16V7K PX_EN AL21 AD33 PS_3 PS_2[5:1] 00 000 680 nF NC 4.75K
PX_EN PS_3
CV23 T29
PX@ Mapping to VRAM type please refer to page 45
PS_3[5:1] 11 XXX NC X X
DEBUG DDC/AUX +1.8VGS
1 @ 2 TESTEN AM26 VGA_CLK
+3VGS DDC1CLK
RV18 5.11K_0402_5% AN26 VGA_DAT T27
DDC1DATA
1 PX@ 2 AD28 T28
TESTEN
RV19 1K_0402_5% AM27
AUX1P
1
AL27
AUX1N
GPIO_28_FDO MLPS
JTAG_TRSTB AM23 JTAG_TRSTB AM19 X76@ RV20 @ RV21 PX@RV22
PX@ RV22 PX@RV23
PX@ RV23
DDC2CLK
H Disable JTAG_TDI AN23 AL19 8.45K_0402_1% 8.45K_0402_1% 4.53K_0402_1% 8.45K_0402_1%
JTAG_TDI DDC2DATA +3VGS
JTAG_TCK AK23
JTAG_TCK
2
L Enable JTAG_TMS AL24 JTAG_TMS AN20 PS_0
AM24 AUX2P AM20
T11 JTAG_TDO JTAG_TDO PS_1
AUX2N
PS_2
AL30 +3VGS PS_3
NC
1
AM30 @ @
NC
1
RV24 RV25 @ 1 PX@ 1 PX@ 1 @ 1
THERMAL AL29 10K_0402_5% 10K_0402_5% CV26 CV27 CV29 CV28
NC
<29> RV16 1 @ 2 0_0402_5% THERM_D+ AF29 DPLUS AM29 X76@ RV27 PX@RV28
PX@ RV28 PX@RV29
PX@ RV29 PX@RV30
PX@ RV30
0.01U_0402_25V7K
0.68U_0402_10V6K
0.01U_0402_25V7K
REMOTE1+ NC
0.082U_0402_16V7K
2
<29> RV17 1 @ 2 0_0402_5% THERM_D- AG29

DMINUS 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1% 2K_0402_1%
REMOTE1-
2
1 @ 2 GPIO_28_FDO AN21 2 2 2 2
+3VGS NC
2
4 RV26 10K_0402_5% AM21 VGA_SMB_CK2 1 6 <28,29,4> 4
1 PX@ 2 AK32 NC EC_SMB_CK2
GPIO_28_FDO
5
RV31 10K_0402_5% AK30 QV3A @

NC
AL31 AK29 DMN66D0LDW-7_SOT363-6
+1.8VGS +TSVDD TS_A NC
(1.8V@13mA TSVDD) VGA_SMB_DA2 4 3
DDCVGACLK
AJ30
EC_SMB_DA2 <28,29,4> Place CLOSE VGA CHIP
LV3 1 @ 2 0_0402_5% +TSVDD AJ32 AJ31 QV3B @
TSVDD DDCVGADATA
AJ33 DMN66D0LDW-7_SOT363-6
1U_0402_6.3V6K
TSVSS
10U_0603_6.3V6M
0.1U_0402_16V4Z
CV30
CV31
CV32
1 1 1
MARS@ MARS-XT M2_FCBGA962
TSVDD MarsCRB Design Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2
120ohm 1 1 Issued Date 2012/07/03 Deciphered Date 2013/07/03 Title
PX@
PX@
PX@
0.1u 1 1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ATI_MarsXTX_M2_Main_MSIC
1u 1 1 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
C 1.0
10u 1 1
VAWGA/GB
A B C D E
A B C D E
UV1C
PART 9 0F 9
+1.8VGS @ +MPV18
LV4 (MPLL_PVDD:1.8V@130mA )
MPLL_PVDD MarsCRB Design 1 2 AV33 XTALIN RV32 1 2 1M_0402_5%
XTALIN
220ohm 1 1
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
CV33
CV34
CV35
1 0_0603_5% 1
PX@
0.1u 1 1 1 1 1 YV1
4 3 XTALOUT
1u 1 1 NC OSC
10u 1 1 XTALIN 1 2
PX@
2
PX@
2
PX@
2 AU34 XTALOUT OSC NC
XTALOUT
1 27MHZ 10PF +-20PPM X3G027000DA1H 1
PX@CV36
PX@ CV36 PX@ CV37 PX@
+MPV18 H7 10P_0402_50V8J 10P_0402_50V8J
MPLL_PVDD 2 2
H8
+1.8VGS MPLL_PVDD
+SPV18 (SPLL_PVDD:1.8V@75mA ) AW34
SPLL_PVDD MarsCRB Design XO_IN
120ohm 1 1 1 @ 2 +SPV18 AM10
SPLL_PVDD
PLLS/XTAL
LV5
0.1u 1 1
10U_0603_6.3V6M
CV38
CV39
CV40
1U_0402_6.3V6K
0.1U_0402_16V7K
0_0402_5%
1u 1 1 1 1 1
+SPLL_VDDC AN9 AW35
SPLL_VDDC XO_IN2
10u 1 1
PX@
PX@
PX@
2 2 2
AN10
SPLL_PVSS
+0.95VGS +SPLL_VDDC AK10

SPLL_VDDC MarsCRB Design (SPLL_VDDC:0.95V@100mA ) AF30 CLKTESTA AL10
NC_XTAL_PVDD CLKTESTB
120ohm 1 1 1 @ 2 AF31
NC_XTAL_PVSS
1
LV6 @ @
0.1u 1 1
10U_0603_6.3V6M
CV43
CV44
CV45
1U_0402_6.3V6K
0.1U_0402_16V7K
0_0402_5% CV41 CV42
1 1 1 0.1U_0402_16V7K 0.1U_0402_16V7K
1u 1 1
2
2 2
10u 1 1
PX@
PX@
PX@
2 2 2
1
@ @
RV33 RV34
51.1_0402_1% 51.1_0402_1%
2
+3VS +3VGS
+3VS TO +3VGS
3 1 4.7U_0603_6.3V6K 1U_0603_10V6K
1
QV8 1 1
LP2301ALT1G_SOT23-3 CV46 CV47 @
PX@ RV36
2
PX@ @ 470_0603_5%
2 2
+1.8VALW TO +1.8VGS
2
+5VALW
1
G
2 +0.95VALW TO +0.95VGS
RV37 PX@ RV38 PX@ S @
Load switch
3
QV7
20K_0402_5% 20K_0402_5% 2N7002H_SOT23-3
3 3
1 PX@
1
D PX@ PXS_PWREN# +1.8VALW VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

PXS_PWREN 2 QV6 CV52 +1.8VGS
<28,39,6> PXS_PWREN 0.1U_0402_16V4Z J18VG
G 2N7002H_SOT23-3 U1895V J@
2 1 14 +1.8VGS_LS 1 2
S
3
2 VIN1 VOUT1 13
VIN1 VOUT1
1 C29 PAD-OPEN 4x4m 2
@ PXS_PWREN 3 12 PX@ 1 2 @ C32
ON1 CT1 2200P_0402_50V7K C28
1U_0402_6.3V6K
0.1U_0402_16V4Z
4 11
2 VL VBIAS GND 1
+1.5V TO +1.5VGS AO4430: Rdson: 5.5mohm @ VGS=10V PXS_PWREN 5
ON2 CT2
10 PX@ 1
2200P_0402_50V7K
2
C27 +0.95VGS
6 9 J95VG
J@
+1.5V +1.5VGS +0.95VALW 7 VIN2 VOUT2 8 +0.95VGS_LS 1 2
UV4 VIN2 VOUT2
AO4304L_SO8 15 PAD-OPEN 4x4m 2
360mil(9A) 8 1
360mil(9A) GPAD @ C31
PX@ 1 7 2 TPS22966DPUR_SON14_2X3
0.1U_0402_16V4Z
CV48 6 3 1
2
4.7U_0603_6.3V6K 5 1
1 PX@ 1@ @ C30 PX@
CV49 CV50 RV39 @
2
1U_0402_6.3V6K
4.7U_0603_6.3V6K 0.1U_0402_16V4Z 470_0603_5%
4
PX@ 2
2 2
1
+3VALW B+
RV41 240K_0402_5%
1
2 1
PX@ PX@
2
R286 1
1
100K_0402_5% RV42 @ PX@ D

4 CV53 @ QV1 2 PXS_PWREN# 4
0_0402_5%
2
0.1U_0402_25V6 2N7002H_SOT23-3 G
6
2 S
1
3
3
PX@
PX@ PXS_PWREN# 2 QV157A
PXS_PWREN 5 QV157B DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
1
1

PX@ R276
100K_0402_5%
ATI_MarsXTX_M2_BACO POWER
2
Custom 1.0
VAWGA/GB
A B C D E
A B C D E
UV1G
PART 6 0F 9 UV1F
AB39 A3 PART 8 0F 9
E39 GND GND A37 +0.95VGS
GND GND DP_VDDR DP_VDDC
(DP_VDDC:0.95V@280mA/link )
F34 AA16
F39 GND GND AA18 AP31
G33 GND GND AA2 DP_VDDC AP32
GND GND DP_VDDC
0.1U_0402_16V7K
10U_0603_6.3V6M
1U_0402_6.3V6K
G34 AA21 AN33
CV54
GND GND DP_VDDC
CV55
CV56
H31 AA23 AP33
H34 GND GND AA26 AN24 DP_VDDC AL33
GND GND NC DP_VDDC 1 1 1
H39 AA28 AP24 AM33
J31 GND GND AA6 AP25 NC DP_VDDC AK33
PX@
PX@
PX@
1 J34 GND GND AB12 AP26 NC DP_VDDC AK34 1
K31 GND GND AB15 AU28 NC DP_VDDC AN31 2 2 2
K34 GND GND AB17 DP_VDDR MarsCRB Design AV29 NC DP_VDDC
GND GND NC
K39
L31 GND GND
AB20
AB22
0.1u 1 1
L34 GND GND AB24 1u 1 1 AP20 AP13
M34 GND GND AB27 AP21
NC NC AT13 DP_VDDC MarsCRB Design
M39 GND GND AC11 10u 1 1 AP22 NC NC AP14 0.1u 1 1
N31 GND GND AC13 AP23 NC NC AP15
N34 GND GND AC16 AU18 NC NC 1u 1 1
P31 GND GND AC18 AV19 NC
P34 GND GND AC2 +1.8VGS +DP_VDDR (DP_VDDR:1.8V@237mA/link )
NC DP GND 10u 1 1
P39 GND GND AC21 AN27
R34 GND GND AC23 DP_VSSR
RV43 1 @ 2 0_0402_5% +DP_VDDR AH34 AP27
T31 GND GND AC26 AJ34 DP_VDDR DP_VSSR AP28
GND GND DP_VDDR DP_VSSR
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
T34 AC28 AF34 AW24
CV57
CV58
CV59
T39 AC6 AG34 AW26
U31 GND GND AD15 AM37 DP_VDDR DP_VSSR AN29
GND GND 1 1 1 DP_VDDR DP_VSSR
U34 AD17 AL38 AP29
V34 GND GND AD20 AM32 DP_VDDR DP_VSSR AP30
PX@
PX@
PX@
V39 AD22 AW30
W31 GND GND AD24 2 2 2 DP_VSSR AW32
W34 GND GND AD27 DP_VSSR AN17
Y34 GND GND AD9 DP_VSSR AP16
Y39 GND GND AE2 DP_VSSR AP17
GND GND AE6 DP_VSSR AW14
GND AF10 DP_VSSR AW16
GND AF16 DP_VSSR AN19
GND AF18 DP_VSSR AP18
GND AF21 DP_VSSR AP19
GND GND DP_VSSR
AG17 AW20
F15 GND AG2 CALIBRATION DP_VSSR AW22
2 F17 GND GND AG20 DP_VSSR AN34 2
F19 GND GND DP_VSSR AP39
F21 GND AG6 AW28 DP_VSSR AR39
F23 GND GND AG9 NC DP_VSSR AU37
F25 GND GND AH21 DP_VSSR AF39
F27 GND GND AJ10 DP_VSSR AH39
F29 GND GND AJ11 AW18 DP_VSSR AK39
F31 GND GND AJ2 NC DP_VSSR AL34
F33 GND GND AJ28 DP_VSSR AV27
F7 GND GND AJ6 DP_VSSR AR28
F9 GND GND AK11 DP_VSSR
RV44 2 PX@ 1 150_0402_1% AM39 AV17
G2 GND GND AK31 DP_CALR DP_VSSR AR18
G6 GND GND AK7 DP_VSSR AN38
H9 GND GND AL11 DP_VSSR AM35
J2 GND GND AL14 DP_VSSR AN32
J27 GND GND AL17 DP_VSSR
J6 GND GND AL2
J8 GND GND AL20
K14 GND GND
K7 GND AL23
L11 GND AL26
L17 GND GND AL32 MARS@ MARS-XT M2_FCBGA962
L2 GND GND AL6
L22 GND GND AL8
L24 GND GND AM11
L6 GND GND AM31
M17 GND GND AM9
M22 GND GND AN11
M24 GND GND AN2
N16 GND GND AN30
N18 GND GND AN6
N2 GND GND AN8
3 N21 GND GND AP11 3
N23 GND GND AP7
N26 GND GND AP9
N6 GND GND AR5
R15 GND GND B11
R17 GND GND B13
R2 GND GND B15
R20 GND GND B17
R22 GND GND B19
R24 GND GND B21
R27 GND GND B23
R6 GND GND B25
T11 GND GND B27
T13 GND GND B29
T16 GND GND B31
T18 GND GND B33
T21 GND GND B7
T23 GND GND B9
T26 GND GND C1
U15 GND GND C39
U17 GND GND E35
U2 GND GND E5
U20 GND GND F11
U22 GND GND F13
U24 GND GND
U27 GND GND
U6 GND
V11 GND AG22
V16 GND NC
V18 GND
V21 GND
V23 GND
4 V26 GND 4
W2 GND
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND A39 MECH#1 TV12 PAD
Y24 GND VSS_MECH AW1 MECH#2 TV13 PAD
Y27 GND
GND
VSS_MECH
VSS_MECH
AW39 MECH#3 TV14 PAD Security Classification Compal Secret Data Compal Electronics, Inc.
ATI_MarsXTX_M2_PWR_GND
MARS@ MARS-XT M2_FCBGA962 Size Document Number
Rev
Custom 1.0
VAWGA/GB
A B C D E
A B C D E
(PCIE_VDDR:1.8V@100mA ) +PCIE_VDDR LV7

@ +1.8VGS
+1.5VGS UV1E
For GDDR5, MVDDQ = 1.5V PART 5 0F 9 +PCIE_VDDR 2 1
PCIE_VDDR MarsCRB Design
0.1u 0 2
CV62
CV63
CV64
CV65
(VDDR1:1.5V@3A,GDDR5:1125MHz ) MEM I/O 0_0603_5%
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
0.01U_0402_25V7K
+1.5VGS AC7
VDDR1 NC
AA31 1 1 1 1 1u 2 3
AD11 AA32
AF7
VDDR1 NC AA33 10u 1 1
CV66
CV60
CV67
CV68
CV69
CV70
CV71
CV73
CV74
CV75
CV76
CV61
CV77
CV78
CV79
CV171
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDDR1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
NC
220U_B2_2.5VM_R35
PX@
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AG10 VDDR1 AA34
NC 2 2 2 2
PX@
PX@
PX@
+ AJ7 W30
VDDR1 NC
@ AK8 Y31
VDDR1 NC
AL9 VDDR1 V28
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 NC_BIF_VDDC
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
G11 W29
VDDR1 NC_BIF_VDDC +0.95VGS
G14 AB37
1 VDDR1 PCIE_PVDD PCIE_VDDC MarsCRB Design 1
PCIE
G17 (PCIE_VDDC:0.95V@2.5A_GEN3.0 )
VDDR1
G20
G23
VDDR1 PCIE_VDDC
G30
G31
+0.95VGS 1u 7 5
VDDR1 PCIE_VDDC
G26 H29 10u 2 1
CV80
CV81
CV82
CV83
CV84
CV85
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDDR1
10U_0603_6.3V6M
PCIE_VDDC
G29 VDDR1 H30 1 1 1 1 1 1
PCIE_VDDC
H10 J29
VDDR1 MarsCRB Design J7
VDDR1 PCIE_VDDC J30
VDDR1 PCIE_VDDC
0.01u 5 0 J9 VDDR1 PCIE_VDDC
L28
2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
K11 M28
VDDR1 PCIE_VDDC
0.1u 5 5 K13 VDDR1 PCIE_VDDC
N28
K8 R28
1u 0 5 L12
VDDR1
VDDR1
PCIE_VDDC T28
PCIE_VDDC
2.2u 5 0 L16 VDDR1 U28
L21 PCIE_VDDC +0.95VGS
VDDR1
10u 3 5 L23 VDDR1 (BIF_VDDC:0.95V@1.4A)
L26 N27 +0.95VGS
220u 0 1 VDDR1 BACO BIF_VDDC
L7 T27
VDDR1 BIF_VDDC
10U_0603_6.3V6M
M11
CV86
CV87
CV88
VDDR1
1U_0402_6.3V6K
1U_0402_6.3V6K
N11 1 1 1
VDDR1
P7 VDDR1 AA15
CORE VDDC
R11 AA17
+1.8VGS +VDDC_CT VDDR1 VDDC
PX@
U11 AA20
VDDR1 VDDC 2 2 2
PX@
PX@
(VDD_CT:1.8V@13mA ) U7 AA22
VDD_CT MarsCRB Design 1 @ 2 Y11
VDDR1 VDDC AA24
VDDR1 VDDC
120ohm 1 1 LV8 Y7 VDDR1 VDDC
AA27
AB16
CV89
CV90
CV91
0_0402_5%
10U_0603_6.3V6M
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1u 1 1 VDDC AB18
1 1 1 VDDC
AB21
1u 1 3 VDDC AB23 +VGA_CORE
VDDC
10u 1 1 LEVEL AB26
2 2 2 VDDC
PX@
PX@
@
TRANSLATION AB28
AF26 VDDC AC17
+VDDC_CT VDD_CT VDDC
AF27 VDD_CT AC20
AG26 VDDC AC22
VDD_CT VDDC
AG27 AC24
VDDR3 MarsCRB Design VDD_CT VDDC
AC27
+3VGS +VDDR3 VDDC
120ohm 1 0 VDDC
AD18
AD21
2 (VDDR3:3.3V@25mA) I/O VDDC
2
0.1u 1 0 1 @ 2 +VDDR3 AF23
VDDR3 VDDC
AD23
LV9 AF24 VDDR3 AD26
1u 2 3 AG23
VDDC
AF17
CV92
CV93
CV94
CV95
0_0402_5%
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDDR3 VDDC
10u 0 1 1 1 1 1 AG24 AF20
VDDR3 VDDC
AF22
VDDC AG16
DVP VDDC
AD12 VDDR4 AG18
2 2 2 2 VDDC
PX@
PX@
PX@
@
AF11
AF12
VDDR4
VDDR4 VDDC
AH22 VGA_CORE Cap in power side sheet
AF13 VDDR4 AH27
VDDC AH28
VDDC
M26
VDDC
AF15 N24
+1.8VGS +VDDR4 VDDR4 VDDC
@ AG11 R18
LV10 VDDR4 VDDC
( VDDR4:1.8V@300mA) AG13 VDDR4 R21
VDDR4 MarsCRB Design 1 2 +VDDR4 AG15 VDDC R23
VDDR4 VDDC
220ohm 1 1 VDDC
R26
T17
CV96
CV97
0_0603_5%
1U_0402_6.3V6K
0.1U_0402_16V7K
0.1u 1 1 VDDC T20

1 1 VDDC
T22
1u 1 1 VDDC T24
VDDC
10u 1 0 U16
2 2 VDDC
PX@
PX@
U18
VDDC U21
VDDC
U23
VDDC U26
VDDC
V17
VDDC
V20
VDDC V22
VDDC
V24
VDDC V27
VDDC
Y16
VDDC
Y18
VDDC Y21
VDDC
Y23
VDDC Y26
VDDC +VGA_CORE
Y28
3 VDDC 3
(VDDCI:0.9~1.15V@8.8A)
AA13
VDDCI
AB13
VDDCI AC12
VDDCI
AC15
VDDCI
AD13
VDDCI AD16
VDDCI
M15
VDDCI M16
VDDCI
M18
Route as differential pair VOLTAGE VDDCI
M23
CORE I/O
SENESE VDDCI
ISOLATED
N13
VDDCI
<39> AF28 FB_VDDC N15
VCCSENSE_VGA VDDCI N17
VDDCI
N20
VDDCI
AG28 N22
FB_VDDCI VDDCI
TV15 R12
VDDCI
R13
AH29 VDDCI R16
<39> VSSSENSE_VGA FB_GND VDDCI
T12
VDDCI
T15
VDDCI V15
VDDCI
Y13
VDDCI
4 4

ATI_MarsXTX_M2_Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
VAWGA/GB
A B C D E
A B C D E
UV1H
UV1I
PART 3 0F 9
PART 4 0F 9
GDDR5/DDR3
MDA0 C37 G24 MAA0
DQA0_0 MAA0_0/MAA_0 GDDR5/DDR3
MDA1 C35 DQA0_1 MAA0_1/MAA_1 J23 MAA1 MDB0 C5 MAB0_0/MAB_0 P8 MAB0
A35 H24 C3 DQB0_0 T9
MDA2 DQA0_2 MAA0_2/MAA_2 MAA2 MDB1 MAB0_1/MAB_1 MAB1
DQB0_1
MDA3 E34 DQA0_3 MAA0_3/MAA_3 J24 MAA3 MDB2 E3 MAB0_2/MAB_2 P9 MAB2
DQB0_2
MDA4 G32 H26 MAA4 MDB3 E1 N7 MAB3
DQA0_4 MAA0_4/MAA_4 DQB0_3 MAB0_3/MAB_3
MDA5 D33 J26 MAA5 MDB4 F1 N8 MAB4
MDA6 F32 DQA0_6 MAA0_6/MAA_6 H21 MAA6 MDB5 F3 MAB0_5/MAB_5 N9 MAB5
E32 G21 F5 DQB0_5 U9
MDA7 MAA7 MDB6 MAB6
MEMORY INTERFACE A
MDA8 D31 DQA0_8 MAA1_0/MAA_8 H19 MAA8 MDB7 G4 MAB0_7/MAB_7 U8 MAB7
DQB0_7
MDA9 F30 H20 MAA9 MDB8 H5 Y9 MAB8
MDA10 C30 L13 MAA10 MDB9 H6 W9 MAB9
MDA11 A30 DQA0_11 MAA1_3/MAA_11 G16 MAA11 MDB10 J4 MAB1_2/MAB_10 AC8 MAB10
F28 J16 K6 DQB0_10 AC9
MDA12 DQA0_12 MAA1_4/MAA_12 MAA12 MDB11 MAB1_3/MAB_11 MAB11
DQB0_11
MDA13 C28 DQA0_13 MAA1_5/MAA_BA2 H16 A_BA2 MDB12 K5 MAB1_4/MAB_12 AA7 MAB12
1 DQB0_12 1
MDA14 A28 J17 A_BA0 MDB13 L4 AA8 B_BA2
DQA0_14 MAA1_6/MAA_BA0 MDA[0..63] DQB0_13 MAB1_5/BA2
MDA15 E28 H17 A_BA1 MDB14 M6 Y8 B_BA0
DQA0_15 MAA1_7/MAA_BA1 MDA[0..63] <16,17> DQB0_14 MAB1_6/BA0
MDA16 D27 DQA0_16 MDB15 M1 MAB1_7/BA1 AA9 B_BA1
MAA[0..15] DQB0_15
MEMORY INTERFACE B
MDA17 F26 A32 DQMA0 MDB16 M3
DQA0_17 WCKA0_0/DQMA_0 MAA[0..15] <16,17> DQB0_16
MDA18 C26 DQA0_18 WCKA0B_0/DQMA_1 C32 DQMA1 MDB17 M5 H3 DQMB0
A_BA[0..2] DQB0_17 WCKB0_0/DQMB_0
MDA19 A26 D23 DQMA2 MDB18 N4 H1 DQMB1
DQA0_19 WCKA0_1/DQMA_2 A_BA[0..2] <16,17> DQB0_18 WCKB0B_0/DQMB_1
MDA20 F24 E22 DQMA3 MDB19 P6 T3 DQMB2
DQA0_20 WCKA0B_1/DQMA_3 DQB0_19 WCKB0_1/DQMB_2
MDA21 C24 C14 DQMA4 DQMA[0..7] MDB20 P5 T5 DQMB3
DQA0_21 WCKA1_0/DQMA_4 DQMA[0..7] <16,17> DQB0_20 WCKB0B_1/DQMB_3
MDA22 A24 A14 DQMA5 MDB21 R4 AE4 DQMB4
DQA0_22 WCKA1B_0/DQMA_5 DQB0_21 WCKB1_0/DQMB_4
MDA23 E24 E10 DQMA6 QSA[0..7] MDB22 T6 AF5 DQMB5
DQA0_23 WCKA1_1/DQMA_6 QSA[0..7] <16,17> DQB0_22 WCKB1B_0/DQMB_5
MDA24 C22 D9 DQMA7 MDB23 T1 AK6 DQMB6
DQA0_24 WCKA1B_1/DQMA_7 QSA#[0..7] DQB0_23 WCKB1_1/DQMB_6
MDA25 A22 MDB24 U4 AK5 DQMB7
DQA0_25 QSA#[0..7] <16,17> DQB0_24 WCKB1B_1/DQMB_7
MDA26 F22 DQA0_26 C34 QSA0 MDB25 V6
D21 EDCA0_0/QSA_0 D29 V1 DQB0_25 F6
MDA27 DQA0_27 QSA1 MDB26 QSB0
EDCA0_1/QSA_1 DQB0_26 EDCB0_0/QSB_0
MDA28 A20 DQA0_28 D25 QSA2 MDB27 V3 K3 QSB1
EDCA0_2/QSA_2 DQB0_27 EDCB0_1/QSB_1
MDA29 F20 E20 QSA3 MDB28 Y6 P3 QSB2
DQA0_29 EDCA0_3/QSA_3 DQB0_28 EDCB0_2/QSB_2
MDA30 D19 E16 QSA4 MDB29 Y1 V5 QSB3
MDA31 E18 E12 QSA5 MDB[0..63] MDB30 Y3 AB5 QSB4
DQA0_31 EDCA1_1/QSA_5 MDB[0..63] <18,19> DQB0_30 EDCB1_0/QSB_4
MDA32 C18 J10 QSA6 MDB31 Y5 AH1 QSB5
MDA33 A18 D7 QSA7 MAB[0..15] MDB32 AA4 AJ9 QSB6
DQA1_1 EDCA1_3/QSA_7 MAB[0..15] <18,19> DQB1_0 EDCB1_2/QSB_6
MDA34 F18 MDB33 AB6 AM5 QSB7
DQA1_2 B_BA[0..2] DQB1_1 EDCB1_3/QSB_7
MDA35 D17 A34 QSA#0 MDB34 AB1
DQA1_3 DDBIA0_0/QSA_0B B_BA[0..2] <18,19> DQB1_2
MDA36 A16 DQA1_4 E30 QSA#1 MDB35 AB3 G7 QSB#0
F16 DDBIA0_1/QSA_1B E26 DQMB[0..7] AD6 DQB1_3 DDBIB0_0/QSB_0B K1
MDA37 DQA1_5 QSA#2 <18,19> MDB36 QSB#1
DDBIA0_2/QSA_2B DQMB[0..7] DQB1_4 DDBIB0_1/QSB_1B
MDA38 D15 DQA1_6 C20 QSA#3 MDB37 AD1 P1 QSB#2
DDBIA0_3/QSA_3B QSB[0..7] DQB1_5 DDBIB0_2/QSB_2B
MDA39 E14 C16 QSA#4 MDB38 AD3 W4 QSB#3
DQA1_7 DDBIA1_0/QSA_4B QSB[0..7] <18,19> DQB1_6 DDBIB0_3/QSB_3B
MDA40 F14 C12 QSA#5 MDB39 AD5 AC4 QSB#4
DQA1_8 DDBIA1_1/QSA_5B DQB1_7 DDBIB1_0/QSB_4B
MDA41 D13 J11 QSA#6 QSB#[0..7] MDB40 AF1 AH3 QSB#5
DQA1_9 DDBIA1_2/QSA_6B QSB#[0..7] <18,19> DQB1_8 DDBIB1_1/QSB_5B
MDA42 F12 F8 QSA#7 MDB41 AF3 AJ8 QSB#6
DQA1_10 DDBIA1_3/QSA_7B DQB1_9 DDBIB1_2/QSB_6B
MDA43 A12 DQA1_11 MDB42 AF6 AM3 QSB#7
DQB1_10 DDBIB1_3/QSB_7B
MDA44 D11 J21 ODTA0 MDB43 AG4
DQA1_12 ADBIA0/ODTA0 ODTA0 <16> DQB1_11
MDA45 F10 G19 ODTA1 MDB44 AH5 T7 ODTB0
DQA1_13 ADBIA1/ODTA1 ODTA1 <17> DQB1_12 ADBIB0/ODTB0 ODTB0 <18>
MDA46 A10 DQA1_14 MDB45 AH6 W7 ODTB1 <19>
C10 H27 CLKA0 AJ4 DQB1_13 ADBIB1/ODTB1 ODTB1
MDA47 DQA1_15 CLKA0 <16> MDB46
CLKA0 DQB1_14
MDA48 G13 DQA1_16 CLKA0B G27 CLKA0# <16> MDB47 AK3 L9 CLKB0 <18>
CLKA0# DQB1_15 CLKB0 CLKB0
MDA49 H13 MDB48 AF8 L8 CLKB0#
DQA1_17 DQB1_16 CLKB0B CLKB0# <18>
MDA50 J13 J14 CLKA1 MDB49 AF9
DQA1_18 CLKA1 CLKA1 <17> DQB1_17
2 MDA51 H11 DQA1_19 CLKA1B H14 CLKA1# <17> MDB50 AG8 AD8 CLKB1 <19> 2
G10 CLKA1# AG7 DQB1_18 CLKB1 AD7 CLKB1# CLKB1
MDA52 DQA1_20 MDB51 <19>
DQB1_19 CLKB1B CLKB1#
MDA53 G8 DQA1_21 K23 RASA0# <16> MDB52 AK9
RASA0B RASA0# DQB1_20
MDA54 K9 K19 RASA1# MDB53 AL7 T10 RASB0#
DQA1_22 RASA1B RASA1# <17> DQB1_21 RASB0B RASB0# <18>
MDA55 K10 MDB54 AM8 Y10 RASB1#
DQA1_23 DQB1_22 RASB1B RASB1# <19>
MDA56 G9 DQA1_24 K20 CASA0# <16> MDB55 AM7
A8 CASA0B K17 CASA1# CASA0# AK1 DQB1_23 W10 CASB0#
MDA57 DQA1_25 <17> MDB56 <18>
CASA1B CASA1# DQB1_24 CASB0B CASB0#
MDA58 C8 DQA1_26 MDB57 AL4 AA10 CASB1# <19>
DQB1_25 CASB1B CASB1#
MDA59 E8 CSA0B_0 K24 CSA0#_0 MDB58 AM6
DQA1_27 CSA0#_0 <16> DQB1_26
MDA60 A6 CSA0B_1 K27 MDB59 AM1 P10 CSB0#_0
DQA1_28 DQB1_27 CSB0B_0 CSB0#_0 <18>
MDA61 C6 DQA1_29 MDB60 AN4 L10
E6 M13 CSA1#_0 AP3 DQB1_28 CSB0B_1
MDA62 DQA1_30 CSA1B_0 <17> MDB61
CSA1#_0 DQB1_29
MDA63 A5 DQA1_31 CSA1B_1 K16 MDB62 AP1 AD10 CSB1#_0 <19>
DQB1_30 CSB1B_0 CSB1#_0
MDB63 AP5 AC10
L18 K21 CKEA0 DQB1_31 CSB1B_1
+VDD_MEM15_REFDA MVREFDA CKEA0 <16>
CKEA0
+VDD_MEM15_REFSA L20 MVREFSA CKEA1 J20 CKEA1 <17> U10 CKEB0 <18>
CKEA1 CKEB0 CKEB0
+VDD_MEM15_REFDB Y12 AA11 CKEB1
<19>
MVREFDB CKEB1 CKEB1
L27 NC WEA0B K26 WEA0# <16> +VDD_MEM15_REFSB AA12
WEA0# MVREFSB
N12 WEA1B L15 WEA1# N10 WEB0#
NC WEA1# <17> WEB0B WEB0# <18>
AG12 AB11 WEB1#
NC WEB1B WEB1# <19>
H23 MAA13
MAA0_8/MAA_13
1 PX@ 2 M27 MEM_CALRP0 MAA1_8/MAA_14 J19 MAA14 MAB0_8/MAB_13 T8 MAB13
RV47 120_0402_1% M21 MAA15 W8 MAB14
MAA0_9/MAA_15 MAB1_8/MAB_14
M12 M20 U12 MAB15
NC MAA1_9/RSVD MAB0_9/MAB_15
AH12 NC MAB1_9/RSVD V12
DRAM_RST AH11 DRAM_RST#_R
MARS@ MARS-XT M2_FCBGA962 MARS@ MARS-XT M2_FCBGA962
3 3
Ball to RV57 < 1"

CV100 to RV57 < 200 mil +1.5VGS
+1.5VGS +1.5VGS CV100 to RV53 < 1" +1.5VGS +1.5VGS
1
RV48
1
1
4.7K_0402_5%
RV49 RV50 @
40.2_0402_1% 40.2_0402_1% RV51 RV52
2
PX@ PX@ 40.2_0402_1% 40.2_0402_1%

PX@ PX@
2
2
+VDD_MEM15_REFDA +VDD_MEM15_REFSA <16,17,18,19> 1 PX@ 2 1 PX@ 2 DRAM_RST#_R +VDD_MEM15_REFDB +VDD_MEM15_REFSB
DRAM_RST#
RV53 51.1_0402_1% RV54 10_0402_5%
1
1
1 1 1 1
1
2
RV56
RV55 CV98 100_0402_1% CV99 CV100 RV58 CV101 RV59 CV102
100_0402_1% 1U_0402_6.3V6K PX@ 1U_0402_6.3V6K 120P_0402_50V9 RV57 100_0402_1% 1U_0402_6.3V6K 100_0402_1% 1U_0402_6.3V6K
2
PX@ 2 PX@ 2 PX@ PX@ 4.99K_0402_1% PX@ 2 PX@ PX@ 2 PX@

2
2
PX@
1
DRAM_RST# is a daisy-chain net that connects to all VRAM

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These
Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
4 4
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

ATI_MarsXTX_M2_MEM IF
C 1.0
VAWGA/GB
A B C D E
5 4 3 2 1
UV6
UV5
+VREFC_A1 M8 E3 MDA24
+VREFC_A0 M8 E3 MDA23 H1 VREFCA DQL0 F7 MDA30
H1 VREFCA DQL0 F7 MDA19 VREFDQ DQL1 F2 MDA27
VREFDQ DQL1 F2 MDA22 MAA0 N3 DQL2 F8 MDA29
MAA0 N3 DQL2 F8 MDA18 MAA1 P7 A0 DQL3 H3 MDA25
MAA1 P7 A0 DQL3 H3 MDA21 MAA2 P3 A1 DQL4 H8 MDA28
MAA2 P3 A1 DQL4 H8 MDA17 MAA3 N2 A2 DQL5 G2 MDA26
MAA3 N2 A2 DQL5 G2 MDA20 MAA4 P8 A3 DQL6 H7 MDA31
MAA4 P8 A3 DQL6 H7 MDA16 MAA5 P2 A4 DQL7
MAA5 P2 A4 DQL7 MAA6 R8 A5
D
MAA6 R8 A5 MAA7 R2 A6 D7 MDA12 D
MAA7 R2 A6 D7 MDA0 MAA8 T8 A7 DQU0 C3 MDA10
MDA[0..31] MAA8 T8 A7 DQU0 C3 MDA5 MAA9 R3 A8 DQU1 C8 MDA14
<15> MDA[0..31] A8 DQU1 A9 DQU2
MAA9 R3 C8 MDA1 MAA10 L7 C2 MDA11
MAA10 L7 A9 DQU2 C2 MDA6 MAA11 R7 A10/AP DQU3 A7 MDA13
<15,17> MAA[15..0] A10/AP DQU3 A11 DQU4
MAA11 R7 A7 MDA3 MAA12 N7 A2 MDA9
MAA12 N7 A11 DQU4 A2 MDA4 MAA13 T3 A12 DQU5 B8 MDA15
<15> DQMA[3..0] A12 DQU5 A13 DQU6
MAA13 T3 B8 MDA2 MAA14 T7 A3 MDA8
MAA14 T7 A13 DQU6 A3 MDA7 MAA15 M7 A14 DQU7
<15> QSA[3..0] A14 DQU7 A15/BA3 +1.5VGS
MAA15 M7
A15/BA3 +1.5VGS
<15> QSA#[3..0]
A_BA0 M2 B2
M2 B2 A_BA1 N8 BA0 VDD D9
<15,17> A_BA0 BA0 VDD BA1 VDD
N8 D9 A_BA2 M3 G7
<15,17> A_BA1 BA1 VDD BA2 VDD
<15,17> M3 G7 K2
A_BA2 BA2 VDD VDD
K2 K8
VDD K8 VDD N1
VDD N1 CLKA0 J7 VDD N9
J7 VDD N9 CLKA0# K7 CK VDD R1
<15> CLKA0 CK VDD CK VDD
<15> K7 R1 CKEA0 K9 R9
CLKA0# CK VDD CKE/CKE0 VDD +1.5VGS
K9 R9
<15> CKEA0 CKE/CKE0 VDD +1.5VGS
ODTA0 K1 A1
K1 A1 CSA0#_0 L2 ODT/ODT0 VDDQ A8
<15> ODTA0 ODT/ODT0 VDDQ CS/CS0 VDDQ
<15> L2 A8 RASA0# J3 C1
CSA0#_0 CS/CS0 VDDQ RAS VDDQ
J3 C1 CASA0# K3 C9
<15> RASA0# RAS VDDQ CAS VDDQ
K3 C9 WEA0# L3 D2
<15> CASA0# CAS VDDQ WE VDDQ
<15> L3 D2 E9
WEA0# WE VDDQ E9 VDDQ F1
VDDQ F1 QSA3 F3 VDDQ H2
QSA2 F3 VDDQ H2 QSA1 C7 DQSL VDDQ H9
QSA0 C7 DQSL VDDQ H9 DQSU VDDQ
DQSU VDDQ
DQMA3 E7 A9
DQMA2 E7 A9 DQMA1 D3 DML VSS B3
DQMA0 D3 DML VSS B3 DMU VSS E1
DMU VSS E1 VSS G8
VSS G8 QSA#3 G3 VSS J2
C C
QSA#2 G3 VSS J2 QSA#1 B7 DQSL VSS J8
QSA#0 B7 DQSL VSS J8 DQSU VSS M1
DQSU VSS M1 VSS M9
VSS M9 VSS P1
VSS P1 DRAM_RST# T2 VSS P9
T2 VSS P9 RESET VSS T1
<15,17,18,19> DRAM_RST# RESET VSS VSS
T1 L8 T9
L8 VSS T9 ZQ/ZQ0 VSS
ZQ/ZQ0 VSS
1
J1 B1
1
J1 B1 RV85 L1 NC/ODT1 VSSQ B9
RV84 L1 NC/ODT1 VSSQ B9 J9 NC/CS1 VSSQ D1
NC/CS1 VSSQ 240_0402_1% NC/CE1 VSSQ
240_0402_1% J9 D1 MARS@ L9 D8
L9 NC/CE1 VSSQ D8 NCZQ1 VSSQ E2
2
MARS@ NCZQ1 VSSQ E2 VSSQ E8
2
VSSQ E8 VSSQ F9
VSSQ F9 VSSQ G1
VSSQ G1 VSSQ G9
VSSQ G9 VSSQ
VSSQ 96-BALL
96-BALL SDRAM DDR3
SDRAM DDR3 K4W1G1646E-HC12_FBGA96
K4W1G1646E-HC12_FBGA96 X76@
CLKA0 1 MARS@ 2 X76@
RV60 40.2_0402_1%
CLKA0# 1 MARS@ 2
RV61 40.2_0402_1%
1
CV195 +1.5VGS
0.01U_0402_25V7K +1.5VGS
MARS@
2
1
MARS@
1
MARS@ RV63
RV62 4.99K_0402_1%
4.99K_0402_1%
B B
15mil
2
15mil
2
+VREFC_A1
+VREFC_A0
0.1U_0402_16V7K
CV104
MARS@
1
1
0.1U_0402_16V7K
CV103
MARS@ RV65
1
RV64 4.99K_0402_1%
4.99K_0402_1% MARS@
2
MARS@
2
2
2
+1.5VGS
+1.5VGS +1.5VGS
10U_0603_6.3V6M
CV105
1U_0402_6.3V6K
CV106
1U_0402_6.3V6K
CV107
1U_0402_6.3V6K
CV108
1U_0402_6.3V6K
CV109
1U_0402_6.3V6K
CV110
0.1U_0402_16V7K
CV111
0.1U_0402_16V7K
CV112
0.1U_0402_16V7K
CV113
0.1U_0402_16V7K
CV114
10U_0603_6.3V6M
CV151
10U_0603_6.3V6M
CV116
1U_0402_6.3V6K
CV117
1U_0402_6.3V6K
CV118
1U_0402_6.3V6K
CV119
1U_0402_6.3V6K
CV120
1U_0402_6.3V6K
CV152
0.1U_0402_16V7K
CV122
0.1U_0402_16V7K
CV164
0.1U_0402_16V7K
CV153
0.1U_0402_16V7K
CV125
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
@
A A

ATI_Whistler_M2_VRAM_A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C VAWGA/GB 1.0
5 4 3 2 1
5 4 3 2 1
UV7
UV8
+VREFC_A2 M8 E3 MDA38
H1 VREFCA DQL0 F7 MDA36 +VREFC_A3 M8 E3 MDA49
VREFDQ DQL1 F2 MDA39 H1 VREFCA DQL0 F7 MDA51
MAA0 N3 DQL2 F8 MDA34 VREFDQ DQL1 F2 MDA48
MAA1 P7 A0 DQL3 H3 MDA35 MAA0 N3 DQL2 F8 MDA52
D
MAA2 P3 A1 DQL4 H8 MDA33 MAA1 P7 A0 DQL3 H3 MDA50 D
MAA3 N2 A2 DQL5 G2 MDA37 MAA2 P3 A1 DQL4 H8 MDA53
MAA4 P8 A3 DQL6 H7 MDA32 MAA3 N2 A2 DQL5 G2 MDA55
MAA5 P2 A4 DQL7 MAA4 P8 A3 DQL6 H7 MDA54
MAA6 R8 A5 MAA5 P2 A4 DQL7
MAA7 R2 A6 D7 MDA42 MAA6 R8 A5
MAA8 T8 A7 DQU0 C3 MDA44 MAA7 R2 A6 D7 MDA60
MAA9 R3 A8 DQU1 C8 MDA40 MAA8 T8 A7 DQU0 C3 MDA57
MAA10 L7 A9 DQU2 C2 MDA46 MAA9 R3 A8 DQU1 C8 MDA63
MAA11 R7 A10/AP DQU3 A7 MDA43 MAA10 L7 A9 DQU2 C2 MDA56
MAA12 N7 A11 DQU4 A2 MDA45 MAA11 R7 A10/AP DQU3 A7 MDA61
MDA[32..63] MAA13 T3 A12 DQU5 B8 MDA41 MAA12 N7 A11 DQU4 A2 MDA59
<15> MDA[32..63] A13 DQU6 A12 DQU5
MAA14 T7 A3 MDA47 MAA13 T3 B8 MDA62
MAA15 M7 A14 DQU7 MAA14 T7 A13 DQU6 A3 MDA58
<15,16> MAA[15..0] A15/BA3 +1.5VGS A14 DQU7
MAA15 M7
A15/BA3 +1.5VGS
<15> DQMA[7..4]
A_BA0 M2 B2
<15,16> A_BA0 BA0 VDD
<15> <15,16> A_BA1 N8 D9 A_BA0 M2 B2
QSA[7..4] A_BA1 M3 BA1 VDD G7 N8 BA0 VDD D9
<15,16> A_BA2 A_BA1
A_BA2 BA2 VDD BA1 VDD
<15> K2 A_BA2 M3 G7
QSA#[7..4] VDD BA2 VDD
K8 K2
VDD N1 VDD K8
J7 VDD N9 VDD N1
<15> CLKA1 CK VDD VDD
K7 R1 CLKA1 J7 N9
<15> CLKA1# CK VDD CK VDD
<15> K9 R9 CLKA1# K7 R1
CKEA1 CKE/CKE0 VDD +1.5VGS CK VDD
CKEA1 K9 R9
CKE/CKE0 VDD +1.5VGS
<15> K1 A1
ODTA1 L2 ODT/ODT0 VDDQ A8 K1 A1
<15> ODTA1
CSA1#_0 CS/CS0 VDDQ ODT/ODT0 VDDQ
<15> J3 C1 CSA1#_0 L2 A8
RASA1# RAS VDDQ CS/CS0 VDDQ
K3 C9 RASA1# J3 C1
<15> CASA1# CAS VDDQ RAS VDDQ
L3 D2 CASA1# K3 C9
<15> WEA1# WE VDDQ CAS VDDQ
E9 WEA1# L3 D2
VDDQ F1 WE VDDQ E9
QSA4 F3 VDDQ H2 VDDQ F1
QSA5 C7 DQSL VDDQ H9 QSA6 F3 VDDQ H2
DQSU VDDQ QSA7 C7 DQSL VDDQ H9
DQSU VDDQ
C C
DQMA4 E7 A9
DQMA5 D3 DML VSS B3 DQMA6 E7 A9
DMU VSS E1 DQMA7 D3 DML VSS B3
VSS G8 DMU VSS E1
QSA#4 G3 VSS J2 VSS G8
QSA#5 B7 DQSL VSS J8 QSA#6 G3 VSS J2
DQSU VSS M1 QSA#7 B7 DQSL VSS J8
VSS M9 DQSU VSS M1
VSS P1 VSS M9
DRAM_RST# T2 VSS P9 VSS P1
<15,16,18,19> DRAM_RST# RESET VSS VSS
T1 DRAM_RST# T2 P9
L8 VSS T9 RESET VSS T1
ZQ/ZQ0 VSS L8 VSS T9
ZQ/ZQ0 VSS
1
J1 B1
1
RV86 L1 NC/ODT1 VSSQ B9 J1 B1
J9 NC/CS1 VSSQ D1 RV87 L1 NC/ODT1 VSSQ B9
240_0402_1% NC/CE1 VSSQ NC/CS1 VSSQ
L9 D8 240_0402_1% J9 D1
MARS@ NCZQ1 VSSQ E2 MARS@ L9 NC/CE1 VSSQ D8
2
VSSQ E8 NCZQ1 VSSQ E2
2
VSSQ F9 VSSQ E8
VSSQ G1 VSSQ F9
VSSQ G9 VSSQ G1
VSSQ VSSQ G9
96-BALL VSSQ
SDRAM DDR3 96-BALL
K4W1G1646E-HC12_FBGA96 SDRAM DDR3
X76@ K4W1G1646E-HC12_FBGA96
X76@
+1.5VGS
B B
+1.5VGS
1
MARS@
CLKA1 1 MARS@ 2 RV67
1
RV66 40.2_0402_1% MARS@ 4.99K_0402_1%

RV68
4.99K_0402_1%
15mil
2
CLKA1# 1 MARS@ 2
RV69 40.2_0402_1% +VREFC_A3
15mil
2
1
CV196
0.1U_0402_16V7K
CV126
0.01U_0402_25V7K +VREFC_A2 MARS@
1
MARS@ RV70
2
0.1U_0402_16V7K
CV127
MARS@ 4.99K_0402_1%
1
RV71 MARS@
2
4.99K_0402_1%
2
MARS@
2
2
+1.5VGS
+1.5VGS +1.5VGS
10U_0603_6.3V6M
CV128
1U_0402_6.3V6K
CV129
1U_0402_6.3V6K
CV130
1U_0402_6.3V6K
CV131
1U_0402_6.3V6K
CV132
1U_0402_6.3V6K
CV133
0.1U_0402_16V7K
CV134
0.1U_0402_16V7K
CV135
0.1U_0402_16V7K
CV136
0.1U_0402_16V7K
CV137
10U_0603_6.3V6M
CV138
10U_0603_6.3V6M
CV139
1U_0402_6.3V6K
CV140
1U_0402_6.3V6K
CV141
1U_0402_6.3V6K
CV142
1U_0402_6.3V6K
CV143
1U_0402_6.3V6K
CV144
0.1U_0402_16V7K
CV145
0.1U_0402_16V7K
CV146
0.1U_0402_16V7K
CV147
0.1U_0402_16V7K
CV148
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
MARS@
@
A A

5 4 3 2 1
5 4 3 2 1
UV9 UV10
+VREFC_B0 M8 E3 MDB19 +VREFC_B1 M8 E3 MDB26

H1 VREFCA DQL0 F7 MDB20 H1 VREFCA DQL0 F7 MDB30
VREFDQ DQL1 F2 MDB22 VREFDQ DQL1 F2 MDB24
MAB0 N3 DQL2 F8 MDB16 MAB0 N3 DQL2 F8 MDB29
MAB1 P7 A0 DQL3 H3 MDB23 MAB1 P7 A0 DQL3 H3 MDB27
MAB3 N2 A2 DQL5 G2 MDB21 MAB3 N2 A2 DQL5 G2 MDB25
MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
D
MAB6 R8 A5 MAB6 R8 A5 D
MAB7 R2 A6 D7 MDB0 MAB7 R2 A6 D7 MDB15
MAB8 T8 A7 DQU0 C3 MDB4 MAB8 T8 A7 DQU0 C3 MDB10
MAB9 R3 A8 DQU1 C8 MDB1 MAB9 R3 A8 DQU1 C8 MDB14
MAB10 L7 A9 DQU2 C2 MDB6 MAB10 L7 A9 DQU2 C2 MDB11
MAB11 R7 A10/AP DQU3 A7 MDB3 MAB11 R7 A10/AP DQU3 A7 MDB12
MAB12 N7 A11 DQU4 A2 MDB7 MAB12 N7 A11 DQU4 A2 MDB9
MAB13 T3 A12 DQU5 B8 MDB2 MAB13 T3 A12 DQU5 B8 MDB13
MDB[0..31] MAB14 T7 A13 DQU6 A3 MDB5 MAB14 T7 A13 DQU6 A3 MDB8
<15> MDB[0..31] A14 DQU7 A14 DQU7
MAB15 M7 MAB15 M7
A15/BA3 +1.5VGS A15/BA3 +1.5VGS
<15,19> MAB[15..0]
<15> <15,19> M2 B2 B_BA0 M2 B2

DQMB[3..0] B_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9
<15,19> B_BA1
B_BA1 BA1 VDD BA1 VDD
<15> <15,19> M3 G7 B_BA2 M3 G7
QSB[3..0] B_BA2 BA2 VDD BA2 VDD
K2 K2
VDD K8 VDD K8
<15> QSB#[3..0] VDD VDD
N1 N1
J7 VDD N9 CLKB0 J7 VDD N9
<15> CLKB0 CK VDD CK VDD
<15> K7 R1 CLKB0# K7 R1
CLKB0# CK VDD CK VDD
K9 R9 CKEB0 K9 R9
<15> CKEB0 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
K1 A1 ODTB0 K1 A1
<15> ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
<15> L2 A8 CSB0#_0 L2 A8
CSB0#_0 CS/CS0 VDDQ CS/CS0 VDDQ
J3 C1 RASB0# J3 C1
<15> RASB0# RAS VDDQ RAS VDDQ
K3 C9 CASB0# K3 C9
<15> CASB0# CAS VDDQ CAS VDDQ
<15> L3 D2 WEB0# L3 D2
WEB0# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1
QSB2 F3 VDDQ H2 QSB3 F3 VDDQ H2
QSB0 C7 DQSL VDDQ H9 QSB1 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ
DQMB2 E7 A9 DQMB3 E7 A9
DQMB0 D3 DML VSS B3 DQMB1 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
C C
QSB#2 G3 VSS J2 QSB#3 G3 VSS J2
QSB#0 B7 DQSL VSS J8 QSB#1 B7 DQSL VSS J8
CLKB0 1 PX@ 2 DQSU VSS M1 DQSU VSS M1
RV72 40.2_0402_1% VSS M9 VSS M9
VSS P1 VSS P1
T2 VSS P9 DRAM_RST# T2 VSS P9
<15,16,17,19> DRAM_RST# RESET VSS RESET VSS
CLKB0# 1 PX@ 2 T1 T1
RV73 40.2_0402_1% L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
CV197
1
0.01U_0402_25V7K J1 B1 J1 B1
PX@ RV88 L1 NC/ODT1 VSSQ B9 RV89 L1 NC/ODT1 VSSQ B9
2
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1

240_0402_1% NC/CE1 VSSQ 240_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8
PX@ NCZQ1 VSSQ E2 PX@ NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@
+1.5VGS
+1.5VGS
1
PX@
1
PX@ RV75
RV74 4.99K_0402_1%
4.99K_0402_1%
15mil
2
B B
15mil
2
+VREFC_B1
+VREFC_B0
0.1U_0402_16V7K
CV150
PX@
1
1
0.1U_0402_16V7K
CV149
PX@ RV77
1
RV76 4.99K_0402_1%
4.99K_0402_1% PX@
2
PX@
2
2
2
+1.5VGS
+1.5VGS +1.5VGS
10U_0603_6.3V6M
CV115
1U_0402_6.3V6K
CV121
1U_0402_6.3V6K
CV124
1U_0402_6.3V6K
CV191
1U_0402_6.3V6K
CV155
1U_0402_6.3V6K
CV156
0.1U_0402_16V7K
CV157
0.1U_0402_16V7K
CV158
0.1U_0402_16V7K
CV159
0.1U_0402_16V7K
CV160
10U_0603_6.3V6M
CV161
10U_0603_6.3V6M
CV162
1U_0402_6.3V6K
CV163
1U_0402_6.3V6K
CV123
1U_0402_6.3V6K
CV165
1U_0402_6.3V6K
CV166
1U_0402_6.3V6K
CV167
0.1U_0402_16V7K
CV168
0.1U_0402_16V7K
CV169
0.1U_0402_16V7K
CV170
0.1U_0402_16V7K
CV72
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
A A

ATI_Whistler_M2_VRAM_B
5 4 3 2 1
5 4 3 2 1
UV11 UV12
+VREFC_B2 M8 E3 MDB33 +VREFC_B3 M8 E3 MDB55

H1 VREFCA DQL0 F7 MDB37 H1 VREFCA DQL0 F7 MDB50
VREFDQ DQL1 F2 MDB35 VREFDQ DQL1 F2 MDB54
MAB0 N3 DQL2 F8 MDB39 MAB0 N3 DQL2 F8 MDB51
MAB3 N2 A2 DQL5 G2 MDB34 MAB3 N2 A2 DQL5 G2 MDB52
MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
MAB6 R8 A5 MAB6 R8 A5
MAB7 R2 A6 D7 MDB44 MAB7 R2 A6 D7 MDB56
D
MAB8 T8 A7 DQU0 C3 MDB41 MAB8 T8 A7 DQU0 C3 MDB59 D
MDB[32..63] MAB9 R3 A8 DQU1 C8 MDB47 MAB9 R3 A8 DQU1 C8 MDB63
<15> MDB[32..63] A9 DQU2 A9 DQU2
MAB10 L7 C2 MDB43 MAB10 L7 C2 MDB62
MAB11 R7 A10/AP DQU3 A7 MDB45 MAB11 R7 A10/AP DQU3 A7 MDB57
<15,18> MAB[15..0] A11 DQU4 A11 DQU4
MAB12 N7 A2 MDB40 MAB12 N7 A2 MDB61
MAB13 T3 A12 DQU5 B8 MDB46 MAB13 T3 A12 DQU5 B8 MDB58
<15> DQMB[7..4] A13 DQU6 A13 DQU6
MAB14 T7 A3 MDB42 MAB14 T7 A3 MDB60
MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7
<15> QSB[7..4] A15/BA3 +1.5VGS A15/BA3 +1.5VGS
<15> QSB#[7..4]
B_BA0 M2 B2 B_BA0 M2 B2
<15,18> B_BA0 BA0 VDD BA0 VDD
B_BA1 N8 D9 B_BA1 N8 D9
<15,18> B_BA1 BA1 VDD BA1 VDD
<15,18> B_BA2 M3 G7 B_BA2 M3 G7
B_BA2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8
VDD N1 VDD N1
J7 VDD N9 CLKB1 J7 VDD N9
<15> CLKB1 CK VDD CK VDD
<15> K7 R1 CLKB1# K7 R1
CLKB1# K9 CK VDD R9 K9 CK VDD R9
<15> CKEB1
CKEB1 CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
K1 A1 ODTB1 K1 A1
<15> ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
<15> L2 A8 CSB1#_0 L2 A8
CSB1#_0 J3 CS/CS0 VDDQ C1 J3 CS/CS0 VDDQ C1
<15> RASB1#
RASB1# RAS VDDQ RAS VDDQ
<15> K3 C9 CASB1# K3 C9
CASB1# CAS VDDQ CAS VDDQ
L3 D2 WEB1# L3 D2
<15> WEB1# WE VDDQ WE VDDQ
E9 E9
VDDQ F1 VDDQ F1
QSB4 F3 VDDQ H2 QSB6 F3 VDDQ H2
QSB5 C7 DQSL VDDQ H9 QSB7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ
DQMB4 E7 A9 DQMB6 E7 A9
DQMB5 D3 DML VSS B3 DQMB7 D3 DML VSS B3
DMU VSS E1 DMU VSS E1
VSS G8 VSS G8
QSB#4 G3 VSS J2 QSB#6 G3 VSS J2
QSB#5 B7 DQSL VSS J8 QSB#7 B7 DQSL VSS J8
C C
DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
DRAM_RST# T2 VSS P9 DRAM_RST# T2 VSS P9
<15,16,17,18> DRAM_RST# RESET VSS RESET VSS
T1 T1
L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1
1
J1 B1 J1 B1
RV90 L1 NC/ODT1 VSSQ B9 RV91 L1 NC/ODT1 VSSQ B9
J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1
240_0402_1% NC/CE1 VSSQ 240_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8
PX@ NCZQ1 VSSQ E2 PX@ NCZQ1 VSSQ E2
2
2
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
K4W1G1646E-HC12_FBGA96 K4W1G1646E-HC12_FBGA96
X76@ X76@
+1.5VGS
+1.5VGS
1
PX@
RV78
1
CLKB1 1 PX@ 2 PX@ 4.99K_0402_1%

RV79 40.2_0402_1% RV80
4.99K_0402_1%
15mil
2
CLKB1# 1 PX@ 2
RV81 40.2_0402_1% +VREFC_B3
15mil
2
1
1
B B
0.1U_0402_16V7K
CV172
CV198 +VREFC_B2 PX@
1
0.01U_0402_25V7K RV82
1
0.1U_0402_16V7K
CV173
PX@ PX@ 4.99K_0402_1%

2
RV83 PX@
2
4.99K_0402_1%
2
PX@
2
2
+1.5VGS
+1.5VGS +1.5VGS
10U_0603_6.3V6M
CV174
1U_0402_6.3V6K
CV175
1U_0402_6.3V6K
CV176
1U_0402_6.3V6K
CV177
1U_0402_6.3V6K
CV178
1U_0402_6.3V6K
CV179
0.1U_0402_16V7K
CV180
0.1U_0402_16V7K
CV181
0.1U_0402_16V7K
CV182
0.1U_0402_16V7K
CV183
10U_0603_6.3V6M
CV184
10U_0603_6.3V6M
CV185
1U_0402_6.3V6K
CV186
1U_0402_6.3V6K
CV187
1U_0402_6.3V6K
CV188
1U_0402_6.3V6K
CV189
1U_0402_6.3V6K
CV190
0.1U_0402_16V7K
CV154
0.1U_0402_16V7K
CV192
0.1U_0402_16V7K
CV193
0.1U_0402_16V7K
CV194
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
PX@
@
A A

5 4 3 2 1
5 4 3 2 1
+5V_Display
U73
+3VS
+5VS 3
W=40mils
OUT
1
1
IN C543
1
2
C544 GND 0.1U_0402_16V7K 2
0.1U_0402_16V7K 2 AP2330W-7_SC59-3
D D
HDMI@
1
HDMI@ C R434
Q87 2 1 2
MMBT3904_NL_SOT23-3 B 150K_0402_5%
2
E
2
<4> HDMI_DET
@ HDMI@ R1470 R1471 HDMI@
1
R894 2.2K_0402_5% 2.2K_0402_5%
HDMI@ 200K_0402_5%
1
<4> DP2_TXP0 C51 HDMI@ 1 2 0.1U_0402_16V7K HDMI_TX2P R898
DP2_TXP0
1
<4> DP2_TXN0 C52 HDMI@ 1 2 0.1U_0402_16V7K HDMI_TX2N 100K_0402_5% JHDMI1
DP2_TXN0 19
HDMI_DET_R
2
DP2_TXP1 C53 HDMI@ 1 2 0.1U_0402_16V7K HDMI_TX1P 18 HP_DET
<4> DP2_TXP1 +5V_Display +5V
<4> DP2_TXN1 C54 HDMI@ 1 2 0.1U_0402_16V7K HDMI_TX1N 17
DP2_TXN1 DDC/CEC_GND
HDMIDAT_R 16
DP2_TXP2 C55 HDMI@ 1 2 0.1U_0402_16V7K HDMI_TX0P HDMICLK_R 15 SDA
<4> DP2_TXP2
DP2_TXN2 C56 HDMI@ 1 2 0.1U_0402_16V7K HDMI_TX0N
Close to HDMI connector 14 SCL
<4> DP2_TXN2 Reserved
13
DP2_TXP3 C57 HDMI@ 1 2 0.1U_0402_16V7K HDMI_CLKP HDMI_CLK-_CONN 12 CEC 20
<4> DP2_TXP3 CK- G1
<4> DP2_TXN3 C5888 HDMI@ 1 2 0.1U_0402_16V7K HDMI_CLKN D1 ESDU@ 11 21
DP2_TXN3 1 9 10 CK_shield G2 22
HDMI_TX2+_CONN HDMI_TX2+_CONN HDMI_CLK+_CONN
HDMI_TX0-_CONN 9 CK+ G3 23
HDMI_TX2-_CONN 2 8 HDMI_TX2-_CONN 8 D0- G4
C D0_shield C
HDMI_TX0+_CONN 7
WCM-2012HS-900T HDMI_TX1+_CONN 4 7 HDMI_TX1+_CONN HDMI_TX1-_CONN 6 D0+
HDMI_CLKP 4 3 HDMI_CLK+_CONN 5 D1-
4 3 HDMI_TX1-_CONN 5 6 HDMI_TX1-_CONN HDMI_TX1+_CONN 4 D1_shield
HDMI_TX2-_CONN 3 D1+
HDMI_CLKN 1 2 HDMI_CLK-_CONN 2 D2-
1 2 HDMI_TX2+_CONN 1 D2_shield
L30 EMIP@ 3 D2+
SUYIN_100042GR019M23DZL
WCM-2012HS-900T TVWDF1004AD0_DFN9 ME@
HDMI_TX0P 4 3 HDMI_TX0+_CONN
4 3
HDMI_TX0N 1 2 HDMI_TX0-_CONN
1 2 D2 ESDU@
L31 EMIP@ HDMI_TX0+_CONN 1 9 HDMI_TX0+_CONN
EMIP@ L39 HDMI_TX0-_CONN 2 8 HDMI_TX0-_CONN

HDMI_TX1P 2 1 HDMI_TX1+_CONN HDMI_CLK-_CONN R432 1 HDMI@ 2 499_0402_1%
2 1 HDMI_CLK+_CONN 4 7 HDMI_CLK+_CONN
HDMI_CLK+_CONN R433 1 HDMI@ 2 499_0402_1%
HDMI_TX1N 3 4 HDMI_TX1-_CONN HDMI_CLK-_CONN 5 6 HDMI_CLK-_CONN
3 4 HDMI_TX1-_CONN R435 1 HDMI@ 2 499_0402_1%
B WCM-2012HS-900T B
HDMI_TX1+_CONN R436 1 HDMI@ 2 499_0402_1%
EMIP@ L40 3
HDMI_TX2P 2 1 HDMI_TX2+_CONN HDMI_TX0-_CONN R439 1 HDMI@ 2 499_0402_1%
2 1 TVWDF1004AD0_DFN9
HDMI_TX2N 3 4 HDMI_TX2-_CONN
3 4 HDMI_TX2-_CONN R441 1 HDMI@ 2 499_0402_1%
WCM-2012HS-900T HDMICLK_R
HDMIDAT_R
+3VS
3
HDMI CLK DATA Pull high D69
1
D
in Page 22 for 8P4R L30ESDL5V0C3-2_SOT23-3
ESDU@ +3VS 2 Q76
Q75A G 2N7002K_SOT23-3
HDMI@ S HDMI@
3
2
DMN66D0LDW-7_SOT363-6
<22,4> HDMI_CLK HDMI_CLK 1 6 HDMICLK_R

1
5
A A
HDMI_DATA 4 3 HDMIDAT_R
<22,4> HDMI_DATA
Q75B
HDMI@ Security Classification Compal Secret Data Compal Electronics, Inc.
DMN66D0LDW-7_SOT363-6 2012/04/22 2015/04/22 Title
HDMI CONN
B 1.0
VAWGA/GB
5 4 3 2 1
5 4 3 2 1
LCD POWER CIRCUIT

CMOS Camera
+3VS
W=60mils @
2 1
+3VS +LCDVDD_CONN R694 0_0402_5%
W=60mils
U72
D 1 +LCDVDD_CONN D
5 VOUT
4.7U_0603_6.3V6K
CMOS@ +3VS_CMOS
VIN Q70
PMV65XP_SOT23-3
C522
2 1
4 GND
SS (40 MIL) (40 MIL)
D
3 1 10U
1 3 1
EN 2 @
1
C16 APL3512ABI-TRG_SOT23-5 CMOS@ C1153
G
2
1500P_0402_50V7K C1152 R02 10U_0603_6.3V6M
2 R1458 CMOS@ 0.1U_0402_16V4Z 2
150K_0402_5% 2
<28> CMOS_ON#
<4> APU_ENVDD 1
C1155 CMOS@
2
0.1U_0402_16V4Z
R652 2
100K_0402_5%
1
C C
VGA LCD/PANEL BD. Conn.

+LEDVDD B+
1 @ 2
1 1 R813 0_0805_5%
C1158
680P_0402_50V7K C1159
EMIU@ 4.7U_0805_25V6-K
2 2
JLVDS1
1
2 1 31
3 2 G1 32
4 3 G2 33
Add for protect BKOFF# damage 5 4 G3 34
Use APU control for WIN8 R1466 1 2 0_0402_5% 6 5 G4
BKOFF# 7 6
R1463 1 @ 2 0_0402_5% INVT_PWM 8 7
<4> APU_INVT_PWM 8
9
10 9
B <4> LVDS_ACLK 10 B
11
<4> LVDS_ACLK# 11
12
13 12
<4> LVDS_A2 13
1
14
<4> LVDS_A2# 14
15
<4> LVDS_A1 15
BKOFF# R826 16
<28> BKOFF# <4> LVDS_A1# 16
100K_0402_5% 17
<4> LVDS_A0 17
18
<4>
2
LVDS_A0# 18
1
EDID_DATA 19
<4> 19
EDID_CLK 20
<4> 20
R899 21
+3VS 21
10K_0402_5% 1 22
+LCDVDD_CONN 22
(60 MIL) 23
2
680P_0402_50V7K 24 23
+3VS 24
C1160 EMIU@ 25
2 26 25
+3VS_CMOS 26
USB20_P3_R 27
USB20_N3_R 28 27
29 28
30 29
CMOS 30
0_0402_5%
USB20_P3 USB20_P3 2 @ 1 R696 USB20_P3_R
<5>
USB20_N3 USB20_N3 2 @ 1 R695 USB20_N3_R ACES_88341-3001 ME@
<5>
0_0402_5%
L58 EMIU@
USB20_P3 1 2 USB20_P3_R
1 2
USB20_N3 4 3 USB20_N3_R
A 4 3 A
WCM-2012-900T_4P

LVDS CONN / Camera
Size
Document Number Rev
B 1.0
VAWGA/GB
5 4 3 2 1
A B C D E
FCM1608CF-121T03 0603
<4> DAC_RED EMIP@ 1 2 RED
DAC_RED
L36
FCM1608CF-121T03 0603
<4> DAC_GRN EMIP@ 1 2 GREEN
DAC_GRN
L37
FCM1608CF-121T03 0603
1 DAC_BLU EMIP@ 1 2 BLUE 1
<4> DAC_BLU
L38
1
RP22
8 1 DAC_BLU C1107
7 2 DAC_GRN 6P_0402_50V8
2
6 3 DAC_RED
5 4 C1094 C1103 C1104 C1105 C1106
6P_0402_50V8 6P_0402_50V8 6P_0402_50V8 6P_0402_50V8 6P_0402_50V8
150_0804_8P4R_1%
+3VS
2 2
RP1
HDMI_CLK 1 8 +5V_Display
<20,4> HDMI_CLK
HDMI_DATA 2 7
<20,4> HDMI_DATA
CRT_DDC_DAT_CONN 3 6
CRT_DDC_CLK_CONN 4 5
4.7K_8P4R_5%
+5VS 1
ESDP@ C600
1000P_0402_50V7K
2
+5V_Display
1
C529
U10
0.1U_0402_16V7K
2 1 8 1 2
VCC_SYNC BYP C23 0.22U_0402_10V6K JCRT1
6
2 3 RED 11
+3VS VCC_VIDEO VIDEO1 T49
3 RED 1 3
7
7 4 GREEN CRT_DDC_DAT_CONN 12
VCC_DDC VIDEO2 GREEN 2
1 8 16
G
CRT_DDC_DATA 10 5 BLUE JVGA_HS 13 17
<4> DDC_IN1 VIDEO3 G
C537 BLUE 3
0.1U_0402_16V7K 9
2 11 9 CRT_DDC_DAT_CONN JVGA_VS 14
<4> CRT_DDC_CLK DDC_IN2 DDC_OUT1 4
T58
10
<4> 13 12 CRT_DDC_CLK_CONN CRT_DDC_CLK_CONN 15
CRT_VSYNC SYNC_IN1 DDC_OUT2 5
15 14 JVGA_VS_U R106 1 EMIP@ 2 22_0402_5% JVGA_VS CONTE_80431-5K1-152

<4> CRT_HSYNC SYNC_IN2 SYNC_OUT1 ME@
6 16 JVGA_HS_U R107 1 EMIP@ 2 22_0402_5% JVGA_HS

GND SYNC_OUT2
10P_0402_50V8J
10P_0402_50V8J
TPD7S019-15DBQR_SSOP16 R106 R107 for EMI @
1
@
1
C411
C412
2 2
4 +3VS 4
R693 1 2 4.7K_0402_5% CRT_DDC_DATA

R697 1 2 4.7K_0402_5% CRT_DDC_CLK 2012/04/22 2015/04/22 Title
CRT CONN
B 1.0
VAWGA/GB
A B C D E
A B C D E F G H
SATA HDD Conn.

JHDD1
1
0.01U_0402_25V7K 2 1 C137 SATA_ATX_C_DRX_P0 2 GND
<5> SATA_ATX_DRX_P0 RX+
<5> SATA_ATX_DRX_N0 0.01U_0402_25V7K 2 1 C138 SATA_ATX_C_DRX_N0 3
4 RX-
SATA_DTX_C_ARX_N0 C596 1 2 0.01U_0402_25V7K SATA_DTX_ARX_N0 5 GND
<5> SATA_DTX_C_ARX_N0 TX-
SATA_DTX_C_ARX_P0 C597 1 2 0.01U_0402_25V7K SATA_DTX_ARX_P0 6
<5> SATA_DTX_C_ARX_P0 TX+
7
GND
1 1
8
1 2 +3V_HDD 9 3.3V
+3VS 10 3.3V
R551 0_0805_5%
@ 11 3.3V
12 GND
13 GND
14 GND
1 2 +5V_HDD 15 5V
+5VS 16 5V
R550 0_0805_5%
@ 17 5V
18 GND
19 Reserved
+5V_HDD 10U 20 GND 23
R02 21 12V GND 24
22 12V GND
12V
1 1 1
SUYIN_127043FB022G278ZR
EMIP@ C598 C599 C602
1000P_0402_50V7K 0.1U_0402_16V4Z 10U_0603_6.3V6M
2 2 2
2 2
FOR 15"
SATA ODD FFC Conn.
JODD2
CAP in Small Board 1
SATA_ATX_DRX_P1 2 1
<5> SATA_ATX_DRX_P1 2
SATA_ATX_DRX_N1 3
<5> SATA_ATX_DRX_N1 3
4
SATA_DTX_C_ARX_N1 5 4
<5> SATA_DTX_C_ARX_N1 5
SATA_DTX_C_ARX_P1 6
<5> SATA_DTX_C_ARX_P1 6
1 2 ODD_DETECT# 7
R710 ZODD@ 0_0402_5% +5V_ODD 8 7
9 8
ODD_DA# 10 9
<28> ODD_DA# 10
R02 11
GND 12
GND
HB_A051020-SAHR21
ME@
Co-lay
3
ODD Power Control FOR 14" 3
1
J@ J6
2 Need OPEN SATA ODD Conn.
1 2 JODD1
+5VALW +5VS
JUMP_43X79 +5V_ODD 1
Q90 SATA_ATX_DRX_P1 14@ C619 1 2 0.01U_0402_25V7K SATA_ATX_C_DRX_P1_14 2 GND
SATA_ATX_DRX_N1 14@ C616 1 2 0.01U_0402_25V7K SATA_ATX_C_DRX_N1_14 3 A+
A-
S
3 1 4
SATA_DTX_C_ARX_N114@ C614 1 2 0.01U_0402_25V7K SATA_DTX_ARX_N1_14 5 GND
B-
1
ZODD@ LP2301ALT1G_SOT23-3 SATA_DTX_C_ARX_P114@ C613 1 2 0.01U_0402_25V7K SATA_DTX_ARX_P1_14 6

7 B+
G
2
ZODD@ R930 GND

10K_0402_5%
1 ODD_DETECT# 8
2
R1110 C642 9 DP
+5V_ODD
1 2 1 2 C641 10 +5V
10U_0603_6.3V6M ODD_DA# 11 +5V
MD
1
200K_0402_5% 2 R02 12 15
ZODD@ 0.1U_0402_16V4Z 13 GND GND 14
OUT
ZODD@ 1 R555 2 GND GND

+3VS
10K_0402_5%
2 ALLTO_C18518-11305-L
<6> ODD_EN IN ZODD@
ZODD@ ME@
GND
Q91
DTC124EKAT146_SC59-3
3
4 4

HDD/ODD/FAN/SCREW
Size
Document Number Rev
B 1.0
VAWGA/GB
A B C D E F G H
A B C D E
+3VALW +3V_LAN
+LX
Layout Notice : Place as close Close together
chip as possible. J10
J@ LL2 LL3 SWR@
1 2 LL1 SWR@
1 2 +LX_R 1 2 +LX FBMA-L11160808601LMA10T_2P FBMA-L11160808601LMA10T_2P
1000P_0402_50V7K
+1.1_AVDDL_L 1 2 +1.1_AVDDL 1 2 +LX_R
10U_0603_6.3V6M
0.1U_0402_16V7K
4.7UH_SIA4012-4R7M_20%
JUMP_43X79
CL1
CL2
0.1U_0402_16V7K
1U_0402_6.3V4Z
4.7U_0603_6.3V6K
1 1
CL4
CL5
CL6
@ Note: Place Close to LAN chip 1 1 1
D
3 1
1 2 2 LL1 DCR< 0.15 ohm 1
CL3
Rate current > 1A
RL3 2 2 2
QL1
G
2
LAN_PWR_ON# 2 @ 1 PMV65XP_SOT23-3~D
<28> LAN_PWR_ON#
2 10U
@
10K_0402_5% CL7 SWR@SWR@SWR@
1
0.1U_0402_16V7K Place close to Pin34
Close to
Pin40
LAN Chip Vendor recommand reserve the
PU resistor close LAN chip
AMD recommand reserve Diode UL1 8172@
RL4 1 @ 2 4.7K_0402_5% +3V_LAN

+3V_LAN
D4
@ AR8172-AL3A-R
2 1 LAN_PERST#
<10,6> APU_PCIE_RST#
0.1U_0402_16V7K
RB751V-40TE17_SOD323-2
1U_0402_6.3V4Z
CL10
CL8
1 @ 2 1 1
R577 0_0402_5%
UL1
2
Place Close to Chip 2 2 2
CL9 1 2 0.1U_0402_16V7K PCIE_DTX_ARX_N1 29 38 RL12 10K_0402_5%
<5> PCIE_DTX_C_ARX_N1 TX_N LED_0 39 2 LDO@ 1 mount RL12 if use LDO modue
CL11 1 2 0.1U_0402_16V7K PCIE_DTX_ARX_P1 30
Atheros LED_1 23
<5> PCIE_DTX_C_ARX_P1 TX_P LED_2
AR8151/AR8161 Place close to Pin16
36
<5> PCIE_ATX_C_DRX_N1 RX_N 12 MDI0-
TRXN0 MDI0- <25>
35 11 MDI0+
<5> PCIE_ATX_C_DRX_P1 RX_P TRXP0 MDI0+ <25>
15 MDI1-
TRXN1 MDI1- <25>
32 14 MDI1+
<5> CLK_PCIE_LAN# REFCLK_N TRXP1 MDI1+ <25>
33 18
<5> CLK_PCIE_LAN REFCLK_P TRXN2 17
LAN_PERST# 2 TRXP2 21
PERST# TRXN3 20
3 TRXP3 Place Close to PIN1
<28> LAN_WAKE# W AKE#
25 10 LAN_RBIAS 1 2 +3V_LAN
26 SMCLK RBIAS RL8 2.37K_0402_1%
SMDATA
Place Close to PIN1
28 1 +3V_LAN
NC VDD33
CL12
CL13
CL14
CL15
CL16
1000P_0402_50V7K
27
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16V7K
1U_0402_6.3V4Z
TESTMODE 1 1 1 1
2
40 +LX
LX +LX
LAN_XTALO 7
1
LAN_XTALI 8 XTLO RL10 30K_0402_5% 2 2 2 2
XTLI 5 +1.7_VDDCT 1 2
VDDCT/ISOLAN +3V_LAN
4
<6> LAN_CLKREQ# CLKREQ# 24
DVDDL/PPS 37 +LX_R 10U
3
+1.1_AVDDL 13 DVDDL_REG/DVDDL 3
+1.1_AVDDL 19 AVDDL +2.7_AVDDH
+1.1_AVDDL 31 AVDDL 16 +3V_LAN
+1.1_AVDDL_L 34 AVDDL AVDDH/AVDD33 22 +2.7_AVDDH
+1.1_AVDDL 6 AVDDL AVDDH 9 +2.7_AVDDH
AVDDL_REG/AVDDL AVDDH_REG
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
CL17
CL18
CL19
CL20
CL21
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1 1 1 1
CL22
CL23
CL24
CL25
CL26
41 1 1 1 1 1
GND
AR8162-AL3A-R_QFN40_5X5
2 2 2 2 2
Near 8162@
2 2 2 2 2
Pin6
Near
Near Near Near Pin9 Near Near
Pin13 Pin19 Pin31 Pin22 Pin37
LAN_XTALI
YL1 LAN_XTALO
4 3
NC OSC
4 1 2 4
OSC NC
1 25MHZ_20PF_FSX3M-25.M20FDO 1
CL28 CL29
15P_0402_50V8J 15P_0402_50V8J
2 2
LAN-AR8151
Custom 1.0
VAWGA/GB
A B C D E
A B C D E
ESDU@
DL1
Place Close to TL1 AZC099-04S.R7G_SOT23-6 Reserve gas tube for EMI go rural solution
MDI1+ 1 4 MDI0+
I/O1 I/O3
DL1 2
GND VDD
5
1 1'S PN:SC300001G00 1
MDI0- 3 6 MDI1-
2'S PN:SC300002E00 I/O2 I/O4
RL14 CL30
1 2 1 2
CHASSIS1_GND
75_0805_5% 10P_0603_50V
EMIP@ EMIP@
2 1
TL1
DLL1
<24> MDI0+ 1 16 MDO0+ BS4200N-C-LV_SMB-F2
MDI0+ 2 TD+ TX+ 15
<24> MDI0- MDO0- EMIGASP@
MDI0- TD- TX-
3 14 MCT
4 CT CT 13
5 NC NC 12
NC NC Place Close to TL1
1 6 11 MCT
MDI1+ 7 CT CT 10 MDO1+
<24> MDI1+ RD+ RX+
EMIP@ CL31 <24> MDI1- 8 9 MDO1-
MDI1- RD- RX-
0.01U_0402_25V7K
2
2
MHPC_NS681612A 2
EMIP@
CL63 1 2 0.1U_0603_50V7K
CL61 1 2 0.1U_0603_50V7K
EMIP@
CHASSIS1_GND
JLAN1
MDO0+ 1
PR1+
MDO0- 2
PR1-
MDO1+ 3
PR2+
MCT 4
PR3+
MCT 5
PR3-
3 MDO1- 6 3
PR2-
MCT 7 9
PR4+ GND 10
MCT 8 GND
PR4- 2 2
SANTA_130456-121 ESDP@ C173 C178 ESDP@
0.1U_0402_16V7K 0.1U_0402_16V7K
CHASSIS1_GND 1 1
ME@
4 4

LAN_Transformer
B 1.0
VAWGA/GB
A B C D E
A B C D E
+3VS +3VS_TS
1 TS@ 2 JTS1
R5583 0_0402_5% 8
7 GND
6 GND
+3VS_TS 6
D
3 1 5
4 5
<5> USB20_N1 4
3
1 <5> USB20_P1 3 1
Q156 2
G
2
@ PMV65XP_SOT23-3~D EC_TS_ON# R726 1 TS@ 2 0_0402_5% TS_RST# 1 2
R5581 1 2 100K_0402_5% 1
0.1U_0402_16V4Z
<28> @
EC_TS_ON#
C1322
1 2 ACES_50208-00601-P01
ME@
C1331
0.1U_0402_16V4Z TS@
2 1
@
2 2
+1.5VS
+3VS_WLAN
Mini-Express Card(WLAN/WiMAX)
JWLN1
<6> R1500 1 @ 2 0_0402_5% APU_PCIE_WLAN_WAKE# 1 2
APU_PCIE_WAKE# 1 2
3 4
5 3 4 6
<6> BT_DISABLE# 5 6
WLAN_CLKREQ# 7 8
<6> WLAN_CLKREQ# 7 8
9 10
11 9 10 12
<5> CLK_PCIE_WLAN# 11 12
<5> 13 14
CLK_PCIE_WLAN 15 13 14 16
17 15 16 18
19 17 18 20
19 20 WL_OFF# <6> +3VS +3VS_WLAN
21 22 APU_PCIE_RST#
21 22 APU_PCIE_RST# <10,6>
<5> 23 24 +3VS_WLAN
PCIE_DTX_C_ARX_N2 25 23 24 26
<5> PCIE_DTX_C_ARX_P2 25 26 J7
3 27 28 J@ 3
29 27 28 30 APU_SCLK0_W R1496 1 2 @ 0_0402_5% 1 2
29 30 APU_SCLK0 <6,8,9> 1 2
31 32 APU_SDATA0_W R1497 1 2 @ 0_0402_5%
<5> PCIE_ATX_C_DRX_N2 31 32 APU_SDATA0 <6,8,9>
<5> 33 34
PCIE_ATX_C_DRX_P2 35 33 34 36 JUMP_43X79
USB20_N5 <5>
+3VS_WLAN 37 35 36 38 USB20_N5
USB20_P5 <5>
37 38 USB20_P5
39 40
41 39 40 42
43 41 42 44
100_0402_1% 45 43 44 46
R1498 47 45 46 48
EC_TX 1 2 49 47 48 50
<28> EC_TX 49 50
EC_RX 1 2 51 52
<28> EC_RX 51 52
R1499
100_0402_1% 53 54
GND1 GND2
BELLW_80003-8041
ME@
<6> 1 2 BT_OFF#_R
BT_OFF#
R1520 1K_0402_5%
For EC to detect
4 4
debug card insert.
2
R1501
100K_0402_5%
1
MINI1 CARD (WLAN) / MINI2 CARD (Option)
B 1.0
VAWGA/GB
A B C D E
5 4 3 2 1
1 R567@ 2 U2DN0_L
Right Ext.USB Conn. <5> USB20_N6
0_0402_5% EMIU@
1 R566 2
<5> 1 R569@ 2U2DP0_L 0_0402_5%
+5VALW USB20_P6
0_0402_5%
+USB_VCCB L51
1 R574 2 4 EMIP@ 3 U2DN0
<5> USB30_N8 4 3
0_0402_5%
R02
U36 RIGHT USB PORT X1 1 R575 2 1 2 U2DP0
D <5> USB30_P8 1 2 D
1 8 0_0402_5%
C713 0.1U_0402_16V4Z 2 GND VOUT 7 WCM-2012-900T_4P
2 1 3 VIN VOUT 6 1 R562 2
4 VIN VOUT 5 0_0402_5%
<28> USB_ON# EN FLG USB_OC0# <6> Colay with USB2.0 only
EMIU@
USB2R@ G547I2P81U_MSOP8
USB2R@ JUSB3 ME@

WCM-2012HS-900T +USB3_VCCA
8 1 2 U3RXDN0
+USB_VCCB GND <5> USB30_MRX_DTX_N0 1 2
W=80mils 7 W=80mils
6
GND
4 3 U3RXDP0 JUSB1
LP1 Port0
6 <5> USB30_MRX_DTX_P0 4 3
+USB_VCCB 5 EMIP@ U3TXDP0 9
EMIUSB2RU@ 4 5 L50 1 SSTX+
1 4 VBUS
C714 1 R900 2 1 0_0402_5% USB20_N0_C 3 U3TXDN0 8
USB2R@ + <5> USB20_N0
R896 2 1 0_0402_5% USB20_P0_C 2 3 U2DP0 3 SSTX-
<5> USB20_P0 2 D+
220U_6.3V_M C715 EMIUSB2RU@ 1 7
470P_0402_50V7K 1 U2DN0 2 GND 10
D- GND
2
6.3ĭ * 5.9 2 2 ACES_88058-060N U3RXDP0 6 11
EMIUSB2RP@ SSRX+ GND
SF000001500 USB2R@ C858 4 12
L66 WCM-2012-900T_4P 0.1U_0402_16V7K WCM-2012HS-900T U3RXDN0 5 GND GND 13
USB20_N0 1 2 USB20_N0_C 1 2 U3TXDN0_L 1 2 U3TXDN0 SSRX- GND
1 2 <5> USB30_MTX_C_DRX_N0 1 2
C
TAITW_PUBAU1-09FNLSCNN4H0 C
ME@
USB20_P0 4 3 USB20_P0_C <5> USB30_MTX_C_DRX_P0 1 2 U3TXDP0_L 4 3 U3TXDP0
4 3 4 3
D25 ESDU@ C859 L49 EMIP@
1
PJDLC05_SOT23-3 0.1U_0402_16V7K
1 R570@ 2 U2DN1_L
<5> USB20_N7
0_0402_5% EMIU@
1 R728 2
1 R571@ 2U2DP1_L 0_0402_5%
<5> USB20_P7
0_0402_5%
L55
1 R572 2 4 EMIP@ 3 U2DN1
<5> USB30_N9 4 3
0_0402_5%
2A/Active Low <5> 1 R573 2 1 2 U2DP1

USB30_P9 1 2
0_0402_5%
+5VALW +USB3_VCCA ESDU@ D27 WCM-2012-900T_4P
U3RXDN0 9 1 U3RXDN0 Colay with USB2.0 only 1 R721 2
C704 U35 R02 W=80mils 0_0402_5%
0.1U_0402_16V4Z 1 8 U3RXDP0 8 2 U3RXDP0 EMIU@
1 2 2 GND VOUT 7
VIN VOUT U3TXDN0 7
B 3 6 4 U3TXDN0 B
USB_ON# 4 VIN VOUT 5
EN FLG USB_OC1# <6>
U3TXDP0 6 5 U3TXDP0
G547I2P81U_MSOP8 WCM-2012HS-900T +USB3_VCCA
3
<5> USB30_MRX_DTX_N1
1
1 2
2 U3RXDN1
W=80mils
U2DP1 3
D34
ESDU@
6
8
4 3 U3RXDP1 JUSB2
LP2 Port1
I/O2 I/O4 <5> USB30_MRX_DTX_P1 4 3
EMIP@ U3TXDP1 9
YSCLAMP0524P_SLP2510P8-10-9 L54 1 SSTX+
U3TXDN1 8 VBUS
2 5 ESDU@ D30 U2DP1 3 SSTX-
GND VDD +5VALW D+
U3RXDN1 9 1 U3RXDN1 7
U2DN1 2 GND 10
U3RXDP1 8 D- GND
2 U3RXDP1 U3RXDP1 6
SSRX+ GND
11
1 4 U2DN1 C856 4 12
I/O1 I/O3 U3TXDN1 7 WCM-2012HS-900T GND GND
4 U3TXDN1 0.1U_0402_16V7K U3RXDN1 5 13
+USB3_VCCA 1 2 U3TXDN1_L 1 2 U3TXDN1 SSRX- GND
AZC099-04S.R7G_SOT23-6 <5> USB30_MTX_C_DRX_N1 1 2
U3TXDP1 6 5 U3TXDP1 TAITW_PUBAU1-09FNLSCNN4H0
ME@
D22
ESDU@ 3
<5> USB30_MTX_C_DRX_P1
1 2 U3TXDP1_L 4 3 U3TXDP1
U2DN0 3 6 4 3
I/O2 I/O4 8 C857 L53 EMIP@
0.1U_0402_16V7K
A A
1 2 5 YSCLAMP0524P_SLP2510P8-10-9
GND VDD +5VALW
1 C735
+
C736 470P_0402_50V7K Security Classification Compal Secret Data Compal Electronics, Inc.
220U_6.3V_M 1 4 U2DP0 2012/04/22 2015/04/22 Title
SF000002Y00 2 2 I/O1 I/O3 Issued Date Deciphered Date
USB2.0 / USB3.0 / BT
AZC099-04S.R7G_SOT23-6 Size Document Number Rev
B 1.0
VAWGA/GB
5 4 3 2 1
5 4 3 2 1
+3VALW Vcc 3.3V +/- 5%

+3VLP
J11
J@
J12
J@
R1562 100K +/- 5%
1 2 1 2 Board ID min typ
1 2 1 2 1
C1254
R1564 VAD_BID V AD_BID VAD_BID max
100P_0402_50V8J
JUMP_43X79 +3V_EC JUMP_43X79 +5VALW
0 0 0 V 0 V 0 V MP
2
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V PVT
L44
FBM-11-160808-601-T_0603 +3V_EC
1 1 1 1 1 1
+EC_VCCA 2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
0.1U_0402_16V4Z
C1255
0.1U_0402_16V4Z
C1256
0.1U_0402_16V4Z
C1257
0.1U_0402_16V4Z
C1258
1000P_0402_50V7K
C1261
1000P_0402_50V7K
C1259
1 2
+3V_EC +EC_VCCA
R1266 33K +/- 5%
1 1
USB_ON# 1 2
3 0.712 V 0.819 V 0.875 V EVT
C1262 C1260 2 2 @2 @2 2 2
D D
0.1U_0402_16V4Z 1000P_0402_50V7K 10K_0402_5% +5VS
111
125
1 2 2 ECAGND 2 +3VALW
22
33
96
67
9
L43 U44
FBM-11-160808-601-T_0603
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
EC_VDD/AVCC
1
R1562 TP_CLK R1568 1 2 4.7K_0402_5%
@ 100K_0402_5%
<6> GATEA20 1 21 ADP_65 <34> TP_DATA R1570 1 2 4.7K_0402_5%
GATEA20 GATEA20/GPIO00 GPIO0F ADP_65
KBRST# 2 23 BEEP#
<6> KBRST# BEEP# <31>
2
SERIRQ 3 KBRST#/GPIO01 BEEP#/GPIO10 26 EC_FAN_PWM
<5> SERIRQ SERIRQ GPIO12 EC_FAN_PWM <29> +3VS
<5,6> LPC_FRAME# 4 27 ACOFF <35>
LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 ACOFF
<5> LPC_AD3 5 MP BRDID
LPC_AD3 LPC_AD3
<5> LPC_AD2 7 PWM Output
LPC_AD2 LPC_AD2
EMIU@ R1560 LPC_AD1 8 63 BATT_TEMP EC_FAN_PWM R1561 1 @ 2 10K_0402_5%
<5> LPC_AD1 LPC_AD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <34>
C1263 2 1 22P_0402_50V8J 2 EMIU@ 1 LPC_AD0 10 LPC & MISC 64 GPU_IMON
<5> LPC_AD0 LPC_AD0 AD1/GPIO39 GPU_IMON <39>
10_0402_5% 65 ADP_I EC_TACH R1581 1 2 10K_0402_5%
ADP_I/AD2/GPIO3A ADP_I <34,35>
<5,6> LPC_CLK0_EC 12 AD Input 66 ADP_ID <33>
LPC_CLK0_EC CLK_PCI_EC AD3/GPIO3B ADP_ID
1
<6> LPC_RST# 13 75 BRDID EC_SMB_DA2 R1579 1 @ 2 2.2K_0402_5%
2 1 LPC_RST# EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76 ENBKL R1564
+3V_EC EC_RST# IMON/AD5/GPIO43 ENBKL <4>
R818 47K_0402_5% <6> EC_SCI# 20 0_0402_5% EC_SMB_CK2 R1578 1 @ 2 2.2K_0402_5%
2 1 EC_SCI# EC_SCII#/GPIO0E
BATT_LEN# 38
<34> BATT_LEN# GPIO1D
C819 0.1U_0402_16V4Z +3V_EC
2
68 ADP_90 <34>
DAC_BRIG/GPIO3C 70 ADP_90
DA Output EN_DFAN1/GPIO3D
KSI0 55 71 EC_SMB_DA1 R1577 1 2 2.2K_0402_5%
KSI1 56 KSI0/GPIO30 IREF/GPIO3E 72
KSI2 57 KSI1/GPIO31 CHGVADJ/GPIO3F EC_SMB_CK1 R1574 1 2 2.2K_0402_5%
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <31>
C KSI4 59 84 USB_ON# <27>
C
KSI4/GPIO34 USB_EN#/GPIO4B USB_ON#
KSI5 60 85 ADP_135
KSI5/GPIO35 CAP_INT#/GPIO4C ADP_135 <34>
KSO[0..17] KSI6 61 PS2 Interface 86
KSO[0..17] <30> KSI6/GPIO36 EAPD/GPIO4D
KSI7 62 87 TP_CLK <30>
KSI[0..7] KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK
<30> KSO0 39 88 TP_DATA <30> +3VALW
KSI[0..7] KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA
KSO1 40
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 EC_TS_ON# EC_MUTE# R1565 1 @ 2 10K_0402_5%
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 EC_TS_ON# <26>
KSO4 43 98
KSO5 44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 095VS_PWR_EN LAN_WAKE# R1566 1 2 10K_0402_5%
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 NTC_V
095VS_PWR_EN <32>
KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 NTC_V <34>
KSO7 46 SPI Device Interface
KSO8 47 KSO7/GPIO27
KSO9 48 KSO8/GPIO28 119 EC_SPI_AISO LID_SW# R344 1 2 47K_0402_5%
KSO9/GPIO29 SPIDI/GPIO5B EC_SPI_AISO <5>
KSO10 49 120 EC_SPI_AOSI <5>
KSO11 50 KSO10/GPIO2A SPIDO/GPIO5C 126 EC_SPI_CLK EC_SPI_AOSI
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 EC_SPI_CLK <5>
KSO12 51 128 EC_SPI_CS1#
KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS1# <5>
KSO13 52
KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E
KSO15/GPIO2F ENBKL/AD6/GPIO40
73 APU_IMON APU_IMON <40>
For share ROM need
KSO16 81 74 VGATE VGATE <40>
KSO17 82 KSO16/GPIO48 PECI_KB930/AD7/GPIO41 89 LAN_PWR_ON# SYS_PWRGD_EC 1 2
KSO17/GPIO49 FSTCHG/GPIO50 LAN_PWR_ON# <24>
90 BATT_CHG_LED# <30> R208 100K_0402_5%
BATT_CHG_LED#/GPIO52 BATT_CHG_LED#
91 CAPS_LED# <30>
CAPS_LED#/GPIO53 CAPS_LED#
<34,35> EC_SMB_CK1 77 GPIO 92 PWR_LED# PWR_LED# <30> 095_18ALW_PWR_EN 1 2
EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54
<34,35> EC_SMB_DA1 78 93 BATT_LOW_LED# <30> R1575 100K_0402_5%
EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# +3VLP
EC_SMB_CK2 79 SM Bus 95 SYSON
<11,29,4> EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON <32,37>
EC_SMB_DA2 80 121 VR_ON @ EC_RSMRST# 1 2
Pull high in APU side <11,29,4> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <40>
1
127 095_18ALW_PWR_EN R1576 100K_0402_5%
B PM_SLP_S4#/GPIO59 095_18ALW_PWR_EN <37,38> B
R343
47K_0402_5%
<6> SLP_S3# 6 100 EC_RSMRST# <6>
SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST#
<6> SLP_S5# 14 101 EC_LID_OUT# BATT_TEMP 1 2
SLP_S5# <6>
2
EC_SMI# 15 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 102 Turbo_V EC_LID_OUT# C1265 100P_0402_50V8J
<6> EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 Turbo_V <34>
<21> CMOS_ON# 16 103 <34> ACIN 1 2
CMOS_ON# GPIO0A H_PROCHOT#_EC/GPXIOA06 PROCHOT
17 104 C1266 100P_0402_50V8J
GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <36>
EC_VGA_EN 18 GPO 105 BKOFF#
Pull high in ODD side<23>
<39> EC_VGA_EN
ODD_DA#
ODD_DA# 19 GPIO0C
GPIO0D GPIO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
106 PBTN_OUT# BKOFF#
PBTN_OUT#
<21>
<6> ACIN 1 @ 2
ADP_ID_CLOSE 25 107 R1573 4.7K_0402_5%
<33> ADP_ID_CLOSE EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10
<29> EC_TACH 28 108
EC_TACH LAN_WAKE# 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
<24> LAN_WAKE# EC_PME#/GPIO15
<26> EC_TX 30
EC_TX EC_TX/GPIO16
EC_RX 31 110 ACIN
<26> EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <11,35>
<6> SYS_PWRGD_EC 32 112 EC_ON <36> 095VS_PWR_EN 1 2
SYS_PWRGD_EC PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON
<30> NOVO# NOVO# 34 114 ON/OFF <30> R207 100K_0402_5%
SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFF
36 GPI 115 LID_SW# <30> ENBKL 1 2
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW#
116 SUSP# 1 <32,37> R206 100K_0402_5%
SUSP#/GPXIOD05 SUSP#
117
GPXIOD06 118 ESDP@ C601
PECI_KB9012/GPXIOD07
AGND/AGND
<6> R836 1 @ 2 0_0402_5% XCLKO 122 1000P_0402_50V7K

RTC_CLK XCLKI/GPIO5D 2
PXS_PWREN 123 124 +V18R
GND/GND
GND/GND
GND/GND
GND/GND
<12,39,6> PXS_PWREN XCLKO/GPIO5E V18R

1 H_PROCHOT# <34,4,40,6>
1
GND0
C823
1
1
R1587 @ C1271 4.7U_0603_6.3V6K D
100K_0402_5% 20P_0402_50V8 KB9012QF-A3_LQFP128_14X14 2 PROCHOT 2 1
2
11
24
35
94
113
69
Part Number = SA00004OB30 20mil G

2
Q82 S C1269
3
A A
2N7002H_SOT23-3 47P_0402_50V8J
2
ECAGND

EC ENE KB930/9012
Custom 1.0
VAWGA/GB
5 4 3 2 1
5 4 3 2 1
+3VGS
SMSC thermal sensor
C329
2 placed near APU
0.1U_0402_16V4Z
@
D 1 D
U9 THERMAL@
1 8 EC_SMB_CK2
<11> REMOTE1+ VDD SCLK EC_SMB_CK2 <11,28,4>
1
REMOTE1+ 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 <11,28,4>
C587 THERMAL@
2200P_0402_50V7K REMOTE1- 3 6
2 D- ALERT#
<11> REMOTE1-
+3VGS 1 R335 2 4 5
THERM# GND
4.7K_0402_5%
@ EMC1402-2-ACZL-TR MSOP 8P
Address is 1001100xb
REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"
C C
CPU VGA_L VGA_R HDD

H1 H2 H3
HOLEA HOLEA HOLEA H4 H5 H18
HOLEA HOLEA HOLEA FD1 FD2 FD3 FD4
1
H_3P8 H_3P8 H_3P8
H_3P3 H_3P3 H_2P8
A B C
B FAN1 Conn B
+5VS H6 H7 H8 H10 H11 R H17

HOLEA HOLEA HOLEA HOLEA HOLEA H16 HOLEA
@ JFAN1 HOLEA
R581 2 1 0_0603_5% +5VS_FAN 1
2 1
<28> EC_TACH
1
3 2
<28> EC_FAN_PWM
1
4 3
5 4
2 G5 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_3P0N
6 H_2P5X3P5N
C591 G6
ACES_85205-04001
㨊⚻⫼ ⚻⫼
1
10U_0603_6.3V6M
ME@ D E F
10U
2P8 * 9 pcd M/B M/B
A A
Security Classification Compal Secret Data Compal Electronics,Ltd.

Fintek-Thermal IC/FAN/screw
B 1.0
VAWGA/GB
5 4 3 2 1
+3VLP
2
KSI[0..7] JKB1 ME@
KSI[0..7] <28>
R643 KSI1 1 JKB2 ME@
@ 100K_0402_5% KSO[0..17] KSI7 2 1 26
KSO[0..17] <28> 2 GND2
KSI6 3 25
SMT1-05_4P SWP1 @ KSO9 4 3 GND1
1
1 3 @ KSI4 5 4 KSI1 24
2 R630 1 KSI5 6 5 KSI7 23 24
2 4 0_0402_5% KSO0 7 6 KSI6 22 23
+3VALW KSI2 8 7 KSO9 21 22
6 KSI3 9 8 KSI4 20 21
5 +3VLP KSO5 10 9 KSI5 19 20
10 19
2
KSO1 11 KSO0 18
R642 KSI0 12 11 KSI2 17 18
12 17
2
SMT1-05_4P SWP0 @ 100K_0402_5% KSO2 13 KSI3 16
1 3 KSO4 14 13 KSO5 15 16
R701 KSO7 15 14 KSO1 14 15
1
2 4 100K_0402_5% D26 KSO8 16 15 KSI0 13 14
NOVO# 2 KSO6 17 16 KSO2 12 13
<28>
1
NOVO# 1 NOVO_BTN# KSO3 18 17 KSO4 11 12
6
5
ON/OFF 3 KSO12 19 18 KSO7 10 11

KSO13 20 19 KSO8 9 10
KSO14 21 20 KSO6 8 9
ON/OFF DAN202UT106_SC70-3 KSO11 22 21 KSO3 7 8
ON/OFF <28> 22 7
KSO10 23 KSO12 6
KSO15 24 23 KSO13 5 6
KSO16 25 24 KSO14 4 5
KSO17 26 25 KSO11 3 4
27 26 KSO10 2 3
28 27 KSO15 1 2
29 28 31 1
30 29 GND 32 ACES_88514-2401
30 GND
ACES_88514-3001
L67 WCM-2012-900T_4P
USB20_N4 1 2 USB20_N4_R
1 2
USB20_P4 4 3 USB20_P4_R
4 EMICP@ 3 +3VS
JCR1
1
USB20_N4 R692 2 EMICU@1
EMICU@ 0_0402_5% USB20_N4_R 2 1
<5> USB20_N4 2
<5>
USB20_P4 R687 2 EMICU@
EMICU@1 0_0402_5% USB20_P4_R 3
USB20_P4 4 3
4
5
GND 6
GND
+5VS
CVILU_CF06041H0RB-NH
ME@
JTP1 ME@
C696
8 +3VALW
0.1U_0402_16V4Z 7 GND
GND
6 2
TP_CLK 5 6
<28> TP_CLK 5
TP_DATA 4 ESDP@ C185
<28> TP_DATA 4
TP_3 3 0.1U_0402_16V7K
TP_2 2 3 1
TP_1 1 2 JPWRB1
1 1
ACES_88058-060N 2 1
<28> LID_SW# 2
NOVO_BTN# 3
ON/OFF 4 3
15@ 5 4
2 R628 1 TP_3 6 5
LED1 14@
6
2
0_0402_5%
PWR_LED# 1 2 2 R623 1 ESDP@ 7
<28> PWR_LED# +5VALW GND
2 R629 1 14@ TP_1 649_0402_1% 8
0_0402_5% D24 GND
14@
19-213A-T1D-CP2Q2HY-3T_WHITE ACES_88058-060N
PJSOT24C 3P C/A SOT-23
1
ME@
15/17" 14"
L R 1 VCC 1 VCC
LED2 14@
BATT_LOW_LED# 1 2 2 R764 1
<28> BATT_LOW_LED# +3VALW
SW4 14@ SW5 14@ 470_0402_5%
TJG-533-V-T/R_6P TJG-533-V-T/R_6P JLED1
2 CLK 2 CLK 14@
5
6
5
6
HT-191UD5_AMBER 1
+5VALW 1
4 2 4 2 2
+3VALW 2
TP_3 TP_2 3
3 1 3 1
3 DAT 3 DAT +5VS
LID_SW# 4 3
LED5 14@ 5 4
PWR_LED# 6 5
4 GND 4 L BATT_CHG_LED# 1 2 2 R765 1 BATT_LOW_LED# 7 6
<28> BATT_CHG_LED# +5VALW 7
649_0402_1% BATT_CHG_LED# 8
CAPS_LED# 9 8
5 L 5 R 14@
19-213A-T1D-CP2Q2HY-3T_WHITE 10 9
10
SW6 15@ SW7 15@ 11
TJG-533-V-T/R_6P TJG-533-V-T/R_6P
GND 12 GND
6 R 6 GND
5
6
5
6
LED6 14@
4 2 4 2 HB_A091020-SAHR21
TP_2 TP_1 CAPS_LED# 1 2 2 R303 1 ME@
<28> CAPS_LED# +5VS
3 1 3 1 649_0402_1%
14@
19-213A-T1D-CP2Q2HY-3T_WHITE

BIOS, I/O Port & K/B CONN/TP CONN/PBTN
Size
Document Number Rev
B 1.0
VAWGA/GB
5 4 3 2 1
+VREF_1V65 CA3 vendor suggest

change to 2.2U
Sense resistors must be
+LDO_OUT_3.3V connected same power
that is used for VAUX_3.3
1U_0603_10V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
2.2U_0603_6.3V6K
+3VLP RA11 1 @ 2 0_0402_5% +AVDD_HP
1 1 2 1 AVDD_3.3 pinis output of
CA1
CA2
CA4
0.1U_0402_16V7K
1 2 5.11K_0402_1%
4.7U_0603_6.3V6K
internal LDO. NOT connect RA5 +3VS
CA3
1 1 to external supply.
CA5
CA6
1 2 2 2 1 2 mount RA6 on the Jack Sense circuit
+3VALW @ RA6 10K_0402_1%
1 2 to configure Port-C for mono MIC.
RA10 0_0402_5% 2 @ 2
JSENSE RA7 1 2 20K_0402_1% Don't support LINE_IN function

D +3VS D
RA8 1 2 39.2K_0402_1% PLUG_IN
+3VS
RA7 could be @
1U_0603_10V6K
1U_0603_10V6K
0.1U_0402_16V7K
0.1U_0402_16V7K
1 1
CA8
CA9
1 1
CA15
CA10
Should be same supply rail as used for
PCH HDA bus controller section @
@ 2 2
2 2
Layout Note:Path from +5VS to LPWR_5.0
RPWR_5.0 must be very low
resistance (<0.01 ohms)
RA4 1 @ 2 0_0402_5%
+1.5VS
0.1U_0402_16V7K
4.7U_0603_6.3V6K
+5VS
1 1
CA16 +LDO_1.8V
CA17
0.1U_0402_16V7K
4.7U_0603_6.3V6K
+5VS
1 1
CA18
CA19
0.1U_0402_16V7K
0.1U_0402_16V7K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
@ 2 2 10 mils
1 1 1 1
CA20
CA21
CA22
CA23
0.1U_0402_16V7K
4.7U_0603_6.3V6K
@
2 2
1 1
CA24
CA25
@
2 2 2 2
For EMI
0.1U_0402_16V7K
EMIU@ 2 2
18
29
27
28
24
1
3
7
2
CA26
CA7 EMIU@ UA1
1 RA21 2
Combo Jack
VDD_IO
FILT_1.8
VDDO_3.3
DVDD_3.3
AVDD_3.3
VREF_1.65V
AVDD_5V
AVDD_HP
2
Please bypass caps very close to device.
22P_0402_50V8J 33_0402_5% 13
LPWR_5.0
HDA_RST#_AUDIO 9 RPWR_5.0
16
11
HGNDA, HGNDB 80mils (Normal Open)
<6> HDA_RST#_AUDIO RESET# CLASS-D_REF
C HDA_BITCLK_AUDIO 5 JHP1 C
<6> HDA_BITCLK_AUDIO BIT_CLK
HDA_SYNC_AUDIO 8 38 JSENSE APPLE_MIC RA16 1 EMIP@ 2 100_0402_1% CA28 1 2 2.2U_0402_6.3V6M HGNDB 4
<6> HDA_SYNC_AUDIO SYNC JSENSE
RA9 1 2 33_0402_5% HDA_SDIN0_R 6 NOKIA_MIC RA12 1 EMIP@ 2 100_0402_1% CA27 1 2 2.2U_0402_6.3V6M HGNDA 3
<6> HDA_SDIN0 SDATA_IN
HDA_SDOUT_AUDIO 4 34 HP_L RA13 1 EMIP@ 2 15_0402_5% HPOUT_L 1
<6> HDA_SDOUT_AUDIO SDATA_OUT MICBIASB +MICBIASB
35 HP_R RA14 1 EMIP@ 2 15_0402_5% HPOUT_R 2
MICBIASC +MICBIASC
PC_BEEP 10 32 MICB_L PLUG_IN 5
39 PC_BEEP PORTB_L_LINE 33 MICB_R
<28> EC_MUTE# SPKR_MUTE# PORTB_R_LINE Universal Jack 6
30 APPLE_MIC
PORTD_A_MIC 31 NOKIA_MIC
External MIC SINGA_2SJ2352-000131F
1 PORTD_B_MIC 25 HGNDA ME@
40 DMIC_DAT/GPIO1 HGNDA 26 HGNDB
DMIC_CLK / MUSIC_REQ/GPIO0 HGNDB For Universal jack
Internal analog MIC MIC_IN 36 22 HP_L
37 MUSIC_REQ/GPIO0/PORTC_L_MIC PORTA_L 23 HP_R
GPIO1/PORTC_R_MIC PORTA_R Headphone
CA36
MICB_L RA17 1 2 100_0402_1% 1 2 HP_L
SPK_L2+ 12 2.2U_0402_6.3V6M
SPK_L1- 14 LEFT+ CA46
LEFT- MICB_R RA18 1 2 100_0402_1% 1 2 HP_R
Internal SPEAKER 21 2.2U_0402_6.3V6M
SPK_R2+ 17 AVEE 19 RA20 1 2 3K_0402_5%
RIGHT+ FLY_P
0.1U_0402_16V7K
15 20 1 2
2.2U_0603_6.3V6K
SPK_R1-
RIGHT- FLY_N CA29 1U_0603_10V6K RA19 1 2 3K_0402_5%
1 2 +MICBIASB
CA35
CA30
GND
using wide copper bridge CX20751-11Z_QFN40 2 1

41
B
under codec (100 mils or more) ESD B
HPOUT_L HPOUT_L
HPOUT_R HPOUT_R
CA30 vendor suggest
PC Beep change to 2.2U HGNDB HGNDB
EMIU@ HGNDA HGNDA

EC Beep
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
CA64 1 2 0.1U_0603_50V7K
<28> BEEP#
1 2 RA492
2
CA37 0.1U_0402_16V7K 1 2 PC_BEEP
EMIU@ 1 2 33_0402_5% DA1 DA2
<6> APU_SPKR
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
CA65 1 2 0.1U_0603_50V7K
ICH Beep CA45 0.1U_0402_16V7K
1
EMIU@
1
CA31
CA32
CA33
CA34
CA66 1 2 0.1U_0603_50V7K
EMIP@ LA1 LA2 EMIP@
2
@ RA22 0_0603_5% 0_0603_5%
10K_0402_5% ESDP@ ESDP@
1
EMIP@ LA3 LA4 EMIP@ LA1~LA4 vendor suggest mount 0 ohm first~
2
0_0603_5% 0_0603_5% Bead reserve for EMI if needed

+5VS
Place colose to Codec chip ESD JSPK1
DA3 SPK_R1- LA1 1
EMIU@ 2
FBMA-L11-160808-121LMT_0603 SPK_R1-_CONN 1
SPK_R1-_CONN 6 3 SPK_L2+_CONN SPK_R2+ LA2 1
EMIU@ 2
FBMA-L11-160808-121LMT_0603 SPK_R2+_CONN 2 1
+MICBIASC I/O4 I/O2 SPK_L1- LA3 1
EMIU@ 2
FBMA-L11-160808-121LMT_0603 SPK_L1-_CONN 3 2
SPK_L2+ LA4 1
EMIU@ 2
FBMA-L11-160808-121LMT_0603 SPK_L2+_CONN 4 3
4
EMIP@
EMIP@
EMIP@
EMIP@
5
G5
1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
5 2 6
RA23
2.2K_0402_5%
VDD GND
wide 30MIL 1 1 1 1
G6
CA38
CA39
CA40
CA43
A A
vendor suggest ME@
SPK_R2+_CONN 4 1 SPK_L1-_CONN change to 1000p
2
MIC1 CA41 1U_0603_10V6K I/O3 I/O1

1 MIC_IN_C 1 2 MIC_IN AZC099-04S.R7G_SOT23-6 2 2 2 2 ACES_85205-04001
2 GNDA
1 1 ESDU@
0.1U_0402_16V7K
0.1U_0402_16V7K
WM-64PCY_2P
45@ CA41 vendor suggest
2 2 change to 1U
CA42
CA44
CX20751 Codec
@ @ Custom 1.0
VAWGA/GB
5 4 3 2 1
A B C D E
+5VALW TO +5VS +5VALW VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

+5VS
U35P J5V J@
+3VALW TO +3VS 1
2 VIN1 VOUT1
14
13
+5VS_LS 1 2
VIN1 VOUT1
1 C12 C10 180P_0402_50V8J PAD-OPEN 4x4m 2
Load switch @ SUSP# 3
ON1 CT1
12 1 2 @ C13
@
1U_0402_6.3V6K
0.1U_0402_16V4Z
4 11
2 VL VBIAS GND 1
C9 330P_0402_50V7K
SUSP# 5 10 1 2
ON2 CT2 +3VS
@
6 9 J3V J@
1 +3VALW 7 VIN2 VOUT2 8 +3VS_LS 1 2 1
VIN2 VOUT2
15 PAD-OPEN 4x4m 2
GPAD @ C14
TPS22966DPUR_SON14_2X3
0.1U_0402_16V4Z
1 1
@ C11
1U_0402_6.3V6K
2
+1.8VALW VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

+1.8VS
+1.8VALW TO +1.8VS U1895P J18V J@
1U_0402_6.3V6K
1 14 +1.8VS_LS 1 2
2 VIN1 VOUT1 13
+0.95VALW TO +0.95VS @
1 C24
SUSP# 3
VIN1 VOUT1
12
C21
1
180P_0402_50V8J
2
PAD-OPEN 4x4m 2
@ C26
ON1 CT1
Load switch @
0.1U_0402_16V4Z
4 11
2 VL VBIAS GND 1
C15 330P_0402_50V7K
095VS_PWR_EN 5 10 1 2
<28> 095VS_PWR_EN ON2 CT2 +0.95VS
@
6 9 J95V J@
2 +0.95VALW 7 VIN2 VOUT2 8 +0.95VS_LS 1 2 2
VIN2 VOUT2
15 PAD-OPEN 4x4m 2
GPAD @ C25
TPS22966DPUR_SON14_2X3
0.1U_0402_16V4Z
1 1
@ C22
1U_0402_6.3V6K
+1.5V +0.75VS
+1.5V to +1.5VS Vgs=-4.5V,Id=-2.8A,Rds=110mohm
+1.5V Q20 +1.5VS
1
3 1
1 1 1 R1627 R1629
1
@ 470_0603_5% 470_0603_5%
C470 LP2301ALT1G_SOT23-3 C469 C463 @ @
1 2
1 2
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0603_10V6K R1461
2
2 2 2 220_0603_5% D D
2 SYSON# 2 SUSP
2
G G
S Q93 S Q95
3
1
+5VALW D 2N7002K_SOT23-3 2N7002K_SOT23-3

3 2 SUSP @ @ 3
G
1
S Q23
3
2N7002K_SOT23-3
100K_0402_5% +RTCBATT_3V
R337
R339 +5VALW
2
2
1.5VS_GATE 1 @ 2 1.5VS_GATE_R
1 R1636
1
1
D 0_0402_5% 100K_0402_5%
SUSP# 2 Q26 C462 @
G 2N7002K_SOT23-3 0.1U_0402_16V4Z R1638
1
S 2 SUSP 100K_0402_5%
3
2
Q101 SYSON#
1
DTC124EKAT146_SC59-3
1
OUT
OUT
2 Q102
<28,37> SUSP# IN SYSON 2 DTC124EKAT146_SC59-3
GND
<28,37> SYSON IN
1
GND
1
R1639 @
3
100K_0402_5% R1640
3
100K_0402_5%
2
2
4 4

DC Interface
Size
Document Number Rev
B 1.0
VAWGA/GB
A B C D E
5 4 3 2 1
VIN
PF101 PL101
JDCIN1 7A_24VDC_429007.WRML SMB3025500YA_2P
1 APDIN 1 2 APDIN1 1 2
1 2
D 2 3 D
3
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
4
4 5
5
1
PC101
PC102
PC103
PC104
ACES_50312-00541-001
@
2
PQ102A
PR102 2N7002KDW-2N_SOT363-6
2 1 6 1
+3VALW ADP_ID <28>
680P_0603_50VK
0.1U_0402_16V7K
750_0402_1%
2
1
PC108
PC109
100K_0402_1%
2
2
PR104
2 1
VIN
2N7002KDW-2N_SOT363-6
1
3
100K_0402_1%
PQ102B
PR105
C 5 C
ADP_ID_CLOSE <28>
2
+CHGRTC
PR103
1K_0603_5%
+RTCBATT_3V 1 2
PD101
+3VLP
PU102 S SCH DIO BAS40CW SOT-323
+RTCBATT 3 2 +CHGRTC_R
Vout 1 +RTCBATT_3V 1
Vin
0.1U_0603_25V7K
2 3 PR101
GND
680P_0603_50VK
1K_0603_5% JRTC1 @
1
PC111
1 2 1
2 1
1
PC110
AP2138N-1.5TRG1_SOT23-3
3 2
2
4 GND
2
GND
ACES_50271-0020N-001
B B
RTC Battery
Need use+3.3V transfer to +1.5V LDO to APU side for Kaibini
A A

PWR-DCIN / RTC Battery
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom VAWGA/B 1.0
5 4 3 2 1
5 4 3 2 1
VMB2 VMB
@ PF201 PL201
JBATT1 12A_65V_451012MRL SMB3025500YA_2P
SUYIN_200082GR007M229ZR
1 1 2 1 2
1 2 BATT+
2 3 EC_SMCA
3 4 EC_SMDA
4 5
5 6
6 7
1
7 8
1
100_0402_1%
100_0402_1%
D D
GND 9 PC201 PC203
GND 1000P_0402_50V7K 0.01U_0402_25V7K
2
PR201
PR204
2
2
EC_SMB_CK1 <28>
EC_SMB_DA1 <28> 90W(DIS) : 6.65K 100W active 90W recovery

PH201 under CPU botten side :
1 2 65W(UMA): 1.65K 70W active 65W recovery
PR206
+3VLP CPU thermal protection at 93 +-3 degree C 20120314
6.49K_0402_1%
Recovery at 56 +-3 degree C Change to +EC_VCCA from +3VLP
JBATT2 1 2
SUYIN_200082GR007M229ZR
+3VALW
@ @ PR209
1 6.49K_0402_1%
1 2
2 3
+3VS +EC_VCCA
3 <28,35> ADP_I
4 1 2
4 BATT_TEMP <28>
12.7K_0402_1%
5 PR207
5
1
6 10K_0402_5%
6 A/D
100K_0402_1%
PR226
7 @ PR229
7
2
PR215
8.45K_0402_1%
8 @ 10K_0402_1%
GND 9 PROCHOT 1 2
GND <28,4,40,6> H_PROCHOT# <28>
PR221
2
NTC_V
<28>
1
PQ201
1
1
C D C
@ 2 ADP_OCP_1 Turbo_V
<28>
1
G
S 2N7002KW_SOT323-3 PH201
2
25.5K_0402_1%
9.31K_0402_1%
5.9K_0402_1%
100K_0402_1%_TSM0B104F4251RZ
2
PR225
2N7002KW_SOT323-3
PR227
PR228
PR216 PR222
2
0_0402_5% 100K_0402_1%
PROCHOT 1 2
1
@
1
1
D
PQ206
2N7002KW_SOT323-3
2
VL +3VALW <28> ADP_65 G
S
2N7002KW_SOT323-3
<28>
1
D ECAGND
PQ208
2
VL <28> ADP_90
PR214 G
2
PQ207
S
3
PC202 PR211 100K_0402_1%
1
1
D ECAGND
6 1
1
0.01U_0402_25V7K 100K_0402_1% BATT_OUT <28> 2

ADP_135 <35>
PR202 PR210 G
2
1
2
75K_0402_1% 47K_0402_1% S
3
BATT_OUT
PQ202A
2 2N7002KDW-2N_SOT363-6
2
PC208
1
1
8
0.068U_0402_16V7K
BATT_TEMP3 PQ202B ECAGND
P
+ 1 1 2 5 2N7002KDW-2N_SOT363-6
B 2 O B
-
G
PU201A
4
1
AS393MTR-E1 SO 8P OP
4
2
PD201
PR213 VL PR205
1
100K_0402_1% 1N4148WS-7-F_SOD323-2
1
PC207 1.5M_0402_5%
2
100P_0402_50V8J
1
+3VLP
VMB
1
+3V_LDO
75K_0402_1%
@ PR218 PR220
2
47K_0402_1%
@ PR208
100K_0402_1%
8
@ PC210
2
1
1
5 0.068U_0402_16V7K~N D D
P
+ 7 1 2 2 BATT_LEN# 2
<28> PQ205
1
O
2N7002KW_SOT323-3
6 G G 2N7002KW_SOT323-3
-
G
PQ209
1N4148WS-7-F_SOD323-2
S S
3
3
2
100K_0402_1%
100P_0402_50V8J
4
1
PU201B
@ PR217
AS393MTR-E1 SO 8P OP @
@ PC213
PD203
2
@ PR223
1
1.5M_0402_5% @
+5VALW
22U_0603_6.3V6M
@ PU202
1
@ PC212
A 1 5 A
IN OUT +3V_LDO
2
2
GND
1
3 4
SHDN# BYP @ PC214
G9191-330T1U_SOT23-5 4.7U_0402_6.3V6M
2
1
PC211 @ Security Classification Compal Secret Data Compal Electronics, Inc.

1U_0402_16V6K Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
2
PWR-BATTERY CONN/OTP
5 4 3 2 1
5 4 3 2 1
P3
B+
P2
PQ301 PQ302
AO4407AL_SO8 AO4423L_SO8
8 1 1 8 PR301
VIN 7 2 2 7 0.01_1206_1% CHG_B+
6 3 3 6
5 5 1 4 1 2 PQ312
PL301 AO4407AL_SO8
2 3 1UH_PCMB061H-1R0MS_7A_20% 1 8
4
2 7
3 6
@ 10U_0805_25V6K
@ 10U_0805_25V6K
2200P_0402_50V7K
PQ304 5
10U_0805_25V6K
10U_0805_25V6K
D D
47K_0402_5%
1
2
200K_0402_1%
0.1U_0603_25V7K
PC319
4
1
PR302
PC310
PC313
PC315
PC316
DTA144EUA_SC70-3 DISCHG_G
PC302
PR304
1
1 2 PR322
200K_0402_1%
2
2
2 PC301 1 2
2
5600P_0402_25V7K ACN VIN
2ACOFF-1
1SS355_SOD323-2
2
1
ACP PR321
1DISCHG_G-1
47K_0402_1%
1
2
PD302
P2-1 PR325
0.1U_0402_25V6
1
2 200K_0402_1%
PQ303 PQ311
1
PC307 PC311 DTC115EUA_SC70-3
1
DTC115EUA_SC70-3
PR306 1 2 2 1
3
20K_0402_1%
1 2 0.1U_0402_25V6 2 1 2
6
PQ306
ACPRN
1
D
150K_0402_1%
2N7002KW _SOT323-3 PC308 PD303 PQ313

PR305
PQ307A 2 BATT_OUT 1SS355_SOD323-2

2 2N7002KDW -2N_SOT363-6 G 0.1U_0402_25V6 P2 2N7002KW _SOT323-3
1
D
0.1U_0402_25V6
S
3
2 1 2 PACIN
1
1
PC324
VIN G
S
3
392K_0402_1%
2
1
P2-2
10_1206_5%
MDS1525URH 1N SO8
2
5
6
7
8
C C
PR309
2N7002KDW-2N_SOT363-6
PQ309
PR319
3
PQ307B
ACOK
CMPIN
CMPOUT
ACP
ACN
PR303 PR308 ADP_I
<28,34>
2
47K_0402_1% 64.9K_0402_1% 21 PR311
1
PACIN 1 2 5 1 2 6 TP 1 2 4
ACDET PC314
PC303 PC304 20 BQ24737VCC 1 2 0_0402_5%
4
1 2 1 2 7 VCC
IOUT PL302 PR324
3
2
1
1U_0603_25V6K
1
PQ305 0.1U_0402_25V6 100P_0402_50V8J 19 10UH_PCMB104T-100MS_6A_20% 0.01_1206_1%

PHASE
DTC115EUA_SC70-3 <28> EC_SMB_DA1
8
SDA
PU301
1 2
BATT+
BQ24727RGRR_VQFN20_3P5X3P5 LX_CHG CHG1 4
PR313 18 DH_CHG
HIDRV
5
6
7
8
1 2ACOFF-12 9 2 3
ACOFF <28> <28> SCL
1
EC_SMB_CK1
PQ310
PR315 PR320 PC317
4.7_1206_5%
MDS1521URH 1N SO8
PR323
10K_0402_1% 316K_0402_1% 2.2_0603_5% 0.047U_0603_16V7K
1 2 10 17 BST_CHG 1 2 2 1 SRP SRN
10U_0805_25V6K
10U_0805_25V6K
124737_SN
ILIM BTST
1
+3VALW
3
PD301 4
PR316 @
LODRV
1
PC322
PC323
PQ314 100K_0402_1% 16 2 1
GND
SRN
SRP
REGN
1
BM
2N7002KW _SOT323-3
2
BATT_OUT <34>
2
2
RB751V-40_SOD323-2
680P_0603_50V7K
G 11
12
13
14
15
3
2
1
1
PC320
S
3
2
PC312 BQ24737VDD
6.8_0402_5%
1
10_0402_5%
1U_0603_25V6K
2
PR317
PR318
@
PC306 DL_CHG
2
2
B 0.1U_0402_25V6 B
2 1
1
PC305 @ 1 PC309
0.1U_0402_25V6 0.1U_0402_25V6
2
BQ24737VDD
PR314
10K_0402_1%
1
1 2
ACIN <11,28>
PR310
PR307 10K_0402_1%
47K_0402_1%
PACIN
2
PQ308
1
2N7002KW _SOT323-3
1
D PR312
ACPRN 2
G 12K_0402_1%
2
S
3
A A

PWR-CHARGER
1.0
VAWGA/B
5 4 3 2 1
A B C D E
3V5V_EN_R 2 1 3V5V_EN
0.047U_0402_25V6
PR411
PC432
10K_0402_1%
2 1
1 1
PR402
PR414 499K_0402_1%
1 2 ENLDO_3V5V 2 1
B+
1
150K_0402_1%
1U_0603_25V6K
0_0402_5%
1
PR403
@ PR415
2 1
PC407
2
0_0402_5%
2
PU401
B+ PL401 7 1 3V5V_EN_R
HCB2012KF-121T50_0805 IN EN1 PC439 PR416
1 2 3V_VIN 8 3 1 2 2 1
IN EN2
2200P_0402_50V7K
68P_0402_50V8J
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
PC402
6 1
BST_3V 2 1 2 0.01U_0402_25V7K 1K_0402_5%
BS
PC401
PC403
1
1
PC404
PC405
PC406
PR401 0.1U_0603_25V7K
0_0402_5% PL402
@ @ 10 LX_3V 1 2
+3VALWP
2
@ LX
9 4 1.5UH_PCMC063T-1R5MN_9A_20%
GND OUT
470P_0402_50V8J
470P_0402_50V8J
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
@ @
1
PC412 @
PC413 @
PC434
PC435
4.7_1206_5%
2 5
<37> SPOK PG LDO +3VLP
PC408
PC409
PC410
PC411
1
PR404
SY8208BQNC_QFN10_3X3
2
100K_0402_1%
100K_0402_1%
PC414
1
13V_SN
4.7U_0603_6.3V6M
680P_0603_50V7K
PR417
PR410
1 ENLDO_3V5V
PC415 @
2 @ 2
+3VLP
2
2
+3VALWP
0_0402_5%
PR412
B+ PL403
HCB2012KF-121T50_0805
1 2 5V_VIN @
2 PC436 PR413
1 2 2 1
6800P_0402_25V7K 1K_0402_5%
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
68P_0402_50V8J
0.1U_0402_25V6
PU402
8 1 3V5V_EN
IN EN1
1
1
PC419
PC420
PC416
PC417
PC418
3 PC421
EN2 0.1U_0603_25V7K
6 BST_5V 1 2 1 2
2
@ @ BS
PR405
0_0402_5% PL404
9 10 LX_5V 1 2 +5VALWP
GND LX
5V_VCC 5 4 1.5UH_PCMC063T-1R5MN_9A_20%
150U_D2_6.3VY_R15M
VCC OUT 1
1
470P_0402_50V8J
470P_0402_50V8J
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
680P_0603_50V7K 4.7_1206_5%
@ @
1
PR406 @
PC427 @
PC428 @
PC433
PC437
PC438
2 7 +
PG LDO VL
1
PC422
PC423
PC424
PC425
PC426
4.7U_0603_6.3V6M
SY8208CQNC_QFN10_3X3
2
2@
1 5V_SN
2
2
1
PC430
4.7U_0603_6.3V6M
3 3
PC429 @
2
@PJ401
@ PJ401
+3VALWP 1 2 +3VALW
1 2
PR407 JUMP_43X118
2.2K_0402_5%
EC_ON 2 1
<28> EC_ON
MAINPWON 1 2 @PJ402
@ PJ402
<28> MAINPWON
+5VALWP 1 2 +5VALW
PR408 1 2
0_0402_5% JUMP_43X118
3V5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR409
PC431
2
2
4 4

PWR-3VALWP/5VALWP
A B C D E
A B C D
PL502
1.5V_B+ 1 2 B+
HCB2012KF-121T50_0805
2200P_0402_50V7K
10U_0805_25V6K
STATE S3 S5 1.5VP VTT_REFP 0.75VSP
0.1U_0402_25V6
4.7U_0805_25V6-K
MDU1516URH_POWERDFN56-8-5
1
PC501
PC520
PC509
PC513
S0 Hi Hi On On On
5
Off
2
@ @
S3 Lo Hi On On (Hi-Z) +1.5VP
PQ501
UG_1.5V 4
S4/S5 Lo Lo Off Off Off
2
1 1
LX_1.5V
3
2
1
PR503
Note: S3 - sleep ; S5 - power off 0_0402_5%
PR501 PC512 PL501
1
2.2_0603_5% 0.1U_0603_25V7K 1UH_PCMB104T-1R0MH_18A_20%
BST_1.5V 1 2 BST_1.5V-1 1 2 2 1
+0.75VSP +1.5VP
10U_0805_25V6K
10U_0805_25V6K
1
MDU1511RH_POWERDFN56-8-5
5
@
20
19
18
17
16
1
1
PC504
PC505
PU501 PR515
4.7_1206_5% @
VLDOIN
VTT
BOOT
UGATE
PHASE
21 1 1
2
PAD
PQ502
1 15 LG_1.5V 4 + +
VTTGND LGATE PC521 PC522
1
@
2 14 PC517 330U_2.5V_M 2 2 220U_6.3V_M
VTTSNS PGND PR511 680P_0603_50V7K
3
2
1
2
6.65K_0402_1%
3 13 2 1
GND RT8207MZQW _W QFN20_3X3 CS
4 12
+VTT_REFP VTTREF VDDP
5 11 2 1
+1.5VP VDDQ VDD
+5VALW
PGOOD
PR514
+3VALW +1.5VP
1
5.1_0603_5%
1U_0603_10V6K
TON
PC506 OCP min 20A
FB
S3
S5
2 0.033U_0402_16V7K 2
2
1
OVP min 1.65V
PC510
10K_0402_5%
PC511
10
PR510
1U_0603_10V6K
S3_1.5V
2
PR502
S5_1.5V
49.9K_0402_1% @
2
SUSP# 1 2
<28,32>
PGOOD_1.5V
PR509
PR505
887K_0402_1%
SYSON <28,32>
1 2 2 1 1.5V_B+
0_0402_5% PR507 PJ504

1
PC503 @ PC508 5.6K_0402_1% 2 1

0.1U_0402_16V6K 0.1U_0402_16V7K 2 1 2 1
@ JUMP_43X118
2
@ PC526
1
1 2 PJ505
+1.5VP 2 1 +1.5V
PR506 2 1
5.76K_0402_1% 68P_0402_50V8J @ JUMP_43X118
2
PJ506
2 1
+0.75VSP 2 1 +0.75VS
JUMP_43X79
@
3 3
PU502
SY8033BDBC_DFN10_3X3
PL503
4
PJ502 1UH_PH041H-1R0MS_3.2A_20%
2 1 1.8VSP_VIN 10 2 1.8VSP_LX 1 2
+3VALW
PG
2 1 PVIN LX +1.8VALWP
@ JUMP_43X79 9 3
4.7_1206_5%
PVIN LX
1
1
PR508
PC502 8
22U_0805_6.3VAM SVIN
68P_0402_50V8J
1
6 FB=0.6Volt
2200P_0402_50V7K
68P_0402_50V8J
0.1U_0402_25V6
2
FB
1
5 @ PC525
22U_0805_6.3VAM
22U_0805_6.3VAM
1 2
EN
1
PC518
PC519
NC
NC
PR512
TP
PC514
PC515
PC516
20K_0402_1% PJ507
680P_0603_50V7K
2
SPOK
PC523
@ PR516 +1.8VALW P 2 1 +1.8VALW

11
2
1 2 EN_1.8VSP 2 1
2
<36,38> @ @ @ JUMP_43X79
0_0402_5% @ @
0.1U_0402_10V7K
2
1
PC507 @
1
PR504 PC524
1M_0402_5% 0.1U_0402_10V7K
2
1.8VSP_FB
PR611
2
095_18ALW_PWR_EN
1
1 2
<28>
0_0402_5% PR513
10K_0402_1%
4 4
2

PWR-+1.5VP/+1.8VALWP
Custom 1.0
VAWGA/GB
A B C D
5 4 3 2 1
D D
PL601
HCB2012KF-121T50_0805
0.95V_B+ 1 2 B+
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
5
6
7
8
1
PQ601
PC602
PC603
PC604
PC605
MDS1525URH 1N SO8
2
PR609 @
1 2 4
0_0402_5%
3
2
1
095_18ALW_PWR_EN PR610
1 2 PR602 PC606 PL661
<28> 40.2K_0402_1% PU601 2.2_0603_5% 0.22U_0603_16V7K 1UH_PCMC063T-1R0MN_12A_20%
0_0402_5%
PR603
1
PGOOD VBST
10 1
BST_0.95V 2BST_0.95V-11 2 1 2 +0.95VALWP
@ PR601 2 1 0.95V_TRIP 2 9 DH_0.95V
0_0402_5% TRIP DRVH
1 2 0.95V_EN 3 8 LX_0.95V
4.7_1206_5%
<37> SPOK EN SW
1
1
5
6
7
8
0.95V_FB 4 7
PR604
+5VALW
2
VFB V5IN + PC607
PQ602
47K_0402_5%
.1U_0402_16V7K
MDS1521URH 1N SO8
1 PR606 2 0.95V_RF 5 6 DL_0.95V 220U_6.3V_M
@ PR605
RF DRVL PC608 @
@ PC601
2
470K_0402_1% 11 1U_0603_10V6K 2
PR607
2
TP 4
680P_0603_50V7K
1
1 2 TPS51212DSCR_SON10_3X3
PC609
VFB=0.7V
PR605 reserve 3.48K_0402_1%
1
3
2
1
2
@
PR608
C 10K_0402_1% +0.95VALWP OCP(min)=15.6A C
2
PJ602
2 1
2 1
@ JUMP_43X118
+0.95VALWP PJ603 +0.95VALW

2 1
2 1
@ JUMP_43X118
B B
A A

PWR-+0.95VALWP
C 1.0
VAWGA/B
5 4 3 2 1
A B C D
+3VGS
VBOOT GPU_VID5 GPU_VID4 GPU_VID3 GPU_VID2 GPU_VID1 GPU_VID0
10K_0402_1%
10K_0402_1%
PR803 @ 10K_0402_1%
10K_0402_1%
PR805 @ 10K_0402_1%
PR806 @ 10K_0402_1%
PR807 @ 10K_0402_1%
PR808 @ 10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
0.85V 1 1 0 1 0 NA
2
+VGA_B+ PL801
@ HCB4532KF-800T90_1812
1 2
PR801
PR802
PR804
PR809
PR810
PR811
PR812
B+
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
GPU_VID5
GPU_VID4
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
PC801 @
1
@ PC803
@ PC804
@ PR813
@ PC802
1 1
0_0402_5%
2
1 2 VRON_VGA
<12,28,6> PXS_PWREN
2
PR820 PR814
1 2 0_0402_5%
<28> EC_VGA_EN
GPU_VID5
GPU_VID4
GPU_VID3
<11> GPU_VID2
<11> GPU_VID1
0_0402_5%
1
@ PR816
@
2.2K_0402_1% PC805 @ PR817
PR817 PC806 PQ801
1
1 2 1 2 2.2_0603_5% 0.22U_0603_10V7K CSD87351Q5D_SON8-7
+3VS
GPU_VID0
@
BOOT2_VGA 2 1 BOOT2_2_VGA 1 2 2 PL802
@ PR818 100P_0402_25V8K
GPU_GPIO0 1 2 UGATE2_VGA 0.22UH_PCME064T-R22MS_28A_20%
<11> +VGA_CORE
7
<11>
<11>
<11>
0_0402_5% PHASE2_VGA 3 6 SW2_VGA 1 4
PR819 5
1 2 DPRSLPVR_VGA-1 4 LF2_VGA 2 3 V2N_VGA
1 1 1 1
3.65K_0402_1%
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1
1
2.2K_0402_1%
1_0402_1%
4.7_1206_5%
10K_0402_1%
10K_0402_1%
PR826 @
+3VS PR830 @ + + + +
@ PR827
@ PR837
@ PR829
PC807
PC808
PC809
PC810
GPU_VID6
1.91K_0402_1%
@ PR828
8
1 2 CLK_ENABLE#_VGA
LGATE2_VGA 2 2 2 2
1.91K_0402_1%
2
1
SNUB2_VGA
PR831
VSUM-_VGA
PR832
2
VSUM+_VGA
1 2 PR833
ISEN2_VGA
ISEN1_VGA
2.2K_0402_1%
0_0402_5% 1 2
680P_0402_50V7K
VGA_PWRGD +3VS
PC811 @
@
1
GPU_GPIO0 1 PR834 2
0_0402_5%
@ PR835
2
1 2
PSI#_VGA
2 2
2.2K_0402_1%
2 PR836 1
RBIAS_VGA
147K_0402_1% @ PC812
1U_0603_10V6K +VGA_CORE
40
39
38
37
36
35
34
33
32
31
PU801 1 2
CLK_EN#
DPRSLPVR
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VR_ON
30
BOOT2 29
1 UGATE2 28
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
2 PGOOD PHASE2 27
1
3 PSI# VSSP2 26
PC824
PC825
PC826
PC827
PC828
PC829
PC830
PC831
PC832
PC833
PC834
PC835
PC836
PC837
PC838
PC839
4 RBIAS LGATE2 25
5 VR_TT# VCCP 24 +5VS
2
VW_VGA 6 NTC PWM3 23
COMP_VGA 7 VW LGATE1 22
FB_VGA 8 COMP VSSP1 21
1 2ISEN3_VGA 9 FB PHASE1
ISEN3
1
UGATE1
10 PC872
BOOT1
ISUM+
ISEN2
ISEN1
ISUM-
VSEN
IMON
@ PC871 1U_0603_10V6K
5.9K_0402_1%
VDD
1000P_0402_50V7K
RTN
VIN
22P_0402_50V8J 41
249K_0402_1%
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
2
2
AGND
PR840 @
PC873
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
ISL62883CHRTZ-T_TQFN40_5X5
PR841
11
12
13
14
15
16
17
18
19
20
1
PR842 PR864
PC840
PC841
PC842
PC843
PC844
PC845
PC846
PC851
PC852
PC853
PC854
PC855
PC856
PC857
2
499_0402_1% PC874 0_0402_5%

1 2FB1_VGA1 2 1 2
ISUM-_VGA
1
2
VDD_VGA
RTN_VGA
390P_0402_50V7K
PC847 PR843 PR844 @ 0_0402_5%
33P_0402_50V8J 1.69K_0402_1% 1 2
+5VS
1 2 1 2 PR863 VSEN_VGA PR865
0_0402_5% For 15W one phase PR845 1 2
6.65K_0402_1%
<28>
0.047U_0402_16V7-K
2
1 2 VIN_VGA 1 2
1
GPU_IMON
0_0402_5%
PC849
PR847
+5VS +VGA_B+
1 2FB2_VGA
1 2 0_0402_5%
ISEN2_VGA
PR848
2
3
PC848 PR846 1 2 +VGA_B+ 3
ISEN1_VGA
1
1
150P_0402_50V8J 267K_0402_1% +5VS

1
1_0402_5%
PC876
PC877
1U_0603_10V6K
0.22U_0402_10V6K
0.22U_0402_10V6K
0.22U_0603_25V7K
PR849 VSSSENSE_VGA
1
30K_0402_1%
PC850
PC875
2200P_0402_50V7K
2
BOOT1_VGA
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2
@ @
1
PC878
PC879
PC880
PC881
VSUM-_VGA
2
VSUM+_VGA UGATE1_VGA @
1 2 PQ802
82.5_0402_5%
+VGA_CORE
PR851 @
PR852 PC858 CSD87351Q5D_SON8-7

1
1
PR850 2.2_0603_5% 0.22U_0603_10V7K
1
10_0402_1% 2 1 BOOT1_1_VGA 1 2 2 PL803

2.61K_0402_1%
PR853
PR854 0.22UH_PCME064T-R22MS_28A_20%
<14> 1 2 7
VCCSENSE_VGA
2
PHASE1_VGA 3 6 SW1_VGA 1 4
+VGA_CORE
2
0_0402_5% 5
0.1U_0603_25V7K
VSUM_VGA_N001
0.033U_0603_25V7K
1
4 2 3 V1N_VGA
NTC_VGA
PC859 LF1_VGA
1
1
330P_0402_50V7K
PC860
PC861
3.65K_0402_1%
2
1
PR856
1_0402_1%
4.7_1206_5%
10K_0402_1%
@ PR838
PR858
10K_0402_1%
2
PR855
PR857
0.01U_0402_25V7K
PC864 @
LGATE1_VGA
330P_0402_50V7K
2
1
1
PC863 @
11K_0402_1%
2
1
PC862 PH802 @ @
PR859
1000P_0402_50V7K 10K_0402_1%_TSM0A103F34D1RZ
1 SNUB1_VGA
PR860
2
1 2
VSUM-_VGA
<14> VSSSENSE_VGA
2
Layout Note:
0_0402_5%
Place near Phase1 Choke
VSUM+_VGA
PR861 PR862
ISEN1_VGA
ISEN2_VGA
680P_0402_50V7K
10_0402_1% 887_0402_1% @
4
1 2 1 2 4
PC865
VSUM-_VGA
2
Sun Pro
OCP:42A
1
PC866
0.1U_0402_16V7K
2

PWR-VGA_CORE
C 1.0
VAWGA/GB
A B C D
5 4 3 2 1
CPU_B+ PL901
HCB2012KF-121T50_0805
1 2 B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V5K
5
5
1
1
PC1027
PC1029
PC1030
PC1032
PC901 PR901 + PC1031
PC1028
330P_0402_50V7K 2K_0402_1% 220U_25V_M
2
2 1 2 1 PR954 @
UGATE_NB1 1 2 4 4 2
PQ905
PQ901
<4> 150P_0402_50V8J
APU_VDDNB_SEN PC1033
PR902 PR903 PR904 @ PR905
2
10_0402_5%
1 2
1.54K_0402_1%
1
267K_0402_1%
2 1 2 1 2
41.2K_0402_1%
1
0_0402_5%
ͲͲͲͲͲͻͲͲȋͳǤͳΪǦͷΨȌ
+APU_CORE_NB PL902
3
2
1
3
2
1
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
D ʹͲͳͳȀͳͲȀʹͳ PR906 PC1034 PR907
0_0402_5% 1000P_0402_50V7K 499_0402_1%
PC1035
47P_0402_50V8J PHASE_NB1 1 4 D
ͳ 1 2 2 1 2 1 2 1
PR908 PC1036 2 3
+APU_CORE_NB
1
VSUMP_NB PC1037 2.2_0603_1% 0.22U_0603_25V7K
0.01U_0402_50V7K BOOT_NB1 2 1 2 1 @ PR910
2.61K_0402_1%
10K_0402_5%_ERTJ0ER103J
1
4.7_1206_5%
5
2 1
PR909
680P_0603_50V7K
0.022U_0402_25V7K
0.15U_0603_16V7K
1 2
2
PR912
11K_0402_1%
2
PR911
3.65K_0402_1%
12
VSUMP_NB 2 1
PH901
PC1038
PC1039
LGATE_NB1 4 4 @ PC1040
1
2
PQ906
PQ902
PR914
1
PR913 1_0402_1%
324_0402_1% VSUMN_NB 2 1
2
VSUMN_NB 2 1
3
2
1
3
2
1
1
@ PR915 @ PC1042
PC1041 100_0402_1% 220P_0402_50V7K LGATE_NB1
0.1U_0603_50V7K 2 1 2 1
2
PHASE_NB1
ʹͲͳͳȀͳͲȀʹͳ UGATE_NB1
̴Ȁ
PR916 27.4K_0402_1% 20K_0402_1%
BOOT_NB1
ʹͲͳʹȀͳͲȀ͵Ͳ
2 1
PR917 ǣǦǦεͶ
41
40
39
38
37
36
35
34
33
32
31
2 1 2 1 PU901 ǦǦεͶǤͲ
TP
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT_NB
470K_0402_5%_TSM0B474J4702RE
PH902
1 30
PC1043 NTC_NB BOOT2
1000P_0402_50V7K
2 1 2 29
PR918 0_0402_5% IMON_NB UGATE2
C 2 1 <4>
1 2 SVC 3 28 C
APU_SVC SVC PHASE2
PR920 0_0402_5%
H_PROCHOT# +5VALW
PR919 133K_0402_1%
<28,34,4,6>
1 2 4 27
100K_0402_1% @ PR922 PR921 0_0402_5% VR_HOT_L LGATE2
+3VS
2 1 <4>
1 2 SVD 5 26
APU_SVD SVD VDDP
PR923 0_0402_5% ISL62771HRTZ-T_TQFN40_5X5 PR924
+1.8VS 1 PR953 2 1 2 VDDIO 6 25 2 1
0_0402_5% PR925 0_0402_5% VDDIO VDD 1_0603_5%
1U_0603_25V6K
0.1U_0402_25V6
2
12 1<4> 1 2 SVT 7 24 LGATE1

PC1073
+1.5VS APU_SVT SVT LGATE1

2
1
@ PR952 PR926 0_0402_5%
1U_0603_25V6K
0_0402_5% <28> PC1044 1 2 ENABLE 8 23 PHASE1
PC1046
1
APU_IMON VR_ON ENABLE PHASE1

PC6602 1000P_0402_50V7K 0.1U_0402_25V6 PR927 0_0402_5%
PC1045
1
2
1 PR951 2 2 1 2 PWROK 9 22 UGATE1 CPU_B+
<4> APU_PWRGD PWROK UGATE1
0_0402_5%
1 PR928 2 10 21 BOOT1
133K_0402_1% IMON BOOT1 +3VS
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
0.1U_0402_25V5K
PGOOD
PC1047
ISUMN
ISUMP
COMP
ISEN2
ISEN1
VSEN
1000P_0402_50V7K 1
NTC
RTN
1 2
FB
1
PC6601
PC1049
PC1048
PC1050
PC1051
PC1052
20K_0402_1% 1000P_0402_50V7K
11
12
13
14
15
16
17
18
19
20
PR930 27.4K_0402_1% PR929 2
2
2 1 1 PR931 2 100K_0402_1% @
PR955
2
+5VS 1 2 4 4
PQ907
PQ903
PH903 UGATE1
470K_0402_5%_TSM0B474J4702RE <28>
VGATE
2 1 0_0402_5%
ͲͲͲͲͲ
ͲͲȋͳǤʹͷΪǦ͹ΨȌ
PL903
3
2
1
3
2
1
PR932 0.36UH_FDUE1030D-H-R36M=P3_32A_20%
1 2 ISEN2
PHASE1 1 4
0_0402_5%
PR933 PC1053 2 3
+APU_CORE
2 1 ISEN1 2.2_0603_1% 0.22U_0603_25V7K
1
PR934 BOOT12 1 2 1 @ PR935
10K_0402_1% 4.7_1206_5% PR936
PC1054 PR937 PC1055 PR938 @ 3.65K_0402_1%
5
B B
1000P_0402_50V7K 499_0402_1% 47P_0402_50V8J 32.4K_0402_1% VSUM+ 2 1
ʹͲͳͳȀͳͲȀʹͳ 2 1 2 1 2 1 2 1
330P_0402_50V7K
1 2
@ PC1057
̴Ȁ @ 680P_0603_50V7K PR941
2
VSUM+ PR939 PR940 PC1058 1_0402_1%

1.54K_0402_1% 267K_0402_1% 150P_0402_50V8J LGATE1 4 4 VSUM- 2 1
PC1056
2.61K_0402_1%
2
10K_0402_5%_ERTJ0ER103J
1
2 1 2 1 2 1
PQ908
PQ904
1
PR942
0.01U_0402_50V7K
0.15U_0603_16V7K
2
PR944 PC1061
3
2
1
3
2
1
2
2K_0402_1% 330P_0402_50V7K
11K_0402_1%
12
2 1 2 1
PH904
PR943
PC1059
PC1060
1
1
1
PR945 PR946
487_0402_1% 10_0402_5%
2
VSUM- 2 1 2 1 +APU_CORE
PC1063@ PR947
1
@ PR948 820P_0402_50V7K 0_0402_5%

PC1062 100_0402_1% 1 2 <4>
0.1U_0603_50V7K 2 1 2 1 APU_VDD_SEN
2
PR949
0_0402_5%
1 2
0.01U_0402_50V7K
PR950 APU_VDD_RUN_FB_L <4>

10_0402_5%
2
2 1
PC1064
1
ʹͲͳͳȀͳͲȀʹͳ
ͳ
A A

APU_CORE/APU_CORE_NB
Custom 1.0
VAWGA/B
5 4 3 2 1
A B C D E
1 1
10U_0603 *3
10U_0603 * 4
+APU_CORE +APU_CORE_NB
PC1001
PC1002
PC1003
PC1004
PC1067
PC1068
PC1065
PC1066
PC1009
PC1010
PC1011
PC1071
PC1072
PC1069
PC1070
PC1013
PC1014
PC1015
PC1016
22U_0603_6.3V6MPC1005
22U_0603_6.3V6MPC1006
22U_0603_6.3V6MPC1007
22U_0603_6.3V6MPC1008
1
1
@ @ @ @ @ @ @
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2
2
0.01U_0402_25V7K~N
0.01U_0402_25V7K~N
1
PC1019
1
PC1017
2 2
2
@
2
0.1U_0402_25V7K~N
0.1U_0402_25V7K~N
1
PC1020
1
PC1018
2
@
2
3 3
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1 1 1
330U_D2_2V_Y
330U_D2_2V_Y
330U_D2_2V_Y
1 1 1
PC1024
PC1025
PC1026
+ + +
PC1021
PC1022
PC1023
+ + +
2 2 2@
2 2 2
4 4

PWR-PROCESSOR DECOUPLING
A B C D E
5 4 3 2 1
9HUVLRQFKDQJHOLVW3,5/LVW 3DJHRI

IRU+:
,WHP 5HDVRQIRUFKDQJH 3* 0RGLI\/LVW 'DWH 3KDVH
For share rom 28 Change SYS_PWRGD_EC from pin 86 to pin 32 12/17 DVT
D D
For 095VS_PWR_EN pull down 28 Add R207 12/17 DVT
For VBIAS first raise up

12,
Change U1895V, U35P, U1895P VBIAS from +5VALW to VL 12/17 DVT
32
For follow VIWGP design 27 Change JUSB3 pin define 12/18 DVT
For Audio Precision 31 Change CA36, CA46 from 1U to 2.2U 12/21 DVT
For SYS_PWRGD_EC pull down 28 Add R208 12/24 DVT
For share rom 28 Change R1575, R1576 to 100K 12/24 DVT
For reserve EC +3VL 28 Add J11, J12 and modify +3VALW to +3V_EC 12/24 DVT
05
C C
For share ROM 05 modify ROM net-name & resistor value 12/24 DVT
For common VIWGP design 22 modify R106, R107 to 22ohm 12/24 DVT
For power S3 reduction 28 Change EC_INVT_PWM to ADP_ID_CLOSE 12/25 DVT
For common VIWGP design 23 Change JODD1 symbol 12/27 DVT
For reserve wake on wlan function 26 Add R1500 12/27 DVT
For 1.5VS discharge 32 Change R339 to 0ohm, mount Q23 & R1461 12/29 DVT
For AMD suggest 4 Change R576 to 0ohm 12/29 DVT
For VGA sequence 12 Delete R123 & C40, change C28, C27 to 2200P 12/29 DVT
B B
For +3VALW APU Power Consumption 7 Add R582 01/03 DVT
For ESD request 22 Add C600, C601, PC6601, PC6602 01/03 DVT
28
40
For no support DC wake & LID function 28 Pull high only SMB & RST use +3V_EC, other use +3VALW 01/04 DVT
For reserve cost down experiment 30 Add R630, R643 01/04 DVT
For Common VIWGP 30 Change SW4,SW5,SW6,SW7 footprint 01/04 DVT
For instant plug/unplug AC has beep sound 31 @RA22 01/04 DVT

5
For Crystal Capactance fine tune
6
Modify C794,C795,C682,C686,CV36,CV37 value 01/09 DVT
A
12 A

PIR (PWR)
Custom
C38-G series Chief River Schematic1.0
5 4 3 2 1
5 4 3 2 1

IRU+:
For EMI request 30 Change L67 to EMICP@, Change R692,R687 to EMICU@ 02/02 PVT
D D
For Share ROM recoverable solution as 05 Add RP12 02/02 PVT

original method
For BIOS post time 06 Pull high PXS_PWREN to +3VS by RP14 02/02 PVT
For ZiZi noise 31 Change AVDD_HP from +3VS to +3VLP 02/02 PVT
For follow KABINI latest CRB 04 @ R576,C164,C342 02/02 PVT
For APU control PWM only 21 Delete R1465 02/02 PVT
For Corret Net-name to prevet confuse 04 Change TL_INVT_PWM, TL_ENVDD to APU_INVT_PWM, APU_ENVDD 02/02 PVT
21
For Reserve DDC CLK DATA pull high 22 Add R693, R697 02/02 PVT
C C
For Common Intel project 30 Change R623,R765,R303 to 620ohm 02/02 PVT
For Common Intel project 23 Reserve R551 02/02 PVT
For reduce BOM 31 Delete RA3, and Change RA4 to short-pad 02/05 PVT
For reduce BOM 26 Change R1498,R1499 from 0 ohm to 100 ohm 02/05 PVT
11
For reduce BOM
12
Change RV43,LV1,LV2,LV3,LV4,LV5,LV6,RV16,RV17,LV7,LV8,LV9,LV10 02/05 PVT
to short-pad
13
14
14
For better location
18
CV72 <-> CV171 ; CV60 <-> CV70 ; CV154 <-> CV191 02/05 PVT
19
B B
For reduce BOM 21 Change R1463 from 0 ohm to short-pad 02/06 PVT
For better audio precision performance 31 Change CA27,CA28 from 1U to 2.2U 02/08 PVT
For reduce BOM & layout concern 07 Delete C195 02/16 PVT
For test point request 22 Add T49, T58 on JCRT1 02/18 PVT
For ESD request 25 Add C173, C178 02/18 PVT

For reduce BOM 05 Change R112, R115, R116, R119, R125, R126 to short-pad 02/18 PVT
For Crystal timming 06 Change C682 from 18P to 22P 02/20 PVT
For ESD request 30 Change D24 from ESDU@ to ESDP@, Part number from SCA00000E00 02/23 PVT
to SCA00001G00
A
21 A
For EMI request 27 Change L58,L51,L55,L66,L67 from SM070000K00 to SM070000Z00 02/23 PVT
30

PIR (PWR)
Custom
5 4 3 2 1
5 4 3 2 1

IRU3:5
For Common Intel project 30 Change R623,R765,R303 to 649ohm 03/05 PreMP

D D
For VGA Clock Request 06 Reserve R578,R689 03/05 PreMP
For Reduce BOM 05 Change R103, R104 to short-pad 03/11 PreMP
For Reduce BOM 21 Change R696, R695, R813 to short-pad 03/11 PreMP
For Reduce BOM 23 Change R550 to short-pad 03/11 PreMP
For Reduce BOM 31 Change RA11 to short-pad 03/11 PreMP
C C
For ESD require 30 Add C185 03/25 PreMP
For Module Design 22 Change R693, R697 from 10k to 4.7k 03/25 PreMP
For ESD require 04 Add C195 03/26 PreMP
For Reduce BOM 04 @ RP11 03/26 PreMP
For Board ID 28 @ R1562 and change R1564 to 0ohm 03/28 PreMP

B B

A A

PIR (PWR)
Custom
5 4 3 2 1
5 4 3 2 1
Power-Up/Down Sequence
"Mars" has the following requirements with regards to power-supply
Ʉ
Mars XT VRAM STRAP sequencing to avoid damaging the ASIC:
All the ASIC supplies must reach their respective nominal voltages within 20 ms
of the start of the ramp-up sequence, though a shorter ramp-up duration is
Vendor PS_3[ 2 ] PS_3[ 1 ] PS_3[ 0 ] R_pu R_pd
Ʉ
preferred. The maximum slew rate on all rails is 50 mV/ȝs.
The external pull ups on the DDC/AUX signals (if applicable) should ramp up
Ʉ
D K4W2G1646E-BC1A 0 0 0 RV20 RV27
before or after both VDDC and VDD_CT have ramped up. D
SA000068U00 NC 4.75K VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
MT41J128M16JT-093G:K
SA000067500 0 0 1 RV20
8.45K
RV27
2K
Ʉ
should reach 90% before VDD_CT starts to ramp up (or vice versa).
For power down, reversing the ramp-up sequence is recommended.
2G H5TQ2G63DFR-N0C
SA000065300 0 1 0 RV20 RV27
4.53K 2K
H5TC2G63FFR-11C 1 0 0 RV20 RV27
SA00006H400 4.53K 4.99K

K4W1G1646G-BC11 0 1 1 RV20 RV27
VDDR3(3.3VGS)
SA00004GS00 6.98K 4.99K
1G PCIE_VDDC(0.95VGSV)
RV20 RV27
H5TQ1G63EFR-11C 1 1 1
SA000041SB0 4.75K NC
VDDR1(1.5VGS)
MS2G@ X7646738L01
C
MM2G@ X7646738L02 VDDC/VDDCI(1.12V)
C
OLDMH2G@ X7646738L09
NEWMH2G@ X7646738L10
MS1G@ X7646738L03 VDD_CT(1.8V)
MH1G@ X7646738L04
PERSTb
SUN PRO VRAM STRAP
REFCLK
Vendor PS_3[ 2 ] PS_3[ 1 ] PS_3[ 0 ] R_pu R_pd

Straps Reset
K4W4G1646B-HC11 0 0 0 RV20 RV27
SA000068R00 NC 4.75K Straps Valid

MT41K256M16HA-107G:E 0 0 1 RV20 RV27
2G SA000065D00
8.45K 2K Global ASIC Reset
B B
H5TQ4G63MFR-11C 0 1 0 RV20 RV27
SA00006DG00 4.53K 2K T4+16clock
K4W2G1646E-BC1A 0 1 1 RV20 RV27
SA000068U00 6.98K 4.99K

RV20 RV27
MT41J128M16JT-093G:K
1 1 0
1G SA000067500 3.4K 10K
RV20 RV27
H5TC2G63FFR-11C
SA00006H400 1 0 0 4.53K 4.99K
RV20 RV27
H5TQ2G63DFR-N0C
SA000065300 1 1 1 4.75K NC
A A
SS2G@ X7646738L05
SM2G@ X7646738L06
SH2G@ TBD
SS1G@ X7646738L07 Security Classification Compal Secret Data Compal Electronics, Inc.
SM1G@ X7646738L08 Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title
NEWSH1G@ X7646738L13 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
OLDSH1G@ X7647538L01 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
VAWGA/GB
5 4 3 2 1
A B C D E
EC_ON
B+ +3VLP
PU401
SY8208BQKC +3VALW
+EC_VCCA
LAN_PWR_ON#
+3V_LAN
P-CHANNEL
PMV65XP
1 1
SUSP#
U35P +3VS
TPS22966DPUR
PXS_PWREN
U315V +3VGS
TPS22966DPUR
SPOK
PU502 +1.8VALW
SY8033BDBC
SUSP#
U1895P +1.8VS
TPS22966DPUR
PXS_PWREN
U1895V +1.8VGS
TPS22966DPUR
2 EC_ON 2
+VL
PU402
SY8208CQKC
+5VALW
SUSP#
U35P +5VS
TPS22966DPUR
SUSP# / SYSON
+0.75VS
PU501
RT8207MZQW
+1.5V
SUSP#
P-CHANNEL +1.5VS
LP2301ALT1G
PXS_PWREN
U315V +1.5VGS
TPS22966DPUR
3 3
SPOK
PU601 +0.95VALW
TPS51212DSCR
SUSP#
U1895P +0.95VS
TPS22966DPUR
PXS_PWREN
U1895V +0.95VGS
TPS22966DPUR
EC_VGA_EN
PU801 +VGA_CORE
ISL62883CHRTZ
VR_ON
+APU_CORE
PU901
ISL62771HRTZ
+APU_CORE_NB
4 4
SPOK
PQ204 +VSB
TP0610K
Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date Deciphered Date Power Map
Custom VAWGA/GB 1.0
A B C D E
5 4 3 2 1
+3VALW B+ +5VALW
+3VALW / +1.8VALW / +1.5VALW / +0.95VALW
+3VS / +1.8VS / +1.5VS / +0.95VS
+3VLP +3VALW
+APU_CORE / +APU_CORE_NB
+3VGS / +1.5VGS
PU502 PU601 +RTCBATT
+1.8VGS / +0.95VGS
+1.8VALW +0.95VALW
V V V V +3VGS +VGA_CORE
D EC EC_RSMRST# 5 D
V V
3A 3B
PBTN_OUT# 6 APU 22
095_18ALW_PWR_EN PXS_RST# 23
V V
SLP_S3# / SLP_S5# 7 AND GPU_RST# GPU
V
GATE MarsXTX
V V
4A 5
B+ B+
KBRST# 10 20 APU_PCIE_RST#
3B 5
V
3A 3B 18 APU_PWRGD +3VS +1.5VA
PU402 PU401 SPOK
SYS_PWRGD_EC 17
14 VGA_PEWGD
V
+5VALW / VL +3VALW/+3VLP
V
V V
LPC_RST# 19
V
2A 2B EC_ON
WLAN / WiMAX
V
Mini-Express Card
1A ACIN
V V
B+ +5VS +3VS
PXS_PWREN 13
V
C C
ON/OFF
4A 1B
EC_VGA_EN 12
V
+5VS / +3VS / +1.8VS D4
V
+5VALW B+ PU801
AC MODE Diode
+VGA_CORE
VIN
V
095VS_PWR_EN 11
18 +1.8VALW +5VALW
+3V_LAN
APU_PWRGD 16
V
PU901 VGATE
V
BATT MODE 15 +APU_CORE /
VR_ON U1895V
BATT+ +APU_CORE_NB
V
V
+3VS +5VALW LAN
V
+1.8VGS
SYSON
SUSP#
+5VALW
RTC Battery LAN_PERST# 21
U315V
V
+CHGRTC_R 8 9
+3VGS
+3VALW +0.95VALW +5VALW
V
B
+5VALW +3VALW +5VALW U35P B
B+ +5VS
+CHGRTC_R +3VLP VIN BATT+ U1895V
V
+1.8VALW +5VALW
U35P +1.5V +5VALW
+0.95VGS
V
PU501 +3VS
V
PU102 PU301 +1.5V

+1.5V U1895P
V
+RTCBATT B+ U315V
V
+1.8VS
+1.5VGS
+3VALW
Q20
V
+5VALW +0.95VALW +5VALW

+1.5VS B+
MODEL NAME: PU501 U1895P

V
V
A
PCB NAME: +0.75VS +0.95VS A
REVISION:
DATE: 2011/11/23 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date Deciphered Date Title
Power sequence
COMPAL CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date: Sheet of
Rev
1.0
5 4 3 2 1

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A B C D E

AMD "Kabini" Platform

LA-9911P REV: 1.0

Security Classification Compal Secret Data Compal Electronics, Inc.

LVDS Conn. P21 DP0

LPC Gen3 Port 0 Port 1

Touch Pad Thermal Sensor

Int. MIC Int. Speaker Conn. Audio Combo Jacks

USB/B Security Classification Compal Secret Data Compal Electronics, Inc.

Voltage Rails BOARD ID Table

PX@ Common VGA circuit

Device Address HEX ESDP@ ESD pop component

UAPUA HDMI & LVDS should be reverse in KABINI:

X4@ FT3_BGA769 +APU_CORE_NB

R103 1 @ 2 0_0402_5% AY2 LPCCLK0

FT3 REV 0.51

R656 1 @ 2 100K_0402_5% EC_LID_OUT# <28>

CORE POWER OF APU RTC OF APU VDDBT_RTC_G

for Clear CMOS

INTEGRATED GPU POWER OF APU +3VALW/+3VS OF APU +3VALW

+APU_CORE_NB VDDCR_NB +3VS @

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VDD_095_5 AL21 FT3 REV 0.51 FT3 REV 0.51

AJ11 VDD_095_ALW_3 VDD_095_8 AM23

FT3 REV 0.51

+VREF_DQ +1.5V +1.5V

DDRAB_SMA12 83 VDD3 VDD4 84 DDRAB_SMA11

4 R70 205 206 4

+VREF_DQ +1.5V +1.5V

Security Classification Compal Secret Data Compal Electronics, Inc.

W38 U33 PCIE_GTX_ARX_P2 CV5 PX@ 1 2 0.1U_0402_16V7K AK35

K35 L30 MARS@ MARS-XT M2_FCBGA962

H35 J33 UV1 SUN@

PX@ MARS@ MARS-XT M2_FCBGA962

Security Classification Compal Secret Data Compal Electronics, Inc.

UV1B CONFIGURATION STRAPS RECOMMENDED SETTINGS

<29> RV17 1 @ 2 0_0402_5% THERM_D- AG29

RV31 10K_0402_5% AK30 QV3A @

+0.95VGS +SPLL_VDDC AK10

D PX@ PXS_PWREN# +1.8VALW VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

100K_0402_5% RV42 @ PX@ D

Issued Date 2012/07/03 Deciphered Date 2013/07/03 Title

(PCIE_VDDR:1.8V@100mA ) +PCIE_VDDR LV7

0.1u 1 1 VDDC T20

MARS@ MARS-XT M2_FCBGA962

Security Classification Compal Secret Data Compal Electronics, Inc.

DRAM_RST AH11 DRAM_RST#_R

MARS@ MARS-XT M2_FCBGA962 MARS@ MARS-XT M2_FCBGA962

Ball to RV57 < 1"

+1.5VGS +1.5VGS CV100 to RV53 < 1" +1.5VGS +1.5VGS

PX@ PX@ 40.2_0402_1% 40.2_0402_1%

PX@ 2 PX@ 2 PX@ PX@ 4.99K_0402_1% PX@ 2 PX@ PX@ 2 PX@

DRAM_RST# is a daisy-chain net that connects to all VRAM

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

VSSQ E8 NCZQ1 VSSQ E2

RV66 40.2_0402_1% MARS@ 4.99K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

+VREFC_B0 M8 E3 MDB19 +VREFC_B1 M8 E3 MDB26

<15> <15,19> M2 B2 B_BA0 M2 B2

J9 NC/CS1 VSSQ D1 J9 NC/CS1 VSSQ D1

Security Classification Compal Secret Data Compal Electronics, Inc.

+VREFC_B2 M8 E3 MDB33 +VREFC_B3 M8 E3 MDB55